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- sssp_facebook/command.txt +1 -0
- sssp_facebook/events.txt +9 -0
- sssp_facebook/fingerprint/bbfp +10 -0
- sssp_facebook/fingerprint/footprint_pieces/segment.0 +1 -0
- sssp_facebook/fingerprint/footprint_pieces/segment.1 +1 -0
- sssp_facebook/fingerprint/footprint_pieces/segment.2 +1 -0
- sssp_facebook/fingerprint/footprint_pieces/segment.3 +1 -0
- sssp_facebook/fingerprint/footprint_pieces/segment.4 +1 -0
- sssp_facebook/fingerprint/footprint_pieces/segment.5 +1 -0
- sssp_facebook/fingerprint/footprint_pieces/segment.6 +1 -0
- sssp_facebook/fingerprint/footprint_pieces/segment.7 +1 -0
- sssp_facebook/fingerprint/footprint_pieces/segment.8 +1 -0
- sssp_facebook/fingerprint/footprint_pieces/segment.9 +1 -0
- sssp_facebook/fingerprint/pieces/bbfp +10 -0
- sssp_facebook/fingerprint/pieces/segment.0 +1 -0
- sssp_facebook/fingerprint/pieces/segment.1 +1 -0
- sssp_facebook/fingerprint/pieces/segment.2 +1 -0
- sssp_facebook/fingerprint/pieces/segment.3 +1 -0
- sssp_facebook/fingerprint/pieces/segment.4 +1 -0
- sssp_facebook/fingerprint/pieces/segment.5 +1 -0
- sssp_facebook/fingerprint/pieces/segment.6 +1 -0
- sssp_facebook/fingerprint/pieces/segment.7 +1 -0
- sssp_facebook/fingerprint/pieces/segment.8 +1 -0
- sssp_facebook/fingerprint/pieces/segment.9 +1 -0
- sssp_facebook/fingerprint/run_0/PARAMS.in +268 -0
- sssp_facebook/fingerprint/run_0/PARAMS.out +1102 -0
- sssp_facebook/fingerprint/run_0/sim.log +44 -0
- sssp_facebook/fingerprint/run_1/PARAMS.in +268 -0
- sssp_facebook/fingerprint/run_1/PARAMS.out +1102 -0
- sssp_facebook/fingerprint/run_1/sim.log +44 -0
- sssp_facebook/fingerprint/run_2/PARAMS.in +268 -0
- sssp_facebook/fingerprint/run_2/PARAMS.out +1102 -0
- sssp_facebook/fingerprint/run_2/sim.log +279 -0
- sssp_facebook/fingerprint/run_3/PARAMS.in +268 -0
- sssp_facebook/fingerprint/run_3/PARAMS.out +1102 -0
- sssp_facebook/fingerprint/run_3/sim.log +59 -0
- sssp_facebook/fingerprint/run_4/PARAMS.in +268 -0
- sssp_facebook/fingerprint/run_4/PARAMS.out +1102 -0
- sssp_facebook/fingerprint/run_4/sim.log +242 -0
- sssp_facebook/fingerprint/run_5/PARAMS.in +268 -0
- sssp_facebook/fingerprint/run_5/PARAMS.out +1102 -0
- sssp_facebook/fingerprint/run_5/sim.log +59 -0
- sssp_facebook/fingerprint/run_6/PARAMS.in +268 -0
- sssp_facebook/fingerprint/run_6/PARAMS.out +1102 -0
- sssp_facebook/fingerprint/run_6/sim.log +59 -0
- sssp_facebook/fingerprint/run_7/PARAMS.in +268 -0
- sssp_facebook/fingerprint/run_7/PARAMS.out +1102 -0
- sssp_facebook/fingerprint/run_7/sim.log +59 -0
- sssp_facebook/fingerprint/run_8/PARAMS.in +268 -0
- sssp_facebook/fingerprint/run_8/PARAMS.out +1102 -0
sssp_facebook/command.txt
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/users/deepmish/CRONO/apps/sssp/sssp 1 1 /users/deepmish/dc_datasets/snap/facebook_combined.txt
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sssp_facebook/events.txt
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workload=sssp_facebook
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start_utc=2026-07-18T05:06:15,317903920+00:00
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exit_after_refs=50000000
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target_fetched_instructions=100000000
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skip_instructions=7865949126
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chunk_instructions=10000000
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trace_exit_status=0
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end_utc=2026-07-18T05:06:25,172534868+00:00
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validated_fetched_instructions=96130951
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sssp_facebook/fingerprint/bbfp
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T:3:28 :4:4 :5:3 :6:6 :7:44 :1:3806220 :2:3839050 :8:24621 :9:32828 :10:507279 :11:708604 :12:1014558 :13:65656 :14:24 :15:12 :16:12 :17:32 :18:68 :19:8 :20:12 :21:3 :22:16 :23:9 :24:3 :25:3 :26:3 :27:4 :28:5 :29:3 :30:294 :31:14 :32:70 :33:126 :34:84 :35:28 :36:28 :37:84 :38:154
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T:3:6 :6:2 :7:11 :1:4410266 :2:4426420 :39:2 :8:12117 :9:16156 :10:250755 :11:350204 :12:501510 :13:32312 :14:6 :15:3 :16:3 :17:8 :18:17 :19:2 :20:4 :22:4 :23:3 :30:63 :31:3 :32:15 :33:27 :34:18 :35:6 :36:6 :37:18 :38:33
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T:1:3012350 :2:3015816 :8:2598 :9:3464 :10:19920 :41:2 :11:30024 :12:39840 :13:6936
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sssp_facebook/fingerprint/footprint_pieces/segment.0
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T:140737284519856:1250000 :140737284519859:1250000 :140737284519863:1250000 :140737284519867:1250000 :140737284519873:1250000 :140737284519880:1250000 :140737284519884:1250000 :140737284519887:1250000
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sssp_facebook/fingerprint/footprint_pieces/segment.1
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sssp_facebook/fingerprint/footprint_pieces/segment.2
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sssp_facebook/fingerprint/footprint_pieces/segment.3
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sssp_facebook/fingerprint/footprint_pieces/segment.4
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sssp_facebook/fingerprint/footprint_pieces/segment.5
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T:140737284514384:14 :140737284514388:14 :140737284519785:1 :140737284519793:1 :140737284519795:1 :140737284519799:1 :140737284519805:1 :140737284519808:4 :140737284519810:4 :140737284519816:4 :140737284519820:4 :140737284519823:4 :140737284519827:4 :140737284519829:4 :140737284519832:4 :140737284519835:4 :140737284519839:4 :140737284519842:4 :140737284519845:4 :140737284519848:4 :140737284519856:964836 :140737284519859:964836 :140737284519863:964837 :140737284519867:964837 :140737284519873:972177 :140737284519880:972177 :140737284519884:972177 :140737284519887:972177 :140737284519889:7341 :140737284519894:7341 :140737284519897:7341 :140737284519899:7341 :140737284519902:7341 :140737284519904:7341 :140737284519907:7341 :140737284519912:162453 :140737284519916:162452 :140737284519920:162452 :140737284519922:169645 :140737284519926:169645 :140737284519930:169645 :140737284519935:169645 :140737284519937:162453 :140737284519941:162453 :140737284519944:162453 :140737284519948:162453 :140737284519951:162453 :140737284519955:162453 :140737284520048:7340 :140737284520051:7340 :140737284520054:7340 :140737284520057:7340 :140737284520061:7340 :140737284520064:7340 :140737284520067:7340 :140737284520071:7340 :140737284520077:4 :140737284520080:4 :140737284520084:4 :140737284520087:4 :140737284520090:4 :140737284520094:4 :140737284520378:4 :140737284520383:4 :140737284520387:4 :140737284520392:4 :140737284520396:4 :140737284520398:4 :140737284520400:4 :140737284520404:4 :140737284520411:4 :140737284520413:4 :140737284520416:4 :140737284520422:4 :140737284520427:4 :140737284520431:4 :140737284520436:4 :140737284520442:4 :140737284520448:4 :140737284520452:4 :140737284520456:4 :140737284520460:4 :140737284520466:4 :140737284520470:4 :140737284520474:4 :140737284520482:4 :140737284520486:4 :140737284520490:4 :140737284520494:4 :140737284520496:4 :140737284520499:4 :140737284520501:4 :140737284520503:4 :140737284520505:4 :140737284520509:4 :140737284520511:3 :140737284520515:4 :140737284520520:4 :140737284520524:4 :140737284520529:4 :140737284520535:4 :140737284520537:4 :140737284520541:4 :140737284520543:3 :140737284520547:3 :140737284520551:3 :140737284520576:1 :140737284520580:1 :140737284520590:1 :140737284520592:1 :140737284520597:1 :140737284520601:1 :140737284520606:1 :140737284520610:1 :140737284520612:1 :140737284520614:1 :140737284520619:1 :140737284520623:1 :140737284520629:1 :140737284520631:1 :140737284520641:1 :140737284520651:1 :140737284520656:1 :140737284520660:1 :140737284520665:1 :140737284520671:1 :140737284520673:1 :140737340791056:14 :140737340791060:14 :140737340791062:14 :140737340791065:14 :140737340791067:14 :140737340791073:14 :140737340791075:14 :140737340791081:14 :140737340791082:14 :140737340791087:14 :140737340791088:14 :140737340791094:14 :140737340791099:14 :140737340791101:14 :140737340791105:14 :140737340791108:14 :140737340791111:14 :140737340791115:14 :140737340791118:14 :140737340791120:14 :140737340791123:14 :140737340791125:14 :140737340791199:14 :140737340791203:14 :140737340791207:14 :140737340791211:14 :140737340791214:14 :140737340791220:14 :140737340791223:14 :140737340791225:14 :140737340791228:14 :140737340791231:14 :140737340791233:14 :140737340791236:14 :140737340791241:14 :140737340791243:14 :140737340791245:14 :140737340791249:14 :140737340791252:14 :140737340791257:14 :140737340791262:14 :140737340791266:14 :140737340791268:14 :140737340791274:14 :140737340791276:14 :140737340791279:14 :140737340791360:14 :140737340791364:14 :140737340791369:14 :140737340791373:14 :140737340791376:14 :140737340791378:14 :140737340791380:14 :140737340791382:14 :140737340791385:14 :140737340791386:14 :140737340791387:14 :140737340791390:14 :140737340791392:14 :140737340791394:14 :140737340791396:14 :140737340791399:14 :140737340791401:14
|
sssp_facebook/fingerprint/footprint_pieces/segment.9
ADDED
|
@@ -0,0 +1 @@
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| 1 |
+
T:140737284519856:753088 :140737284519859:753088 :140737284519863:753087 :140737284519867:753087 :140737284519873:753954 :140737284519880:753954 :140737284519884:753954 :140737284519887:753954 :140737284519889:866 :140737284519894:866 :140737284519897:866 :140737284519899:866 :140737284519902:866 :140737284519904:866 :140737284519907:866 :140737284519912:6640 :140737284519916:6641 :140737284519920:6641 :140737284519922:7506 :140737284519926:7506 :140737284519930:7506 :140737284519935:7506 :140737284519937:6640 :140737284519941:6640 :140737284519944:6640 :140737284519948:6640 :140737284519951:6640 :140737284519955:6640 :140737284520048:867 :140737284520051:867 :140737284520054:867 :140737284520057:867 :140737284520061:867 :140737284520064:867 :140737284520067:867 :140737284520071:867
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sssp_facebook/fingerprint/pieces/bbfp
ADDED
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@@ -0,0 +1,10 @@
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+
T:1:5000000 :2:5000000
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| 2 |
+
T:1:5000000 :2:5000000
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| 3 |
+
T:3:28 :4:4 :5:3 :6:6 :7:44 :1:3806220 :2:3839050 :8:24621 :9:32828 :10:507279 :11:708604 :12:1014558 :13:65656 :14:24 :15:12 :16:12 :17:32 :18:68 :19:8 :20:12 :21:3 :22:16 :23:9 :24:3 :25:3 :26:3 :27:4 :28:5 :29:3 :30:294 :31:14 :32:70 :33:126 :34:84 :35:28 :36:28 :37:84 :38:154
|
| 4 |
+
T:1:5000000 :2:4999998 :39:2
|
| 5 |
+
T:3:6 :6:2 :7:11 :1:4410266 :2:4426420 :39:2 :8:12117 :9:16156 :10:250755 :11:350204 :12:501510 :13:32312 :14:6 :15:3 :16:3 :17:8 :18:17 :19:2 :20:4 :22:4 :23:3 :30:63 :31:3 :32:15 :33:27 :34:18 :35:6 :36:6 :37:18 :38:33
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| 6 |
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T:1:4999998 :40:2 :2:5000000
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| 7 |
+
T:1:4999998 :40:2 :2:5000000
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| 8 |
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T:1:4999998 :40:2 :2:5000000
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| 9 |
+
T:3:28 :4:4 :5:3 :6:6 :7:44 :1:3859344 :40:2 :2:3888708 :8:22023 :9:29364 :10:487357 :11:678580 :12:974718 :13:58720 :14:24 :15:12 :16:12 :17:32 :18:68 :19:8 :20:12 :21:3 :22:16 :23:9 :24:3 :25:3 :26:3 :27:4 :28:5 :29:3 :30:294 :31:14 :32:70 :33:126 :34:84 :35:28 :36:28 :37:84 :38:154
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| 10 |
+
T:1:3012350 :2:3015816 :8:2598 :9:3464 :10:19920 :41:2 :11:30024 :12:39840 :13:6936
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sssp_facebook/fingerprint/pieces/segment.0
ADDED
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T:140737284519856:5000000 :140737284519873:5000000
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sssp_facebook/fingerprint/pieces/segment.1
ADDED
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T:140737284519856:5000000 :140737284519873:5000000
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sssp_facebook/fingerprint/pieces/segment.2
ADDED
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T:140737284514384:28 :140737284519785:4 :140737284519805:3 :140737284519808:6 :140737284519816:44 :140737284519856:3806220 :140737284519873:3839050 :140737284519889:24621 :140737284519899:32828 :140737284519912:507279 :140737284519922:708604 :140737284519937:1014558 :140737284520048:65656 :140737284520077:24 :140737284520378:12 :140737284520392:12 :140737284520400:32 :140737284520436:68 :140737284520505:8 :140737284520511:12 :140737284520515:3 :140737284520529:16 :140737284520543:9 :140737284520576:3 :140737284520592:3 :140737284520606:3 :140737284520614:4 :140737284520631:5 :140737284520665:3 :140737340791056:294 :140737340791125:14 :140737340791199:70 :140737340791220:126 :140737340791245:84 :140737340791268:28 :140737340791276:28 :140737340791360:84 :140737340791380:154
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sssp_facebook/fingerprint/pieces/segment.3
ADDED
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T:140737284519856:5000000 :140737284519873:4999998 :140737284519884:2
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sssp_facebook/fingerprint/pieces/segment.4
ADDED
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T:140737284514384:6 :140737284519808:2 :140737284519816:11 :140737284519856:4410266 :140737284519873:4426420 :140737284519884:2 :140737284519889:12117 :140737284519899:16156 :140737284519912:250755 :140737284519922:350204 :140737284519937:501510 :140737284520048:32312 :140737284520077:6 :140737284520378:3 :140737284520392:3 :140737284520400:8 :140737284520436:17 :140737284520505:2 :140737284520511:4 :140737284520529:4 :140737284520543:3 :140737340791056:63 :140737340791125:3 :140737340791199:15 :140737340791220:27 :140737340791245:18 :140737340791268:6 :140737340791276:6 :140737340791360:18 :140737340791380:33
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sssp_facebook/fingerprint/pieces/segment.5
ADDED
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T:140737284519856:4999998 :140737284519863:2 :140737284519873:5000000
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sssp_facebook/fingerprint/pieces/segment.6
ADDED
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T:140737284519856:4999998 :140737284519863:2 :140737284519873:5000000
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sssp_facebook/fingerprint/pieces/segment.7
ADDED
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T:140737284519856:4999998 :140737284519863:2 :140737284519873:5000000
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sssp_facebook/fingerprint/pieces/segment.8
ADDED
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T:140737284514384:28 :140737284519785:4 :140737284519805:3 :140737284519808:6 :140737284519816:44 :140737284519856:3859344 :140737284519863:2 :140737284519873:3888708 :140737284519889:22023 :140737284519899:29364 :140737284519912:487357 :140737284519922:678580 :140737284519937:974718 :140737284520048:58720 :140737284520077:24 :140737284520378:12 :140737284520392:12 :140737284520400:32 :140737284520436:68 :140737284520505:8 :140737284520511:12 :140737284520515:3 :140737284520529:16 :140737284520543:9 :140737284520576:3 :140737284520592:3 :140737284520606:3 :140737284520614:4 :140737284520631:5 :140737284520665:3 :140737340791056:294 :140737340791125:14 :140737340791199:70 :140737340791220:126 :140737340791245:84 :140737340791268:28 :140737340791276:28 :140737340791360:84 :140737340791380:154
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sssp_facebook/fingerprint/pieces/segment.9
ADDED
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T:140737284519856:3012350 :140737284519873:3015816 :140737284519889:2598 :140737284519899:3464 :140737284519912:19920 :140737284519916:2 :140737284519922:30024 :140737284519937:39840 :140737284520048:6936
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sssp_facebook/fingerprint/run_0/PARAMS.in
ADDED
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| 1 |
+
# File : PARAMS.golden_cove
|
| 2 |
+
# Date : 02/27/25
|
| 3 |
+
# Description : Golden Cove Configuration
|
| 4 |
+
# Author : Surim Oh <[email protected]>
|
| 5 |
+
#
|
| 6 |
+
# Based on documentation found here:
|
| 7 |
+
# https://en.wikipedia.org/wiki/Golden_Cove
|
| 8 |
+
# https://en.wikichip.org/wiki/intel/microarchitectures/golden_cove
|
| 9 |
+
# https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/3
|
| 10 |
+
|
| 11 |
+
## Simulation Parameters
|
| 12 |
+
--mode full
|
| 13 |
+
--model cmp
|
| 14 |
+
--sim_limit none
|
| 15 |
+
|
| 16 |
+
## Core Parameters
|
| 17 |
+
|
| 18 |
+
# Femptoseconds, 3.2GHz, used for energy estimates.
|
| 19 |
+
--chip_cycle_time 312500
|
| 20 |
+
|
| 21 |
+
|
| 22 |
+
### Fetch Stage
|
| 23 |
+
--fetch_off_path_ops 1
|
| 24 |
+
|
| 25 |
+
#### ICache
|
| 26 |
+
--icache_size 32768
|
| 27 |
+
--icache_assoc 8
|
| 28 |
+
--icache_line_size 64
|
| 29 |
+
|
| 30 |
+
### Uop Cache
|
| 31 |
+
# inclusive w/ L1i
|
| 32 |
+
--uop_cache_enable 1
|
| 33 |
+
--uop_cache_width 8
|
| 34 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 35 |
+
--uop_cache_assoc 8
|
| 36 |
+
--iprf_on_uop_cache_hit 1
|
| 37 |
+
|
| 38 |
+
### Branch Predictor
|
| 39 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 40 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 41 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 42 |
+
--bp_mech tage64k
|
| 43 |
+
|
| 44 |
+
|
| 45 |
+
#### BTB
|
| 46 |
+
|
| 47 |
+
# TODO
|
| 48 |
+
# multi-level BTB
|
| 49 |
+
# 128 entry L0 BTB
|
| 50 |
+
# 6144 entry L1 BTB
|
| 51 |
+
# 12888 entry L2 BTB
|
| 52 |
+
# ~2 entry Return Stack
|
| 53 |
+
# roughly 2x8192 for now
|
| 54 |
+
# BTB model to use.
|
| 55 |
+
--btb_mech generic
|
| 56 |
+
--btb_entries 12288
|
| 57 |
+
--btb_assoc 4
|
| 58 |
+
--btb_main_latency 3
|
| 59 |
+
--btb_l0_present 1
|
| 60 |
+
--btb_l0_entries 128
|
| 61 |
+
--btb_l0_assoc 4
|
| 62 |
+
--btb_l0_latency 1
|
| 63 |
+
--btb_l1_present 1
|
| 64 |
+
--btb_l1_entries 6144
|
| 65 |
+
--btb_l1_assoc 4
|
| 66 |
+
--btb_l1_latency 2
|
| 67 |
+
|
| 68 |
+
# Allow the BTB to be updated by off path ops.
|
| 69 |
+
--btb_off_path_writes 1
|
| 70 |
+
|
| 71 |
+
# NT branches are not inserted in BTB, but do not trigger resteer
|
| 72 |
+
# since we continue without a control flow change
|
| 73 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 74 |
+
|
| 75 |
+
#### CRS
|
| 76 |
+
|
| 77 |
+
# Enable return stack
|
| 78 |
+
--enable_crs 1
|
| 79 |
+
--crs_entries 128
|
| 80 |
+
--crs_realistic 1
|
| 81 |
+
|
| 82 |
+
### iBP
|
| 83 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 84 |
+
--ibtb_mech tc_tagged
|
| 85 |
+
# iBTB Model. tc_tagless, tc_tagged, tc_hybrid.
|
| 86 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 87 |
+
--tc_entries 4096
|
| 88 |
+
--tc_assoc 4
|
| 89 |
+
|
| 90 |
+
### Decode Stage
|
| 91 |
+
--decode_width 6
|
| 92 |
+
--decode_cycles 5
|
| 93 |
+
|
| 94 |
+
### Instruction Decode Queue
|
| 95 |
+
--idq_size 144
|
| 96 |
+
|
| 97 |
+
### Map Stage
|
| 98 |
+
--map_cycles 5
|
| 99 |
+
|
| 100 |
+
# register renaming table
|
| 101 |
+
--reg_renaming_scheme 1
|
| 102 |
+
--reg_table_integer_physical_size 280
|
| 103 |
+
--reg_table_vector_physical_size 332
|
| 104 |
+
|
| 105 |
+
### Issue Stage
|
| 106 |
+
|
| 107 |
+
# Max number of instructions to be renamed, and issued per cycle.
|
| 108 |
+
--issue_width 6
|
| 109 |
+
|
| 110 |
+
--rs_fill_width 0
|
| 111 |
+
# rs_sizes ~205 in total, and they are split into three different reservation stations (RS1, RS2, RS3) where each has 97, 70, 38 entries respectively
|
| 112 |
+
# original architecture
|
| 113 |
+
# RS1 connected to port 0,1,5,6,10
|
| 114 |
+
# RS2 connected to port 2,3,11
|
| 115 |
+
# RS3 connected to port 7,8,4,9
|
| 116 |
+
# scarab does not split ST AGU port and ST port, merge them
|
| 117 |
+
# adjusted architecture to scarab ST AGU (port 4 and 9 removed. rs_size reduced to 186 from 205)
|
| 118 |
+
# RS1 connected to port 0,1,4,5,8
|
| 119 |
+
# RS2 connected to port 2,3,9
|
| 120 |
+
# RS3 connected to port 6,7 (port 4,9 removed, entries reduced to 19 from 38)
|
| 121 |
+
--rs_sizes 97 70 19
|
| 122 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 123 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 124 |
+
|
| 125 |
+
### Exec Stage
|
| 126 |
+
|
| 127 |
+
### DCache
|
| 128 |
+
--dcache_size 49152
|
| 129 |
+
--dcache_read_ports 1
|
| 130 |
+
--dcache_write_ports 1
|
| 131 |
+
--dcache_banks 8
|
| 132 |
+
--dcache_assoc 12
|
| 133 |
+
--dcache_line_size 64
|
| 134 |
+
--dcache_cycles 5
|
| 135 |
+
|
| 136 |
+
### Reorder/Retire Stage
|
| 137 |
+
|
| 138 |
+
# Max number of instructions to be retired per cycle.
|
| 139 |
+
--node_ret_width 8
|
| 140 |
+
--node_table_size 512
|
| 141 |
+
|
| 142 |
+
# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does
|
| 143 |
+
--stores_do_not_block_window 1
|
| 144 |
+
|
| 145 |
+
# TODO: confirm what this knob does
|
| 146 |
+
--prefs_do_not_block_window 1
|
| 147 |
+
|
| 148 |
+
|
| 149 |
+
## Uncore
|
| 150 |
+
|
| 151 |
+
### Mid-level cache
|
| 152 |
+
|
| 153 |
+
# Enable use of a midlevel cache between i/d and L1
|
| 154 |
+
# client 1.25 MiB (1310720 bytes) per core, 8-way, 15 cycles
|
| 155 |
+
# server 2 MiB (2097000 bytes) per core, 8-way, 16 cycles
|
| 156 |
+
--mlc_present 1
|
| 157 |
+
--mlc_size 2097000
|
| 158 |
+
--mlc_assoc 8
|
| 159 |
+
--mlc_cycles 16
|
| 160 |
+
|
| 161 |
+
|
| 162 |
+
### LLC
|
| 163 |
+
# 3 MiB per core, 16-way
|
| 164 |
+
--l1_size 3145728
|
| 165 |
+
--l1_banks 8
|
| 166 |
+
--l1_cycles 36 // just a guess
|
| 167 |
+
--l1_assoc 16
|
| 168 |
+
--l1_line_size 64
|
| 169 |
+
--l1_interleave_factor 64
|
| 170 |
+
|
| 171 |
+
|
| 172 |
+
### prefetcher
|
| 173 |
+
# Kept same as Kaby Lake
|
| 174 |
+
--pref_framework_on 1
|
| 175 |
+
--pref_stream_on 1
|
| 176 |
+
--pref_train_on_pref_misses 0
|
| 177 |
+
--pref_oracle_train 0
|
| 178 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 179 |
+
|
| 180 |
+
--stream_length 64
|
| 181 |
+
--stream_prefetch_n 4
|
| 182 |
+
--stream_start_dis 1
|
| 183 |
+
--stream_train_num 4
|
| 184 |
+
--stream_create_on_dc_miss 0
|
| 185 |
+
--stream_create_on_l1_miss 1
|
| 186 |
+
|
| 187 |
+
--pref_throttlefb_on=1
|
| 188 |
+
--pref_acc_thresh_1=0.75
|
| 189 |
+
--pref_acc_thresh_2=0.4
|
| 190 |
+
--pref_acc_thresh_3=0.4
|
| 191 |
+
--pref_timely_thresh=0.01
|
| 192 |
+
--pref_polpf_thresh=0.005
|
| 193 |
+
--pref_update_interval=8192
|
| 194 |
+
|
| 195 |
+
--mem_req_buffer_pref_watermark 4
|
| 196 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 197 |
+
|
| 198 |
+
### Memory
|
| 199 |
+
# Kept same as Kaby Lake
|
| 200 |
+
--addr_translation random
|
| 201 |
+
|
| 202 |
+
--mem_priority_ifetch 0
|
| 203 |
+
--mem_priority_dfetch 1
|
| 204 |
+
--mem_priority_dstore 2
|
| 205 |
+
--mem_priority_iprf 3
|
| 206 |
+
--mem_priority_dprf 4
|
| 207 |
+
--mem_priority_wb 5
|
| 208 |
+
--mem_priority_wb_nodirty 5
|
| 209 |
+
|
| 210 |
+
--mem_req_buffer_entries 32
|
| 211 |
+
--bus_width_in_bytes 8
|
| 212 |
+
|
| 213 |
+
--ramulator_standard DDR4
|
| 214 |
+
--ramulator_speed DDR4_2400R
|
| 215 |
+
--ramulator_org DDR4_8Gb_x8
|
| 216 |
+
--ramulator_channels 1
|
| 217 |
+
--ramulator_ranks 1
|
| 218 |
+
--ramulator_bankgroups 4
|
| 219 |
+
--ramulator_banks 4
|
| 220 |
+
--ramulator_chip_width 8
|
| 221 |
+
--ramulator_rows 65536
|
| 222 |
+
--ramulator_cols 1024
|
| 223 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 224 |
+
--ramulator_readq_entries 32
|
| 225 |
+
--ramulator_writeq_entries 32
|
| 226 |
+
--ramulator_record_cmd_trace FALSE
|
| 227 |
+
--ramulator_print_cmd_trace FALSE
|
| 228 |
+
--ramulator_tCK 833333
|
| 229 |
+
--ramulator_tCL 16
|
| 230 |
+
--ramulator_tCCD 6
|
| 231 |
+
--ramulator_tCCDS 4
|
| 232 |
+
--ramulator_tCCDL 6
|
| 233 |
+
--ramulator_tCWL 12
|
| 234 |
+
--ramulator_tBL 4
|
| 235 |
+
--ramulator_tWTR 9
|
| 236 |
+
--ramulator_tWTRS 3
|
| 237 |
+
--ramulator_tWTRL 9
|
| 238 |
+
--ramulator_tRP 16
|
| 239 |
+
--ramulator_tRPpb 16
|
| 240 |
+
--ramulator_tRPab 16
|
| 241 |
+
--ramulator_tRCD 16
|
| 242 |
+
--ramulator_tRCDR 16
|
| 243 |
+
--ramulator_tRCDW 16
|
| 244 |
+
--ramulator_tRAS 39
|
| 245 |
+
--dram_tech_in_nm 32
|
| 246 |
+
|
| 247 |
+
## Other
|
| 248 |
+
|
| 249 |
+
|
| 250 |
+
### Debug
|
| 251 |
+
--debug_inst_start 0
|
| 252 |
+
--debug_inst_stop -1
|
| 253 |
+
--debug_cycle_start 0
|
| 254 |
+
--debug_cycle_stop -1
|
| 255 |
+
|
| 256 |
+
|
| 257 |
+
## Stats and Params
|
| 258 |
+
--dump_params 1
|
| 259 |
+
--dump_stats 1
|
| 260 |
+
--dump_trace 0
|
| 261 |
+
|
| 262 |
+
####################################
|
| 263 |
+
--set_off_path_confirmed 1
|
| 264 |
+
|
| 265 |
+
--order_beyond_bus 1
|
| 266 |
+
|
| 267 |
+
--mem_ooo_stores 1
|
| 268 |
+
--mem_obey_store_dep 1
|
sssp_facebook/fingerprint/run_0/PARAMS.out
ADDED
|
@@ -0,0 +1,1102 @@
|
|
|
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|
| 1 |
+
--mode trace_bbv_distributed
|
| 2 |
+
--model cmp
|
| 3 |
+
--frontend memtrace
|
| 4 |
+
--sim_limit none
|
| 5 |
+
--memtrace_roi_begin 1
|
| 6 |
+
--memtrace_roi_end 10000000
|
| 7 |
+
--use_fetched_count 1
|
| 8 |
+
--dump_params 1
|
| 9 |
+
--dump_stats 1
|
| 10 |
+
--dump_trace 0
|
| 11 |
+
--trace_bbv_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.0
|
| 12 |
+
--trace_footprint_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.0
|
| 13 |
+
--segment_instr_count 10000000
|
| 14 |
+
--mlc_present 1
|
| 15 |
+
--mlc_size 2097000
|
| 16 |
+
--mlc_assoc 8
|
| 17 |
+
--mlc_cycles 16
|
| 18 |
+
--l1_size 3145728
|
| 19 |
+
--l1_assoc 16
|
| 20 |
+
--l1_line_size 64
|
| 21 |
+
--l1_cycles 36 // just a guess
|
| 22 |
+
--l1_banks 8
|
| 23 |
+
--l1_interleave_factor 64
|
| 24 |
+
--addr_translation random
|
| 25 |
+
--icache_size 32768
|
| 26 |
+
--icache_assoc 8
|
| 27 |
+
--icache_line_size 64
|
| 28 |
+
--uop_cache_enable 1
|
| 29 |
+
--uop_cache_width 8
|
| 30 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 31 |
+
--uop_cache_assoc 8
|
| 32 |
+
--iprf_on_uop_cache_hit 1
|
| 33 |
+
--dcache_size 49152
|
| 34 |
+
--dcache_assoc 12
|
| 35 |
+
--dcache_line_size 64
|
| 36 |
+
--dcache_cycles 5
|
| 37 |
+
--dcache_read_ports 1
|
| 38 |
+
--dcache_write_ports 1
|
| 39 |
+
--dcache_banks 8
|
| 40 |
+
--mem_ooo_stores 1
|
| 41 |
+
--mem_obey_store_dep 1
|
| 42 |
+
--mem_req_buffer_entries 32
|
| 43 |
+
--mem_priority_ifetch 0
|
| 44 |
+
--mem_priority_dfetch 1
|
| 45 |
+
--mem_priority_dstore 2
|
| 46 |
+
--mem_priority_iprf 3
|
| 47 |
+
--mem_priority_dprf 4
|
| 48 |
+
--mem_priority_wb 5
|
| 49 |
+
--mem_priority_wb_nodirty 5
|
| 50 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 51 |
+
--mem_req_buffer_pref_watermark 4
|
| 52 |
+
--order_beyond_bus 1
|
| 53 |
+
--set_off_path_confirmed 1
|
| 54 |
+
--ramulator_standard DDR4
|
| 55 |
+
--ramulator_speed DDR4_2400R
|
| 56 |
+
--ramulator_org DDR4_8Gb_x8
|
| 57 |
+
--ramulator_channels 1
|
| 58 |
+
--ramulator_ranks 1
|
| 59 |
+
--ramulator_bankgroups 4
|
| 60 |
+
--ramulator_banks 4
|
| 61 |
+
--ramulator_chip_width 8
|
| 62 |
+
--bus_width_in_bytes 8
|
| 63 |
+
--ramulator_rows 65536
|
| 64 |
+
--ramulator_cols 1024
|
| 65 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 66 |
+
--ramulator_readq_entries 32
|
| 67 |
+
--ramulator_writeq_entries 32
|
| 68 |
+
--ramulator_record_cmd_trace FALSE
|
| 69 |
+
--ramulator_print_cmd_trace FALSE
|
| 70 |
+
--ramulator_tCK 833333
|
| 71 |
+
--ramulator_tCL 16
|
| 72 |
+
--ramulator_tCCD 6
|
| 73 |
+
--ramulator_tCCDS 4
|
| 74 |
+
--ramulator_tCCDL 6
|
| 75 |
+
--ramulator_tCWL 12
|
| 76 |
+
--ramulator_tBL 4
|
| 77 |
+
--ramulator_tWTR 9
|
| 78 |
+
--ramulator_tWTRS 3
|
| 79 |
+
--ramulator_tWTRL 9
|
| 80 |
+
--ramulator_tRP 16
|
| 81 |
+
--ramulator_tRPpb 16
|
| 82 |
+
--ramulator_tRPab 16
|
| 83 |
+
--ramulator_tRCD 16
|
| 84 |
+
--ramulator_tRCDR 16
|
| 85 |
+
--ramulator_tRCDW 16
|
| 86 |
+
--ramulator_tRAS 39
|
| 87 |
+
--dram_tech_in_nm 32
|
| 88 |
+
--chip_cycle_time 312500
|
| 89 |
+
--issue_width 6
|
| 90 |
+
--rs_fill_width 0
|
| 91 |
+
--node_table_size 512
|
| 92 |
+
--node_ret_width 8
|
| 93 |
+
--decode_width 6
|
| 94 |
+
--idq_size 144
|
| 95 |
+
--reg_renaming_scheme 1
|
| 96 |
+
--reg_table_integer_physical_size 280
|
| 97 |
+
--reg_table_vector_physical_size 332
|
| 98 |
+
--rs_sizes 97 70 19
|
| 99 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 100 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 101 |
+
--decode_cycles 5
|
| 102 |
+
--map_cycles 5
|
| 103 |
+
--fetch_off_path_ops 1
|
| 104 |
+
--stores_do_not_block_window 1
|
| 105 |
+
--prefs_do_not_block_window 1
|
| 106 |
+
--cbp_trace_r0 /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 107 |
+
--debug_cycle_start 0
|
| 108 |
+
--debug_cycle_stop -1
|
| 109 |
+
--debug_inst_start 0
|
| 110 |
+
--debug_inst_stop -1
|
| 111 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 112 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 113 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 114 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 115 |
+
--bp_mech tage64k
|
| 116 |
+
--btb_mech generic
|
| 117 |
+
--btb_entries 12288
|
| 118 |
+
--btb_assoc 4
|
| 119 |
+
--btb_off_path_writes 1
|
| 120 |
+
--btb_main_latency 3
|
| 121 |
+
--btb_l0_present 1
|
| 122 |
+
--btb_l0_entries 128
|
| 123 |
+
--btb_l0_assoc 4
|
| 124 |
+
--btb_l0_latency 1
|
| 125 |
+
--btb_l1_present 1
|
| 126 |
+
--btb_l1_entries 6144
|
| 127 |
+
--btb_l1_assoc 4
|
| 128 |
+
--btb_l1_latency 2
|
| 129 |
+
--enable_crs 1
|
| 130 |
+
--crs_entries 128
|
| 131 |
+
--crs_realistic 1
|
| 132 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 133 |
+
--ibtb_mech tc_tagged
|
| 134 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 135 |
+
--tc_entries 4096
|
| 136 |
+
--tc_assoc 4
|
| 137 |
+
--pref_stream_on 1
|
| 138 |
+
--stream_prefetch_n 4
|
| 139 |
+
--stream_start_dis 1
|
| 140 |
+
--stream_length 64
|
| 141 |
+
--stream_train_num 4
|
| 142 |
+
--stream_create_on_dc_miss 0
|
| 143 |
+
--stream_create_on_l1_miss 1
|
| 144 |
+
--pref_framework_on 1
|
| 145 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 146 |
+
--pref_train_on_pref_misses 0
|
| 147 |
+
--pref_oracle_train_on 0
|
| 148 |
+
--pref_throttlefb_on 1
|
| 149 |
+
--pref_acc_thresh_1 0.75
|
| 150 |
+
--pref_acc_thresh_2 0.4
|
| 151 |
+
--pref_acc_thresh_3 0.4
|
| 152 |
+
--pref_update_interval 8192
|
| 153 |
+
--pref_timely_thresh 0.01
|
| 154 |
+
--pref_polpf_thresh 0.005
|
| 155 |
+
1 1 1 1 1 1 1
|
| 156 |
+
|
| 157 |
+
--- Cut out everything below to use this file as PARAMS.in ---
|
| 158 |
+
|
| 159 |
+
Parameter status at compile time and values supplied on the command line:
|
| 160 |
+
|
| 161 |
+
SIM_MODE 0 trace_bbv_distributed
|
| 162 |
+
SIM_MODEL 0 cmp
|
| 163 |
+
FRONTEND FE_PIN_EXEC_DRIVEN memtrace
|
| 164 |
+
INST_LIMIT NULL
|
| 165 |
+
SIM_LIMIT "none" none
|
| 166 |
+
FORWARD_PROGRESS_LIMIT 100000000
|
| 167 |
+
FORWARD_PROGRESS_INTERVAL 10000
|
| 168 |
+
FAST_FORWARD 0
|
| 169 |
+
FAST_FORWARD_TRACE_INS 0
|
| 170 |
+
FAST_FORWARD_UNTIL_ADDR 0
|
| 171 |
+
MEMTRACE_ROI_BEGIN 0 1
|
| 172 |
+
MEMTRACE_ROI_END 0 10000000
|
| 173 |
+
FULL_WARMUP 0
|
| 174 |
+
WARMUP 0
|
| 175 |
+
HEARTBEAT_INTERVAL 1000000
|
| 176 |
+
NUM_HEARTBEATS 0
|
| 177 |
+
USE_FETCHED_COUNT FALSE 1
|
| 178 |
+
PERIODIC_DUMP FALSE
|
| 179 |
+
FILE_TAG ""
|
| 180 |
+
OUTPUT_DIR "."
|
| 181 |
+
STATUS_FILE NULL
|
| 182 |
+
BINDIR NULL
|
| 183 |
+
DUMP_PARAMS TRUE 1
|
| 184 |
+
DUMP_STATS TRUE 1
|
| 185 |
+
DUMP_TRACE FALSE 0
|
| 186 |
+
CLEAR_STATS "never"
|
| 187 |
+
STATS_TO_TRACE NULL
|
| 188 |
+
STAT_TRACE_FILE "stats.trace"
|
| 189 |
+
STAT_TRACE_INTERVAL "i:100000"
|
| 190 |
+
PIPEVIEW FALSE
|
| 191 |
+
PIPEVIEW_FILE "pipeview"
|
| 192 |
+
MEMVIEW FALSE
|
| 193 |
+
MEMVIEW_FILE "memview.out"
|
| 194 |
+
MEMVIEW_START "never"
|
| 195 |
+
INST_HASH_TABLE_SIZE 524288 const
|
| 196 |
+
STDOUT_FILE NULL
|
| 197 |
+
STDERR_FILE NULL
|
| 198 |
+
PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp"
|
| 199 |
+
PRINT_PID FALSE
|
| 200 |
+
USE_UNSURE_FREE_LISTS FALSE
|
| 201 |
+
OPTIMIZER2_MAX_NUM_SLAVES 64
|
| 202 |
+
OPTIMIZER2_PERFECT_MEMORYLESS FALSE
|
| 203 |
+
EXIT_COND 0
|
| 204 |
+
NUM_NOPS 0
|
| 205 |
+
NOPS_BB_START 0x5000000
|
| 206 |
+
IGNORE_BAR_FETCH FALSE
|
| 207 |
+
TRACE_BBV_OUTPUT NULL /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.0
|
| 208 |
+
TRACE_FOOTPRINT_OUTPUT "" /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.0
|
| 209 |
+
SEGMENT_INSTR_COUNT 0 10000000
|
| 210 |
+
ENABLE_SWPRF FALSE
|
| 211 |
+
MLC_PRESENT FALSE 1
|
| 212 |
+
MLC_SIZE (512 * 1024) 2097000
|
| 213 |
+
MLC_ASSOC 4 8
|
| 214 |
+
MLC_LINE_SIZE 64
|
| 215 |
+
MLC_CYCLES 12 16
|
| 216 |
+
PERFECT_MLC FALSE
|
| 217 |
+
MLC_READ_PORTS 1
|
| 218 |
+
MLC_WRITE_PORTS 1
|
| 219 |
+
MLC_BANKS 8
|
| 220 |
+
MLC_INTERLEAVE_FACTOR 64
|
| 221 |
+
MLC_CACHE_REPL_POLICY 0
|
| 222 |
+
MLC_WRITE_THROUGH FALSE
|
| 223 |
+
PREFETCH_UPDATE_LRU_MLC TRUE
|
| 224 |
+
FORCE_L1_MISS FALSE
|
| 225 |
+
L1_SIZE (4 * 1024 * 1024) 3145728
|
| 226 |
+
L1_ASSOC 8 16
|
| 227 |
+
L1_LINE_SIZE 64 64
|
| 228 |
+
L1_CYCLES 24 36 // just a guess
|
| 229 |
+
PERFECT_L1 FALSE
|
| 230 |
+
PRIVATE_L1 FALSE
|
| 231 |
+
L1_READ_PORTS 1
|
| 232 |
+
L1_WRITE_PORTS 1
|
| 233 |
+
L1_BANKS 8 8
|
| 234 |
+
L1_INTERLEAVE_FACTOR 64 64
|
| 235 |
+
L1_CACHE_REPL_POLICY 0
|
| 236 |
+
L1_WRITE_THROUGH FALSE
|
| 237 |
+
L1_IGNORE_WB FALSE
|
| 238 |
+
L1_USE_CORE_FREQ FALSE
|
| 239 |
+
MARK_L1_MISSES TRUE
|
| 240 |
+
PREFETCH_UPDATE_LRU_L1 TRUE
|
| 241 |
+
MEMORY_RANDOM_ADDR FALSE
|
| 242 |
+
VA_PAGE_SIZE_BYTES 4096
|
| 243 |
+
NUM_ADDR_NON_SIGN_EXTEND_BITS 48
|
| 244 |
+
ADDR_TRANSLATION 0 random
|
| 245 |
+
CONSTANT_MEMORY_LATENCY FALSE
|
| 246 |
+
MEMORY_CYCLES 100
|
| 247 |
+
STALL_MEM_REQS_ONLY FALSE
|
| 248 |
+
ICACHE_SIZE (64 * 1024) 32768
|
| 249 |
+
ICACHE_ASSOC 4 8
|
| 250 |
+
ICACHE_LINE_SIZE 64 64
|
| 251 |
+
PERFECT_ICACHE FALSE
|
| 252 |
+
ICACHE_READ_PORTS 1
|
| 253 |
+
ICACHE_WRITE_PORTS 1
|
| 254 |
+
ICACHE_BANKS 8
|
| 255 |
+
ICACHE_REPL 0
|
| 256 |
+
UOP_CACHE_ENABLE 1 1
|
| 257 |
+
UOP_CACHE_WIDTH 6 8
|
| 258 |
+
ALWAYS_LOOKUP_ICACHE 0
|
| 259 |
+
UOP_CACHE_INSERT_ONLY_ONPATH FALSE
|
| 260 |
+
UOP_CACHE_READ_PORTS 1
|
| 261 |
+
UOP_CACHE_LINES 384 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 262 |
+
UOP_CACHE_ASSOC 8 8
|
| 263 |
+
UOP_CACHE_MAX_IMM_DISP_LINE 4
|
| 264 |
+
IPRF_ON_UOP_CACHE_HIT FALSE 1
|
| 265 |
+
UOP_CACHE_REPL 0
|
| 266 |
+
PRIORITY_LINE_STICKINESS_PERCENT 50
|
| 267 |
+
PW_PRIORITY_LIST_FILEPATH "pw_priority_list.csv"
|
| 268 |
+
NUM_PRIORITY_PWS 10
|
| 269 |
+
PRIORITIZE_PWS_AFTER_FIRST_STICKY_UNTIL_BACKEND_STALL FALSE
|
| 270 |
+
NO_REPL_AFTER_QUEUE_SIZE 0
|
| 271 |
+
FDIP_UC_SIZE 0
|
| 272 |
+
FDIP_UC_ASSOC 4
|
| 273 |
+
FDIP_UC_INSERT_REPLPOL 0
|
| 274 |
+
MAP_STAGE_CONSUME_FROM_ICACHE_AND_UOC_SAME_CYCLE TRUE
|
| 275 |
+
UOP_QUEUE_LENGTH 7
|
| 276 |
+
DCACHE_SIZE (64 * 1024) 49152
|
| 277 |
+
DCACHE_ASSOC 1 12
|
| 278 |
+
DCACHE_LINE_SIZE 64 64
|
| 279 |
+
DCACHE_CYCLES 2 5
|
| 280 |
+
PERFECT_DCACHE FALSE
|
| 281 |
+
DCACHE_READ_PORTS 8 1
|
| 282 |
+
DCACHE_WRITE_PORTS 1 1
|
| 283 |
+
DCACHE_BANKS 1 8
|
| 284 |
+
DCACHE_INTERLEAVE_FACTOR 4
|
| 285 |
+
DCACHE_REPL 0
|
| 286 |
+
DCACHE_REPL_PREF_THRESH 1
|
| 287 |
+
MEM_OOO_STORES TRUE 1
|
| 288 |
+
MEM_OBEY_STORE_DEP TRUE 1
|
| 289 |
+
PREF_INSERT_LRU FALSE
|
| 290 |
+
PREF_INSERT_MIDDLE FALSE
|
| 291 |
+
PREF_INSERT_LOWQTR FALSE
|
| 292 |
+
PREF_INSERT_DYNACC FALSE
|
| 293 |
+
MEM_REQ_BUFFER_ENTRIES 32 32
|
| 294 |
+
PRIVATE_MSHR_ON TRUE
|
| 295 |
+
MEM_PRIORITY_IFETCH 0 0
|
| 296 |
+
MEM_PRIORITY_DFETCH 0 1
|
| 297 |
+
MEM_PRIORITY_DSTORE 0 2
|
| 298 |
+
MEM_PRIORITY_IPRF 9 3
|
| 299 |
+
MEM_PRIORITY_UOCPRF 9
|
| 300 |
+
MEM_PRIORITY_FDIPPRFON 8
|
| 301 |
+
MEM_PRIORITY_FDIPPRFOFF 9
|
| 302 |
+
MEM_PRIORITY_DPRF 10 4
|
| 303 |
+
MEM_PRIORITY_WB 0 5
|
| 304 |
+
MEM_PRIORITY_WB_NODIRTY 0 5
|
| 305 |
+
PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1
|
| 306 |
+
MEM_REQ_BUFFER_PREF_WATERMARK 0 4
|
| 307 |
+
MEM_REQ_BUFFER_WB_VALVE 2
|
| 308 |
+
MEM_L1_FILL_QUEUE_ENTRIES 32
|
| 309 |
+
MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE
|
| 310 |
+
MEM_MEM_QUEUE_PARTITION_ENABLE FALSE
|
| 311 |
+
MEM_BUS_OUT_QUEUE_AS_FIFO TRUE
|
| 312 |
+
OLDEST_FIRST_TO_MEM_QUEUE TRUE
|
| 313 |
+
ROUND_ROBIN_TO_MEM_QUEUE FALSE
|
| 314 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE FALSE
|
| 315 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0
|
| 316 |
+
L1_CYCLE_TIME 312500
|
| 317 |
+
MLCQ_TO_L1Q_TRANSFER_LATENCY 1
|
| 318 |
+
L1Q_TO_FSB_TRANSFER_LATENCY 1
|
| 319 |
+
PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE
|
| 320 |
+
KICKOUT_PREFETCHES FALSE
|
| 321 |
+
KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE
|
| 322 |
+
KICKOUT_OLDEST_PREFETCH FALSE
|
| 323 |
+
KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE
|
| 324 |
+
ORDER_BEYOND_BUS FALSE 1
|
| 325 |
+
ALL_FIFO_QUEUES FALSE
|
| 326 |
+
QUEUE_MLC_SIZE 0
|
| 327 |
+
QUEUE_L1_SIZE 0
|
| 328 |
+
QUEUE_BUS_OUT_SIZE 0
|
| 329 |
+
QUEUE_CORE_FILL_SIZE 0
|
| 330 |
+
ALLOW_TYPE_MATCHES FALSE
|
| 331 |
+
STREAM_PREFETCH_ON FALSE
|
| 332 |
+
DC_PREF_CACHE_ENABLE FALSE
|
| 333 |
+
DC_PREF_CACHE_CYCLE 0
|
| 334 |
+
PREF_INSERT_DCACHE_IMM TRUE
|
| 335 |
+
DC_PREF_CACHE_SIZE (64 * 1024)
|
| 336 |
+
DC_PREF_CACHE_ASSOC 4
|
| 337 |
+
DC_PREF_ONLY_L1HIT FALSE
|
| 338 |
+
PREF_CACHE_USE_RDY_CYCLE FALSE
|
| 339 |
+
IC_PREF_CACHE_ENABLE FALSE
|
| 340 |
+
IC_PREF_CACHE_SIZE (64 * 1024)
|
| 341 |
+
IC_PREF_CACHE_ASSOC 4
|
| 342 |
+
L1_PREF_CACHE_ENABLE FALSE
|
| 343 |
+
L1_PREF_CACHE_SIZE (1024 * 1024)
|
| 344 |
+
L1_PREF_CACHE_ASSOC 8
|
| 345 |
+
SET_OFF_PATH_CONFIRMED FALSE 1
|
| 346 |
+
USE_CONFIRMED_OFF FALSE
|
| 347 |
+
PREFCACHE_MOVE_OFFPATH FALSE
|
| 348 |
+
CACHE_STAT_ENABLE FALSE
|
| 349 |
+
PREF_DCACHE_HIT_FILL_L1 TRUE
|
| 350 |
+
PREF_ICACHE_HIT_FILL_L1 TRUE
|
| 351 |
+
CRITICAL_ACCESS_PLOT_ENABLE FALSE
|
| 352 |
+
CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat"
|
| 353 |
+
ROUND_ROBIN_TO_L1 FALSE
|
| 354 |
+
PREF_I_TOGETHER FALSE
|
| 355 |
+
ONE_MORE_CACHE_LINE_ENABLE FALSE
|
| 356 |
+
L1_STATIC_PARTITION_ENABLE 0
|
| 357 |
+
L1_STATIC_PARTITION NULL
|
| 358 |
+
L1_DYNAMIC_PARTITION_ENABLE FALSE
|
| 359 |
+
L1_DYNAMIC_PARTITION_POLICY 0
|
| 360 |
+
PARTITION_UMON_DSS_PREF_ENABLE FALSE
|
| 361 |
+
L1_CACHE_HIT_POSITION_COLLECT FALSE
|
| 362 |
+
L1_PART_ON FALSE
|
| 363 |
+
L1_PART_TRIGGER "c:1000000"
|
| 364 |
+
L1_PART_START "t:0"
|
| 365 |
+
L1_PART_WARMUP FALSE
|
| 366 |
+
L1_PART_SHADOW_WARMUP FALSE
|
| 367 |
+
L1_PART_METRIC 0
|
| 368 |
+
L1_PART_SEARCH 0
|
| 369 |
+
L1_PART_USE_STALLING TRUE
|
| 370 |
+
L1_PART_FILL_DELAY 0
|
| 371 |
+
L1_SHADOW_TAGS_MODULO 1
|
| 372 |
+
HIER_MSHR_ON FALSE
|
| 373 |
+
PERF_PRED_ENABLE FALSE
|
| 374 |
+
PERF_PRED_MECH PERF_PRED_CP
|
| 375 |
+
PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY
|
| 376 |
+
PERF_PRED_COUNT_ALL FALSE
|
| 377 |
+
PERF_PRED_COUNT_INST_MISSES TRUE
|
| 378 |
+
PERF_PRED_COUNT_PREFETCHES FALSE
|
| 379 |
+
PERF_PRED_COUNT_OFFPATH_REQS FALSE
|
| 380 |
+
PERF_PRED_COUNT_BW_REQS TRUE
|
| 381 |
+
PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE
|
| 382 |
+
PERF_PRED_SLACK_PERIOD_SIZE 32
|
| 383 |
+
PERF_PRED_REQS_FINISH_AT_FILL FALSE
|
| 384 |
+
PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE
|
| 385 |
+
PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE
|
| 386 |
+
DUMB_MODEL_AVG_REQ_DISTANCE 100
|
| 387 |
+
DUMB_MODEL_RANDOMIZE_DISTANCE FALSE
|
| 388 |
+
DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL
|
| 389 |
+
DUMB_MODEL_AVG_ROW_HITS 1
|
| 390 |
+
DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL
|
| 391 |
+
DUMB_MODEL_MLP 1
|
| 392 |
+
DUMB_MODEL_MLP_PER_CORE NULL
|
| 393 |
+
RAMULATOR_STANDARD "DDR4" DDR4
|
| 394 |
+
RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R
|
| 395 |
+
RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8
|
| 396 |
+
RAMULATOR_CHANNELS 1 1
|
| 397 |
+
RAMULATOR_RANKS 1 1
|
| 398 |
+
RAMULATOR_BANKGROUPS 4 4
|
| 399 |
+
RAMULATOR_BANKS 4 4
|
| 400 |
+
RAMULATOR_CHIP_WIDTH 8 8
|
| 401 |
+
BUS_WIDTH_IN_BYTES 8 8
|
| 402 |
+
RAMULATOR_ROWS 65536 65536
|
| 403 |
+
RAMULATOR_COLS 1024 1024
|
| 404 |
+
RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap
|
| 405 |
+
RAMULATOR_READQ_ENTRIES 32 32
|
| 406 |
+
RAMULATOR_WRITEQ_ENTRIES 32 32
|
| 407 |
+
RAMULATOR_REC_CMD_TRACE "off" FALSE
|
| 408 |
+
RAMULATOR_PRINT_CMD_TRACE "off" FALSE
|
| 409 |
+
RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on"
|
| 410 |
+
RAMULATOR_TCK 833333 833333
|
| 411 |
+
RAMULATOR_TCL 16 16
|
| 412 |
+
RAMULATOR_TCCD 6 6
|
| 413 |
+
RAMULATOR_TCCDS 4 4
|
| 414 |
+
RAMULATOR_TCCDL 6 6
|
| 415 |
+
RAMULATOR_TCWL 12 12
|
| 416 |
+
RAMULATOR_TBL 4 4
|
| 417 |
+
RAMULATOR_TWTR 9 9
|
| 418 |
+
RAMULATOR_TWTRS 3 3
|
| 419 |
+
RAMULATOR_TWTRL 9 9
|
| 420 |
+
RAMULATOR_TRP 16 16
|
| 421 |
+
RAMULATOR_TRPpb 16 16
|
| 422 |
+
RAMULATOR_TRPab 16 16
|
| 423 |
+
RAMULATOR_TRCD 16 16
|
| 424 |
+
RAMULATOR_TRCDR 16 16
|
| 425 |
+
RAMULATOR_TRCDW 16 16
|
| 426 |
+
RAMULATOR_TRAS 39 39
|
| 427 |
+
DRAM_TECH_IN_NM 32 32
|
| 428 |
+
DVFS_ON FALSE
|
| 429 |
+
DVFS_METRIC DVFS_METRIC_NUM_ELEMS
|
| 430 |
+
DVFS_CONFIGS NULL
|
| 431 |
+
DVFS_CONFIG_FILE NULL
|
| 432 |
+
DVFS_START "t:0"
|
| 433 |
+
DVFS_PERIOD "t:312500000000"
|
| 434 |
+
DVFS_LOG TRUE
|
| 435 |
+
DVFS_INDIVIDUAL_CORES FALSE
|
| 436 |
+
DVFS_CHIP_LEVEL FALSE
|
| 437 |
+
DVFS_STATIC NULL
|
| 438 |
+
DVFS_FORCE_CONFIG NULL
|
| 439 |
+
DVFS_REPLAY_CONFIG_TRACE NULL
|
| 440 |
+
DVFS_USE_ORACLE FALSE
|
| 441 |
+
DVFS_USE_BW_SHARING FALSE
|
| 442 |
+
DVFS_USE_DRAM_SHARING FALSE
|
| 443 |
+
DVFS_USE_STALL_TIME FALSE
|
| 444 |
+
DVFS_DRAM_SHARING_SOLVER_BIN NULL
|
| 445 |
+
DVFS_DRAM_SHARING_SOLVER_STRICT TRUE
|
| 446 |
+
DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95
|
| 447 |
+
DVFS_BW_SHARING_MAX_REQS 28.0
|
| 448 |
+
DVFS_BW_SHARING_MAX_RW_COST 0.25
|
| 449 |
+
DVFS_BW_SHARING_NO_PREF_STALL TRUE
|
| 450 |
+
DVFS_BW_SHARING_CRIT_STATS TRUE
|
| 451 |
+
DVFS_COUNT_L1_ACCESS_STALL FALSE
|
| 452 |
+
NUM_CORES 1
|
| 453 |
+
CHIP_CYCLE_TIME 312500 312500
|
| 454 |
+
CORE_0_CYCLE_TIME 312500
|
| 455 |
+
CORE_1_CYCLE_TIME 312500
|
| 456 |
+
CORE_2_CYCLE_TIME 312500
|
| 457 |
+
CORE_3_CYCLE_TIME 312500
|
| 458 |
+
CORE_4_CYCLE_TIME 312500
|
| 459 |
+
CORE_5_CYCLE_TIME 312500
|
| 460 |
+
CORE_6_CYCLE_TIME 312500
|
| 461 |
+
CORE_7_CYCLE_TIME 312500
|
| 462 |
+
CORE_8_CYCLE_TIME 312500
|
| 463 |
+
CORE_9_CYCLE_TIME 312500
|
| 464 |
+
CORE_10_CYCLE_TIME 312500
|
| 465 |
+
CORE_11_CYCLE_TIME 312500
|
| 466 |
+
CORE_12_CYCLE_TIME 312500
|
| 467 |
+
CORE_13_CYCLE_TIME 312500
|
| 468 |
+
CORE_14_CYCLE_TIME 312500
|
| 469 |
+
CORE_15_CYCLE_TIME 312500
|
| 470 |
+
CORE_16_CYCLE_TIME 312500
|
| 471 |
+
CORE_17_CYCLE_TIME 312500
|
| 472 |
+
CORE_18_CYCLE_TIME 312500
|
| 473 |
+
CORE_19_CYCLE_TIME 312500
|
| 474 |
+
CORE_20_CYCLE_TIME 312500
|
| 475 |
+
CORE_21_CYCLE_TIME 312500
|
| 476 |
+
CORE_22_CYCLE_TIME 312500
|
| 477 |
+
CORE_23_CYCLE_TIME 312500
|
| 478 |
+
CORE_24_CYCLE_TIME 312500
|
| 479 |
+
CORE_25_CYCLE_TIME 312500
|
| 480 |
+
CORE_26_CYCLE_TIME 312500
|
| 481 |
+
CORE_27_CYCLE_TIME 312500
|
| 482 |
+
CORE_28_CYCLE_TIME 312500
|
| 483 |
+
CORE_29_CYCLE_TIME 312500
|
| 484 |
+
CORE_30_CYCLE_TIME 312500
|
| 485 |
+
CORE_31_CYCLE_TIME 312500
|
| 486 |
+
CORE_32_CYCLE_TIME 312500
|
| 487 |
+
CORE_33_CYCLE_TIME 312500
|
| 488 |
+
CORE_34_CYCLE_TIME 312500
|
| 489 |
+
CORE_35_CYCLE_TIME 312500
|
| 490 |
+
CORE_36_CYCLE_TIME 312500
|
| 491 |
+
CORE_37_CYCLE_TIME 312500
|
| 492 |
+
CORE_38_CYCLE_TIME 312500
|
| 493 |
+
CORE_39_CYCLE_TIME 312500
|
| 494 |
+
CORE_40_CYCLE_TIME 312500
|
| 495 |
+
CORE_41_CYCLE_TIME 312500
|
| 496 |
+
CORE_42_CYCLE_TIME 312500
|
| 497 |
+
CORE_43_CYCLE_TIME 312500
|
| 498 |
+
CORE_44_CYCLE_TIME 312500
|
| 499 |
+
CORE_45_CYCLE_TIME 312500
|
| 500 |
+
CORE_46_CYCLE_TIME 312500
|
| 501 |
+
CORE_47_CYCLE_TIME 312500
|
| 502 |
+
CORE_48_CYCLE_TIME 312500
|
| 503 |
+
CORE_49_CYCLE_TIME 312500
|
| 504 |
+
CORE_50_CYCLE_TIME 312500
|
| 505 |
+
CORE_51_CYCLE_TIME 312500
|
| 506 |
+
CORE_52_CYCLE_TIME 312500
|
| 507 |
+
CORE_53_CYCLE_TIME 312500
|
| 508 |
+
CORE_54_CYCLE_TIME 312500
|
| 509 |
+
CORE_55_CYCLE_TIME 312500
|
| 510 |
+
CORE_56_CYCLE_TIME 312500
|
| 511 |
+
CORE_57_CYCLE_TIME 312500
|
| 512 |
+
CORE_58_CYCLE_TIME 312500
|
| 513 |
+
CORE_59_CYCLE_TIME 312500
|
| 514 |
+
CORE_60_CYCLE_TIME 312500
|
| 515 |
+
CORE_61_CYCLE_TIME 312500
|
| 516 |
+
CORE_62_CYCLE_TIME 312500
|
| 517 |
+
CORE_63_CYCLE_TIME 312500
|
| 518 |
+
TOPDOWN_FU_EXEC_FEW 0
|
| 519 |
+
ISSUE_WIDTH 4 6
|
| 520 |
+
RS_FILL_WIDTH 8 0
|
| 521 |
+
NODE_TABLE_SIZE 256 512
|
| 522 |
+
NODE_RET_WIDTH 4 8
|
| 523 |
+
NODE_RETIRE_RATE 10
|
| 524 |
+
DECODE_WIDTH 4 6
|
| 525 |
+
IDQ_SIZE 140 144
|
| 526 |
+
REG_RENAMING_SCHEME 0 1
|
| 527 |
+
REG_TABLE_INTEGER_PHYSICAL_SIZE 256 280
|
| 528 |
+
REG_TABLE_VECTOR_PHYSICAL_SIZE 256 332
|
| 529 |
+
REG_TABLE_INTEGER_VIRTUAL_SIZE 256
|
| 530 |
+
REG_TABLE_VECTOR_VIRTUAL_SIZE 256
|
| 531 |
+
REG_RENAMING_MOVE_ELIMINATE FALSE
|
| 532 |
+
NODE_ISSUE_QUEUE_DISPATCH_SCHEME 0
|
| 533 |
+
NODE_ISSUE_QUEUE_SCHEDULE_SCHEME 0
|
| 534 |
+
ISSUE_QUEUE_PARALLEL_PICK FALSE
|
| 535 |
+
RS_SIZES "256" 97 70 19
|
| 536 |
+
RS_CONNECTIONS "xF" b0100110011 b1000001100 b0011000000
|
| 537 |
+
FU_TYPES "0, 0, 0, 0" b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 538 |
+
LSQ_ENABLE TRUE
|
| 539 |
+
LOAD_QUEUE_ENTRY_NUM 128
|
| 540 |
+
STORE_QUEUE_ENTRY_NUM 72
|
| 541 |
+
DECODE_CYCLES 1 5
|
| 542 |
+
MAP_CYCLES 1 5
|
| 543 |
+
ICACHE_LATENCY 3
|
| 544 |
+
EXTRA_REDIRECT_CYCLES 0
|
| 545 |
+
EXTRA_RECOVERY_CYCLES 0
|
| 546 |
+
EXTRA_CALLSYS_CYCLES 20 const
|
| 547 |
+
DIE_ON_CALLSYS FALSE
|
| 548 |
+
DIE_ON_RET_STALL_THRESH 0
|
| 549 |
+
DIE_ON_RET_STALL_CORE 0
|
| 550 |
+
DIE_ON_MEM_BLOCK_THRESH 0
|
| 551 |
+
DIE_ON_MEM_BLOCK_CORE 0
|
| 552 |
+
ICACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 553 |
+
UOP_CACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 554 |
+
FETCH_OFF_PATH_OPS TRUE 1
|
| 555 |
+
WP_COLLECT_STATS TRUE
|
| 556 |
+
OP_INV_DELAY 1
|
| 557 |
+
OP_NOP_DELAY 1
|
| 558 |
+
OP_CF_DELAY 1
|
| 559 |
+
OP_MOV_DELAY 1
|
| 560 |
+
OP_CMOV_DELAY 1
|
| 561 |
+
OP_LDA_DELAY 1
|
| 562 |
+
OP_ILD_DELAY 1
|
| 563 |
+
OP_IST_DELAY 1
|
| 564 |
+
OP_IADD_DELAY 1
|
| 565 |
+
OP_IMUL_DELAY 3
|
| 566 |
+
OP_IDIV_DELAY -20
|
| 567 |
+
OP_ICMP_DELAY 1
|
| 568 |
+
OP_LOGIC_DELAY 1
|
| 569 |
+
OP_SHIFT_DELAY 1
|
| 570 |
+
OP_FLD_DELAY 1
|
| 571 |
+
OP_FST_DELAY 1
|
| 572 |
+
OP_FCVT_DELAY 3
|
| 573 |
+
OP_FADD_DELAY 3
|
| 574 |
+
OP_FMUL_DELAY 5
|
| 575 |
+
OP_FMA_DELAY 5
|
| 576 |
+
OP_FDIV_DELAY -20
|
| 577 |
+
OP_FCMP_DELAY 3
|
| 578 |
+
OP_FCMOV_DELAY 1
|
| 579 |
+
OP_GATHER_DELAY 12
|
| 580 |
+
OP_SCATTER_DELAY 18
|
| 581 |
+
OP_PIPELINED_FAST_DELAY 2
|
| 582 |
+
OP_PIPELINED_MEDIUM_DELAY 5
|
| 583 |
+
OP_PIPELINED_SLOW_DELAY 10
|
| 584 |
+
OP_NOTPIPELINED_MEDIUM_DELAY -5
|
| 585 |
+
OP_NOTPIPELINED_SLOW_DELAY -20
|
| 586 |
+
OP_NOTPIPELINED_VERY_SLOW_DELAY -100
|
| 587 |
+
UNIFORM_OP_DELAY 0
|
| 588 |
+
STALL_ON_WAIT_MEM TRUE
|
| 589 |
+
STORES_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 590 |
+
PREFS_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 591 |
+
OBEY_REG_DEP TRUE
|
| 592 |
+
TRACK_L1_MISS_DEPS FALSE
|
| 593 |
+
CBP_TRACE_R0 NULL /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 594 |
+
CBP_TRACE_R1 NULL
|
| 595 |
+
CBP_TRACE_R2 NULL
|
| 596 |
+
CBP_TRACE_R3 NULL
|
| 597 |
+
CBP_TRACE_R4 NULL
|
| 598 |
+
CBP_TRACE_R5 NULL
|
| 599 |
+
CBP_TRACE_R6 NULL
|
| 600 |
+
CBP_TRACE_R7 NULL
|
| 601 |
+
CBP_TRACE_R8 NULL
|
| 602 |
+
CBP_TRACE_R9 NULL
|
| 603 |
+
CBP_TRACE_R10 NULL
|
| 604 |
+
CBP_TRACE_R11 NULL
|
| 605 |
+
CBP_TRACE_R12 NULL
|
| 606 |
+
CBP_TRACE_R13 NULL
|
| 607 |
+
CBP_TRACE_R14 NULL
|
| 608 |
+
CBP_TRACE_R15 NULL
|
| 609 |
+
CBP_TRACE_R16 NULL
|
| 610 |
+
CBP_TRACE_R17 NULL
|
| 611 |
+
CBP_TRACE_R18 NULL
|
| 612 |
+
CBP_TRACE_R19 NULL
|
| 613 |
+
CBP_TRACE_R20 NULL
|
| 614 |
+
CBP_TRACE_R21 NULL
|
| 615 |
+
CBP_TRACE_R22 NULL
|
| 616 |
+
CBP_TRACE_R23 NULL
|
| 617 |
+
CBP_TRACE_R24 NULL
|
| 618 |
+
CBP_TRACE_R25 NULL
|
| 619 |
+
CBP_TRACE_R26 NULL
|
| 620 |
+
CBP_TRACE_R27 NULL
|
| 621 |
+
CBP_TRACE_R28 NULL
|
| 622 |
+
CBP_TRACE_R29 NULL
|
| 623 |
+
CBP_TRACE_R30 NULL
|
| 624 |
+
CBP_TRACE_R31 NULL
|
| 625 |
+
CBP_TRACE_R32 NULL
|
| 626 |
+
CBP_TRACE_R33 NULL
|
| 627 |
+
CBP_TRACE_R34 NULL
|
| 628 |
+
CBP_TRACE_R35 NULL
|
| 629 |
+
CBP_TRACE_R36 NULL
|
| 630 |
+
CBP_TRACE_R37 NULL
|
| 631 |
+
CBP_TRACE_R38 NULL
|
| 632 |
+
CBP_TRACE_R39 NULL
|
| 633 |
+
CBP_TRACE_R40 NULL
|
| 634 |
+
CBP_TRACE_R41 NULL
|
| 635 |
+
CBP_TRACE_R42 NULL
|
| 636 |
+
CBP_TRACE_R43 NULL
|
| 637 |
+
CBP_TRACE_R44 NULL
|
| 638 |
+
CBP_TRACE_R45 NULL
|
| 639 |
+
CBP_TRACE_R46 NULL
|
| 640 |
+
CBP_TRACE_R47 NULL
|
| 641 |
+
CBP_TRACE_R48 NULL
|
| 642 |
+
CBP_TRACE_R49 NULL
|
| 643 |
+
CBP_TRACE_R50 NULL
|
| 644 |
+
CBP_TRACE_R51 NULL
|
| 645 |
+
CBP_TRACE_R52 NULL
|
| 646 |
+
CBP_TRACE_R53 NULL
|
| 647 |
+
CBP_TRACE_R54 NULL
|
| 648 |
+
CBP_TRACE_R55 NULL
|
| 649 |
+
CBP_TRACE_R56 NULL
|
| 650 |
+
CBP_TRACE_R57 NULL
|
| 651 |
+
CBP_TRACE_R58 NULL
|
| 652 |
+
CBP_TRACE_R59 NULL
|
| 653 |
+
CBP_TRACE_R60 NULL
|
| 654 |
+
CBP_TRACE_R61 NULL
|
| 655 |
+
CBP_TRACE_R62 NULL
|
| 656 |
+
CBP_TRACE_R63 NULL
|
| 657 |
+
FE_FTQ_BLOCK_NUM 32
|
| 658 |
+
FE_FTQ_TAKEN_CFS_PER_CYCLE 2
|
| 659 |
+
FE_FTQ_FT_PER_CYCLE 1
|
| 660 |
+
DUMB_CORE_ON FALSE
|
| 661 |
+
DUMB_CORE 1
|
| 662 |
+
DCACHE_MISS_RATE 10
|
| 663 |
+
L1_MISS_RATE 10
|
| 664 |
+
TRACE_BUF_SIZE 0
|
| 665 |
+
PERFECT_CONFIDENCE FALSE
|
| 666 |
+
CONFIDENCE_ENABLE FALSE
|
| 667 |
+
CONFIDENCE_MECH 0
|
| 668 |
+
CONF_OFF_PATH_THRESHOLD 15
|
| 669 |
+
CONF_OFF_PATH_INC 5
|
| 670 |
+
CONF_BTB_MISS_BP_TAKEN FALSE
|
| 671 |
+
CONF_IPC_RATE_CONF FALSE
|
| 672 |
+
CONF_BTB_MISS_BP_TAKEN_THRESHOLD 0
|
| 673 |
+
CONF_BTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 674 |
+
CONF_IBTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 675 |
+
CONF_MISFETCH_RATE_CYCLES_THRESHOLD 1.0
|
| 676 |
+
CONF_MISPRED_RATE_CYCLES_THRESHOLD 1.0
|
| 677 |
+
CONF_BTB_MISS_SAMPLE_RATE 100000
|
| 678 |
+
CONF_IBTB_MISS_SAMPLE_RATE 100000
|
| 679 |
+
CONF_MISFETCH_SAMPLE_RATE 100000
|
| 680 |
+
CONF_MISPRED_SAMPLE_RATE 100000
|
| 681 |
+
CONF_IPC_SAMPLE_RATE 100000
|
| 682 |
+
CONF_BTB_MISS_RATE_WEIGHT 200
|
| 683 |
+
CONF_BTB_MISS_BP_TAKEN_CONF TRUE
|
| 684 |
+
CONF_IBTB_MISS_BP_TAKEN_CONF TRUE
|
| 685 |
+
CONF_BTB_MISS_RATE_CONF TRUE
|
| 686 |
+
CONF_IBTB_MISS_RATE_CONF TRUE
|
| 687 |
+
CONF_MISFETCH_RATE_CONF TRUE
|
| 688 |
+
CONF_MISPRED_RATE_CONF TRUE
|
| 689 |
+
CONF_INV_BP_CONF TRUE
|
| 690 |
+
CONF_PERFECT_BTB_MISS_CONF FALSE
|
| 691 |
+
CONF_PERFECT_IBTB_MISS_CONF FALSE
|
| 692 |
+
CONF_PERFECT_MISFETCH_CONF FALSE
|
| 693 |
+
CONF_PERFECT_MISPRED_CONF FALSE
|
| 694 |
+
CONF_LOG_DFE_TO_REC FALSE
|
| 695 |
+
CONF_LOG_PHASE_CYCLES FALSE
|
| 696 |
+
NUM_BPS 1
|
| 697 |
+
DFE0_TRIGGER_POLICY 0
|
| 698 |
+
DFE1_TRIGGER_POLICY 1
|
| 699 |
+
DFE2_TRIGGER_POLICY 1
|
| 700 |
+
DFE3_TRIGGER_POLICY 1
|
| 701 |
+
DFE4_TRIGGER_POLICY 1
|
| 702 |
+
DFE0_STOP_POLICY 0
|
| 703 |
+
DFE1_STOP_POLICY 1
|
| 704 |
+
DFE2_STOP_POLICY 1
|
| 705 |
+
DFE3_STOP_POLICY 1
|
| 706 |
+
DFE4_STOP_POLICY 1
|
| 707 |
+
LOOKAHEAD_BUF_SIZE 0
|
| 708 |
+
DEBUG_CYCLE_START 0 0
|
| 709 |
+
DEBUG_CYCLE_STOP 0 -1
|
| 710 |
+
DEBUG_TIME_START 0
|
| 711 |
+
DEBUG_TIME_STOP 0
|
| 712 |
+
DEBUG_INST_START 0 0
|
| 713 |
+
DEBUG_INST_STOP 0 -1
|
| 714 |
+
DEBUG_OP_START 0
|
| 715 |
+
DEBUG_OP_STOP 0
|
| 716 |
+
DEBUG_CACHE_LIB FALSE
|
| 717 |
+
DEBUG_HASH_LIB FALSE
|
| 718 |
+
DEBUG_LIST_LIB FALSE
|
| 719 |
+
DEBUG_PORT_LIB FALSE
|
| 720 |
+
DEBUG_BUS_LIB FALSE
|
| 721 |
+
DEBUG_OP_POOL FALSE
|
| 722 |
+
DEBUG_ORACLE FALSE
|
| 723 |
+
DEBUG_FRONTEND FALSE
|
| 724 |
+
DEBUG_ADDR_TRANS FALSE
|
| 725 |
+
DEBUG_BP FALSE
|
| 726 |
+
DEBUG_BP_DIR FALSE
|
| 727 |
+
DEBUG_BTB FALSE
|
| 728 |
+
DEBUG_CRS FALSE
|
| 729 |
+
DEBUG_MAP FALSE
|
| 730 |
+
DEBUG_MEMORY FALSE
|
| 731 |
+
DEBUG_REPLAY FALSE
|
| 732 |
+
DEBUG_FREQ FALSE
|
| 733 |
+
DEBUG_MODEL FALSE
|
| 734 |
+
DEBUG_THREAD FALSE
|
| 735 |
+
DEBUG_DECOUPLED_FE FALSE
|
| 736 |
+
DEBUG_CONF FALSE
|
| 737 |
+
DEBUG_ICACHE_STAGE FALSE
|
| 738 |
+
DEBUG_DECODE_STAGE FALSE
|
| 739 |
+
DEBUG_CPP_CACHE FALSE
|
| 740 |
+
DEBUG_UOP_CACHE FALSE
|
| 741 |
+
DEBUG_UOP_QUEUE_STAGE FALSE
|
| 742 |
+
DEBUG_IDQ_STAGE FALSE
|
| 743 |
+
DEBUG_MAP_STAGE FALSE
|
| 744 |
+
DEBUG_NODE_STAGE FALSE
|
| 745 |
+
DEBUG_EXEC_STAGE FALSE
|
| 746 |
+
DEBUG_DCACHE_STAGE FALSE
|
| 747 |
+
DEBUG_RETIRED_UOPS FALSE
|
| 748 |
+
DEBUG_EXC_INSERTS FALSE
|
| 749 |
+
DEBUG_BP_CONF FALSE
|
| 750 |
+
DEBUG_ONPATH_CONF FALSE
|
| 751 |
+
DEBUG_STREAM FALSE
|
| 752 |
+
DEBUG_STREAM_MEM FALSE
|
| 753 |
+
DEBUG_WAY FALSE
|
| 754 |
+
DEBUG_L2MARKV FALSE
|
| 755 |
+
DEBUG_L2L1PREF FALSE
|
| 756 |
+
DEBUG_PERF_PRED FALSE
|
| 757 |
+
DEBUG_POWER_UTILS FALSE
|
| 758 |
+
DEBUG_DVFS FALSE
|
| 759 |
+
DEBUG_TRACE_READ FALSE
|
| 760 |
+
DEBUG_INST_FIELDS FALSE
|
| 761 |
+
DEBUG_OP_FIELDS FALSE
|
| 762 |
+
DEBUG_PIN_EXEC_DRIVEN FALSE
|
| 763 |
+
DEBUG_CACHE_PART FALSE
|
| 764 |
+
DEBUG_OPTIMIZER2 FALSE
|
| 765 |
+
DEBUG_PREF FALSE
|
| 766 |
+
DEBUG_FDIP FALSE
|
| 767 |
+
DEBUG_EIP FALSE
|
| 768 |
+
DEBUG_DJOLT FALSE
|
| 769 |
+
DEBUG_FNLMMA FALSE
|
| 770 |
+
PERFECT_BP FALSE
|
| 771 |
+
PERFECT_BTB FALSE
|
| 772 |
+
PERFECT_IBP FALSE
|
| 773 |
+
PERFECT_CRS FALSE
|
| 774 |
+
PERFECT_CBR_BTB FALSE
|
| 775 |
+
PERFECT_NT_BTB FALSE 0 # deprecated, effectively always true.
|
| 776 |
+
CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle
|
| 777 |
+
UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 778 |
+
BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec.
|
| 779 |
+
BP_MECH TAGE64K_BP tage64k
|
| 780 |
+
BP_MECH_L0 BIMODAL_BP
|
| 781 |
+
BP_L0_LATENCY 1
|
| 782 |
+
BP_MAIN_LATENCY 3
|
| 783 |
+
BIMODAL_ENTRIES (4 * 1024)
|
| 784 |
+
HIST_LENGTH 16
|
| 785 |
+
PHT_CTR_BITS 2 const
|
| 786 |
+
BHT_ENTRIES (4 * 1024)
|
| 787 |
+
BHT_ASSOC 4
|
| 788 |
+
HYBRIDS_INDEX_LENGTH 16
|
| 789 |
+
HYBRIDG_HIST_LENGTH 16
|
| 790 |
+
HYBRIDP_HIST_LENGTH 16
|
| 791 |
+
FILTER_INDEX_LENGTH 16
|
| 792 |
+
USE_FILTER FALSE
|
| 793 |
+
INF_HYBRIDGP FALSE
|
| 794 |
+
BP_HASH_TOS FALSE
|
| 795 |
+
IBTB_HASH_TOS FALSE
|
| 796 |
+
BTB_MECH GENERIC_BTB generic
|
| 797 |
+
BTB_ENTRIES 12288 12288
|
| 798 |
+
BTB_ASSOC 4 4
|
| 799 |
+
BTB_NUM_BRSLOT 1
|
| 800 |
+
BTB_BLOCK_SIZE 64
|
| 801 |
+
BTB_OFF_PATH_WRITES TRUE 1
|
| 802 |
+
BTB_MAIN_LATENCY 3 3
|
| 803 |
+
BTB_L0_PRESENT FALSE 1
|
| 804 |
+
BTB_L0_ENTRIES 128 128
|
| 805 |
+
BTB_L0_ASSOC 4 4
|
| 806 |
+
BTB_L0_LATENCY 1 1
|
| 807 |
+
BTB_L1_PRESENT FALSE 1
|
| 808 |
+
BTB_L1_ENTRIES 6144 6144
|
| 809 |
+
BTB_L1_ASSOC 4 4
|
| 810 |
+
BTB_L1_LATENCY 2 2
|
| 811 |
+
ENABLE_CRS TRUE 1
|
| 812 |
+
CRS_ENTRIES 32 128
|
| 813 |
+
CRS_REALISTIC 0 1
|
| 814 |
+
ENABLE_IBP TRUE 1 # Enable the indirect branch predictor
|
| 815 |
+
USE_PAT_HIST TRUE
|
| 816 |
+
IBTB_MECH 1 tc_tagged
|
| 817 |
+
IBTB_HIST_LENGTH 16
|
| 818 |
+
IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb.
|
| 819 |
+
TARGETS_IN_HIST 4
|
| 820 |
+
TC_ENTRIES (4 * 1024) 4096
|
| 821 |
+
TC_ASSOC 4 4
|
| 822 |
+
NUM_CORR_BRANCHES 3
|
| 823 |
+
SEL_HIST_BP_ENTRIES 8192
|
| 824 |
+
SEL_HIST_LENGTH 16
|
| 825 |
+
SEL_HIST_DYN_CNT_TH 16
|
| 826 |
+
SEL_HIST_MISPRED_TH 4
|
| 827 |
+
ENABLE_BP_CONF FALSE
|
| 828 |
+
CONF_MECH 0
|
| 829 |
+
PERF_BP_CONF_PRED FALSE
|
| 830 |
+
BPC_BITS 16
|
| 831 |
+
BPC_MECH 1
|
| 832 |
+
BPC_CTR_RESET TRUE
|
| 833 |
+
BPC_CIT_BITS 8
|
| 834 |
+
BPC_CIT_TH 50
|
| 835 |
+
BPC_CTR_BITS 3
|
| 836 |
+
OPC_COUNT_ZEROS FALSE
|
| 837 |
+
OPC_COUNT_THRESH 10
|
| 838 |
+
INF_LOOP FALSE
|
| 839 |
+
INF_LOOP_BUCKETS 811
|
| 840 |
+
LOOP_ENTRIES (4 * 1024)
|
| 841 |
+
LOOP_ASSOC 4
|
| 842 |
+
LOOP_COUNT_MAX 127
|
| 843 |
+
LOOP_REPEAT_MAX 15
|
| 844 |
+
KNOB_PRINT_BRINFO FALSE
|
| 845 |
+
BR_MISPRED_FILE NULL
|
| 846 |
+
SPEC_LEVEL 3
|
| 847 |
+
RANDOM_DETERMINISTIC TRUE
|
| 848 |
+
TAGESCL64KB_SC TRUE
|
| 849 |
+
TAGESCL64KB_LOOP TRUE
|
| 850 |
+
TAGESCL64KB_ALT TRUE
|
| 851 |
+
CONF_PERCEPTRON_TH 0
|
| 852 |
+
CONF_PERCEPTRON_CTR_BITS 8
|
| 853 |
+
CONF_PERCEPTRON_ENTRIES 127
|
| 854 |
+
CONF_PERCEPTRON_THRESH_OVRD 0
|
| 855 |
+
CONF_HIST_LENGTH 32
|
| 856 |
+
PERCEPTRON_CONF_USE_CONF FALSE
|
| 857 |
+
PERCEPTRON_CONF_TRAIN_HIS FALSE
|
| 858 |
+
PERCEPTRON_CONF_TRAIN_CONF FALSE
|
| 859 |
+
PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE
|
| 860 |
+
PERCEPTRON_TRAIN_MISP_FACTOR 1
|
| 861 |
+
PERCEPTRON_TRAIN_CORR_FACTOR 1
|
| 862 |
+
PERCEPTRON_CONF_HIS_BOTH FALSE
|
| 863 |
+
PERCEPTRON_CONF_HIS_BOTH_LENGTH 4
|
| 864 |
+
MTAGE_REALISTIC_SC_40K FALSE
|
| 865 |
+
MTAGE_REALISTIC_SC_100K FALSE
|
| 866 |
+
H2P_TABLE_BUCKETS 16384
|
| 867 |
+
H2P_MIN_EXEC 5000
|
| 868 |
+
H2P_MIN_MISPRED 333
|
| 869 |
+
H2P_MISPRED_RATIO_PERMIL 10
|
| 870 |
+
H2P_TRACK_CBR TRUE
|
| 871 |
+
H2P_TRACK_REP TRUE
|
| 872 |
+
H2P_TRACK_CALL FALSE
|
| 873 |
+
H2P_TRACK_IBR FALSE
|
| 874 |
+
H2P_TRACK_ICALL FALSE
|
| 875 |
+
H2P_TRACK_RET FALSE
|
| 876 |
+
POWER_INTF_ON FALSE
|
| 877 |
+
POWER_INTF_ENABLE_SCALING FALSE
|
| 878 |
+
POWER_INTF_EXEC "power/power_intf.py"
|
| 879 |
+
POWER_INTF_REF_CHIP_TECH_NM 22
|
| 880 |
+
POWER_INTF_REF_CHIP_FREQ (3.2e9)
|
| 881 |
+
POWER_INTF_REF_MEMORY_FREQ (0.8e9)
|
| 882 |
+
POWER_OTHER (0.0)
|
| 883 |
+
PREF_STREAM_ON FALSE 1
|
| 884 |
+
PREF_STREAM_PER_CORE_ENABLE FALSE
|
| 885 |
+
STREAM_BUFFER_N 16
|
| 886 |
+
STREAM_PREFETCH_N 2 4
|
| 887 |
+
STREAM_START_DIS 5 1
|
| 888 |
+
STREAM_LENGTH 16 64
|
| 889 |
+
STREAM_FULL_N 1
|
| 890 |
+
STREAM_TRAIN_LENGTH 16
|
| 891 |
+
STREAM_TRAIN_NUM 1 4
|
| 892 |
+
PREF_ACC_USE_CACHE FALSE
|
| 893 |
+
STREAM_STALL_ON_QUEUE_FULL FALSE
|
| 894 |
+
PREF_SCHEDULE_NUM 4
|
| 895 |
+
TRAIN_FILTER_SIZE 32
|
| 896 |
+
PREF_REQ_Q_SIZE 64
|
| 897 |
+
STREAM_CREATE_ON_DC_MISS FALSE 0
|
| 898 |
+
STREAM_CREATE_ON_L1_MISS TRUE 1
|
| 899 |
+
STREAM_TRAIN_ON_WRONGPATH TRUE
|
| 900 |
+
STREAM_CREATE_ON_WRONGPATH TRUE
|
| 901 |
+
STREAM_PREF_INTO_DCACHE FALSE
|
| 902 |
+
REMOVE_REDUNDANT_STREAM FALSE
|
| 903 |
+
L2HIT_STREAM_SCHEDULE_NUM 4
|
| 904 |
+
PREF_REQ_QUEUE_FILTER_ON FALSE
|
| 905 |
+
HW_PREF_HIT_TRAIN_STREAM FALSE
|
| 906 |
+
L2HIT_STREAM_BUFFER_N 32
|
| 907 |
+
L2HIT_STREAM_PREFETCH_N 2
|
| 908 |
+
L2HIT_STREAM_START_DIS 2
|
| 909 |
+
L2HIT_STREAM_LENGTH 8
|
| 910 |
+
L2HIT_PREF_REQ_Q_SIZE 128
|
| 911 |
+
L2HIT_L2ACCESS_REQ_Q_SIZE 64
|
| 912 |
+
PREF_STREAM_ACCPERSTREAM FALSE
|
| 913 |
+
PREF_ACC_DISTANCE_10 128
|
| 914 |
+
PREF_FRAMEWORK_ON FALSE 1
|
| 915 |
+
PREF_TRACE_ON FALSE
|
| 916 |
+
PREF_UMLC_ON FALSE
|
| 917 |
+
PREF_UL1_ON TRUE
|
| 918 |
+
PREF_DL0REQ_QUEUE_SIZE 32
|
| 919 |
+
PREF_UMLC_REQ_QUEUE_SIZE 64
|
| 920 |
+
PREF_UL1REQ_QUEUE_SIZE 128
|
| 921 |
+
PREF_SHARED_QUEUES TRUE
|
| 922 |
+
PREF_DL0_MISS_ON TRUE
|
| 923 |
+
PREF_DL0_HIT_ON TRUE
|
| 924 |
+
PREF_DL0REQ_QUEUE_FILTER_ON TRUE
|
| 925 |
+
PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE
|
| 926 |
+
PREF_UL1REQ_QUEUE_FILTER_ON TRUE
|
| 927 |
+
PREF_DL0REQ_ADD_FILTER_ON TRUE
|
| 928 |
+
PREF_UMLC_REQ_ADD_FILTER_ON TRUE
|
| 929 |
+
PREF_UL1REQ_ADD_FILTER_ON TRUE
|
| 930 |
+
PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 931 |
+
PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 932 |
+
PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1
|
| 933 |
+
PREF_DL0SCHEDULE_NUM 4
|
| 934 |
+
PREF_UMLC_SCHEDULE_NUM 4
|
| 935 |
+
PREF_UL1SCHEDULE_NUM 4
|
| 936 |
+
PREF_L1Q_DEMAND_RESERVE 0
|
| 937 |
+
PREF_REPORT_PREF_MATCH_AS_MISS FALSE
|
| 938 |
+
PREF_REPORT_PREF_MATCH_AS_HIT TRUE
|
| 939 |
+
PREF_UPDATE_ON_WRONGPATH TRUE
|
| 940 |
+
PREF_TRAIN_ON_PREF_MISSES FALSE 0
|
| 941 |
+
PREF_ORACLE_TRAIN_ON FALSE 0
|
| 942 |
+
PREF_REQ_DROP FALSE
|
| 943 |
+
PREF_THROTTLE_ON FALSE
|
| 944 |
+
PREF_THROTTLEFB_ON FALSE 1
|
| 945 |
+
PREF_ACC_THRESH_1 0.90 0.75
|
| 946 |
+
PREF_ACC_THRESH_2 0.70 0.4
|
| 947 |
+
PREF_ACC_THRESH_3 0.60 0.4
|
| 948 |
+
PREF_ACC_THRESH_4 0.40
|
| 949 |
+
PREF_UPDATE_INTERVAL 0 8192
|
| 950 |
+
PREF_ANALYZE_LOAD FALSE
|
| 951 |
+
PREF_POL_THRESH_1 0.25
|
| 952 |
+
PREF_POL_THRESH_2 0.10
|
| 953 |
+
PREF_POLBV_ON FALSE
|
| 954 |
+
PREF_POLBV_SIZE 1024
|
| 955 |
+
PREF_TIMELY_THRESH 0.05 0.01
|
| 956 |
+
PREF_POLPF_THRESH 0.01 0.005
|
| 957 |
+
PREF_DEGFB_USEONLYACC FALSE
|
| 958 |
+
PREF_DEGFB_USEONLYPOL FALSE
|
| 959 |
+
PREF_DEGFB_USEONLYLATE FALSE
|
| 960 |
+
PREF_TIMELY_THRESH_2 0.005
|
| 961 |
+
PREF_DEGFB_STATPHASEFILE FALSE
|
| 962 |
+
PREF_MAX_DEGFB 4
|
| 963 |
+
PREF_DHAL FALSE
|
| 964 |
+
PREF_DHAL_SENTTHRESH 16
|
| 965 |
+
PREF_DHAL_USETHRESH_MAX 12
|
| 966 |
+
PREF_DHAL_USETHRESH_MIN2 8
|
| 967 |
+
PREF_DHAL_USETHRESH_MIN1 4
|
| 968 |
+
PREF_DHAL_MAXDEG 64
|
| 969 |
+
PREF_HFILTER_ON FALSE
|
| 970 |
+
PREF_HFILTER_INDEX_BITS 12
|
| 971 |
+
PREF_HFILTER_USE_PC FALSE
|
| 972 |
+
PREF_HFILTER_PRED_USELESS_THRES 2
|
| 973 |
+
PREF_HFILTER_RESET_ENABLE FALSE
|
| 974 |
+
PREF_HFILTER_RESET_INTERVAL 100000
|
| 975 |
+
EIP_ENABLE 0
|
| 976 |
+
L1I_ENTANGLED_TABLE_INDEX_BITS 9
|
| 977 |
+
L1I_ENTANGLED_TABLE_WAYS 16
|
| 978 |
+
DJOLT_ENABLE 0
|
| 979 |
+
FNLMMA_ENABLE 0
|
| 980 |
+
FDIP_ENABLE 1
|
| 981 |
+
FDIP_ALWAYS_PREFETCH FALSE
|
| 982 |
+
PERFECT_FDIP FALSE
|
| 983 |
+
IPRF_MAX_FTQ_ENTRY_CYC 2
|
| 984 |
+
FDIP_BLOOM_FILTER FALSE
|
| 985 |
+
FDIP_BLOOM_ENTRIES 4000
|
| 986 |
+
FDIP_BLOOM2_ENTRIES 1000
|
| 987 |
+
FDIP_BLOOM4_ENTRIES 1000
|
| 988 |
+
FDIP_BLOOM_SIZE 16384
|
| 989 |
+
FDIP_BLOOM_HASHES 6
|
| 990 |
+
FDIP_BLOOM_CLEAR_UNUSEFUL_RATIO 0.95
|
| 991 |
+
FDIP_BLOOM_CLEAR_CYC_PERIOD 10000
|
| 992 |
+
FDIP_UTILITY_HASH_ENABLE 0
|
| 993 |
+
FDIP_UTILITY_PREF_POLICY 0
|
| 994 |
+
FDIP_ADJUSTABLE_FTQ 0
|
| 995 |
+
FDIP_ADJUSTABLE_FTQ_CYC 100000
|
| 996 |
+
UTILITY_RATIO_THRESHOLD 0.58
|
| 997 |
+
TIMELINESS_RATIO_THRESHOLD 0.82
|
| 998 |
+
FDIP_PREF_NO_LATENCY FALSE
|
| 999 |
+
UDP_USEFUL_THRESHOLD 0
|
| 1000 |
+
UDP_WEIGHT_USEFUL 4
|
| 1001 |
+
UDP_WEIGHT_UNUSEFUL 1
|
| 1002 |
+
UDP_WEIGHT_POSITIVE_SATURATION 2147483647
|
| 1003 |
+
FDIP_GHIST_HASHING FALSE
|
| 1004 |
+
FDIP_UTILITY_ONLY_TRAIN_OFF_PATH FALSE
|
| 1005 |
+
FDIP_GHIST_BITS 8
|
| 1006 |
+
UFTQ_MIN_FTQ_BLOCK_NUM 4
|
| 1007 |
+
UFTQ_MAX_FTQ_BLOCK_NUM 64
|
| 1008 |
+
FDIP_SENIORITY_FTQ_HOLD_CYC 30000
|
| 1009 |
+
FDIP_PERFECT_PREFETCH FALSE
|
| 1010 |
+
FDIP_FREEZE_AT_MEM_BUF_LIMIT TRUE
|
| 1011 |
+
FDIP_DUAL_PATH_PREF_IC_ENABLE FALSE
|
| 1012 |
+
FDIP_DUAL_PATH_PREF_UOC_ENABLE FALSE
|
| 1013 |
+
TOP_MISPRED_BR_FILEPATH "br_resteer_coverage.csv"
|
| 1014 |
+
TOP_MISPRED_BR_RESTEER_COVERAGE 0
|
| 1015 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_ENABLE FALSE
|
| 1016 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_MISPRED_THRESHOLD 1
|
| 1017 |
+
FDIP_PRINT_CL_INFO FALSE
|
| 1018 |
+
BRANCH_MISPREDICTION_TABLE_SIZE 0
|
| 1019 |
+
UOC_PREF FALSE
|
| 1020 |
+
UOC_ORACLE_PREF FALSE
|
| 1021 |
+
UOC_ZERO_LATENCY_PREF FALSE
|
| 1022 |
+
L2L1PREF_ON FALSE
|
| 1023 |
+
L2WAY_PREF FALSE
|
| 1024 |
+
L2MARKV_PREF_ON FALSE
|
| 1025 |
+
L2NEXT_PREF_ON FALSE
|
| 1026 |
+
L2HIT_STREAM_PREF_ON FALSE
|
| 1027 |
+
L2L1_DC_HIT_TRAIN FALSE
|
| 1028 |
+
L1_HIT_DUMP_FILE_ON FALSE
|
| 1029 |
+
L1_HIT_DUMP_WO_TXT FALSE
|
| 1030 |
+
L1_HIT_DUMPFILE "l1hit_dump.out"
|
| 1031 |
+
IDEAL_L2_L1_PREFETCHER FALSE
|
| 1032 |
+
IDEAL_L2_ICACHE_PREFETCHER FALSE
|
| 1033 |
+
L1WAY_PREF_SEND_QUEUE 4
|
| 1034 |
+
L1PREF_REQ_QUEUE_SIZE 1024
|
| 1035 |
+
L1PREF_IMMEDIATE FALSE
|
| 1036 |
+
L1WAY_PREF_TIMER_DIS 1000
|
| 1037 |
+
L1MARKV_PREF_SEND_QUEUE 4
|
| 1038 |
+
L1PREF_MARKV_REQ_QUEUE_SIZE 1024
|
| 1039 |
+
MARKV_L2ACCESS_REQ_Q_SIZE 64
|
| 1040 |
+
L1MARKV_PREF_IMMEDIATE FALSE
|
| 1041 |
+
L1MARKV_PREF_TIMER_DIS 1
|
| 1042 |
+
L2L1_HIT_TRAIN TRUE
|
| 1043 |
+
L1MARKV_REQ_TH 1
|
| 1044 |
+
L2L1_IMMEDIATE_PREF_CACHE FALSE
|
| 1045 |
+
L2L1_FILL_PREF_CACHE FALSE
|
| 1046 |
+
L2L1_L2_HIT_STAT FALSE
|
| 1047 |
+
PREF_GHB_ON FALSE
|
| 1048 |
+
DEBUG_PREF_GHB FALSE
|
| 1049 |
+
PREF_GHB_BUFFER_N 1024
|
| 1050 |
+
PREF_GHB_INDEX_N 128
|
| 1051 |
+
PREF_GHB_CZONE_BITS 12
|
| 1052 |
+
PREF_GHB_DEGREE 16
|
| 1053 |
+
PREF_GHB_MAX_DEGREE 32
|
| 1054 |
+
PREF_STRIDE_ON FALSE
|
| 1055 |
+
DEBUG_PREF_STRIDE FALSE
|
| 1056 |
+
PREF_STRIDE_TABLE_N 1024
|
| 1057 |
+
PREF_STRIDE_REGION_BITS 16
|
| 1058 |
+
PREF_STRIDE_DEGREE 4
|
| 1059 |
+
PREF_STRIDE_DISTANCE 16
|
| 1060 |
+
PREF_STRIDE_STARTDISTANCE 1
|
| 1061 |
+
PREF_STRIDE_SINGLE_THRESH 6
|
| 1062 |
+
PREF_STRIDE_MULTI_THRESH 6
|
| 1063 |
+
PREF_STRIDE_SINGLE_STRIDE_MODE FALSE
|
| 1064 |
+
PREF_STRIDEPC_ON FALSE
|
| 1065 |
+
DEBUG_PREF_STRIDEPC FALSE
|
| 1066 |
+
PREF_STRIDEPC_TABLE_N 1024
|
| 1067 |
+
PREF_STRIDEPC_DEGREE 4
|
| 1068 |
+
PREF_STRIDEPC_DISTANCE 16
|
| 1069 |
+
PREF_STRIDEPC_USELOADADDR FALSE
|
| 1070 |
+
PREF_STRIDEPC_TRAINNUM 2
|
| 1071 |
+
PREF_STRIDEPC_STARTDIS 4
|
| 1072 |
+
PREF_PHASE_ON FALSE
|
| 1073 |
+
PREF_PHASE_STUDY FALSE
|
| 1074 |
+
DEBUG_PREF_PHASE FALSE
|
| 1075 |
+
PREF_PHASE_PRIME_HASH 16381
|
| 1076 |
+
PREF_PHASE_INFOSIZE 16384
|
| 1077 |
+
PREF_PHASE_LOG2REGIONSIZE 12
|
| 1078 |
+
PREF_PHASE_REGIONENTRIES 64
|
| 1079 |
+
PREF_PHASE_TRACKEDREGIONS 32
|
| 1080 |
+
PREF_PHASE_INTERVAL 100000
|
| 1081 |
+
PREF_PHASE_TABLE_SIZE 64
|
| 1082 |
+
PREF_PHASE_MAXDIFF_THRESH 64
|
| 1083 |
+
PREF_PHASE_MIN_MISSES 64
|
| 1084 |
+
PREF_PHASE_MISSPER 0.4
|
| 1085 |
+
PREF_2DC_ON FALSE
|
| 1086 |
+
DEBUG_PREF_2DC FALSE
|
| 1087 |
+
PREF_2DC_CACHE_SIZE (1 * 1024)
|
| 1088 |
+
PREF_2DC_CACHE_ASSOC 4
|
| 1089 |
+
PREF_2DC_CACHE_LINE_SIZE 1
|
| 1090 |
+
PREF_2DC_DEGREE 16
|
| 1091 |
+
PREF_2DC_ZONE_SHIFT 10
|
| 1092 |
+
PREF_2DC_TAG_SIZE 16
|
| 1093 |
+
PREF_2DC_NUM_REGIONS 64
|
| 1094 |
+
PREF_2DC_REGION_HASH 61
|
| 1095 |
+
PREF_MARKOV_ON FALSE
|
| 1096 |
+
DEBUG_PREF_MARKOV FALSE
|
| 1097 |
+
PREF_MARKOV_NUM_ENTRIES 65536
|
| 1098 |
+
PREF_MARKOV_NUM_NEXT_STATES 8
|
| 1099 |
+
PREF_MARKOV_SEND_ON_PREF_HIT TRUE
|
| 1100 |
+
PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE
|
| 1101 |
+
PREF_MARKOV_TABLE_UPDATE_POLICY 0
|
| 1102 |
+
PREF_MARKOV_SEND_THRESHOLD 0
|
sssp_facebook/fingerprint/run_0/sim.log
ADDED
|
@@ -0,0 +1,44 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
[0]: ad: 0x7ffff3d9b7c1, op: 427
|
| 2 |
+
[0]: ad: 0x7ffff3d9b7c8, op: 427
|
| 3 |
+
[0]: ad: 0x7ffff3d9b7cc, op: 847
|
| 4 |
+
[0]: ad: 0x7ffff3d9b7cf, op: 330
|
| 5 |
+
new bb detected: 1
|
| 6 |
+
[1]: ad: 0x7ffff3d9b7b0, op: 388
|
| 7 |
+
[1]: ad: 0x7ffff3d9b7b3, op: 8
|
| 8 |
+
[1]: ad: 0x7ffff3d9b7b7, op: 109
|
| 9 |
+
[1]: ad: 0x7ffff3d9b7bb, op: 315
|
| 10 |
+
new bb detected: 2
|
| 11 |
+
Scarab gitrev: 7185dea
|
| 12 |
+
Warning: Scarab expects the trace file type to include OFFLINE_FILE_TYPE_ARCH_REGDEPS (0x20000), but got type: 0xe40
|
| 13 |
+
Scarab started at Fri Jul 17 23:07:24 2026
|
| 14 |
+
|
| 15 |
+
read from initialization: 0x7ffff3d9b7c1
|
| 16 |
+
advanceReader: ROI end reached (ordinal 10000002 > roi_end 10000000)
|
| 17 |
+
Reached end of trace (last_inst) pc=0x7ffff3d9b7c1
|
| 18 |
+
to be appened segment num 1
|
| 19 |
+
10000000
|
| 20 |
+
10000000
|
| 21 |
+
====================================
|
| 22 |
+
TRACE_INST_TAKEN_NOT_CF:0
|
| 23 |
+
TRACE_INST_TAKEN_CF_BR:0
|
| 24 |
+
TRACE_INST_TAKEN_CF_CBR:1250000
|
| 25 |
+
TRACE_INST_TAKEN_CF_REP:0
|
| 26 |
+
TRACE_INST_TAKEN_CF_CALL:0
|
| 27 |
+
TRACE_INST_TAKEN_CF_IBR:0
|
| 28 |
+
TRACE_INST_TAKEN_CF_ICALL:0
|
| 29 |
+
TRACE_INST_TAKEN_CF_ICO:0
|
| 30 |
+
TRACE_INST_TAKEN_CF_RET:0
|
| 31 |
+
TRACE_INST_TAKEN_CF_SYS:0
|
| 32 |
+
====================================
|
| 33 |
+
identity within this segment
|
| 34 |
+
0 / 2
|
| 35 |
+
========================================================
|
| 36 |
+
Number of blocks built : 2
|
| 37 |
+
Average size : 4.00 instructions
|
| 38 |
+
Number of blocks executed : 2500000
|
| 39 |
+
Average weighted size : 4.00 instructions
|
| 40 |
+
Number of total instructions : 10000000
|
| 41 |
+
Number of fetched instruction : 10000000
|
| 42 |
+
========================================================
|
| 43 |
+
Scarab finished at Fri Jul 17 23:07:28 2026
|
| 44 |
+
|
sssp_facebook/fingerprint/run_1/PARAMS.in
ADDED
|
@@ -0,0 +1,268 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# File : PARAMS.golden_cove
|
| 2 |
+
# Date : 02/27/25
|
| 3 |
+
# Description : Golden Cove Configuration
|
| 4 |
+
# Author : Surim Oh <[email protected]>
|
| 5 |
+
#
|
| 6 |
+
# Based on documentation found here:
|
| 7 |
+
# https://en.wikipedia.org/wiki/Golden_Cove
|
| 8 |
+
# https://en.wikichip.org/wiki/intel/microarchitectures/golden_cove
|
| 9 |
+
# https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/3
|
| 10 |
+
|
| 11 |
+
## Simulation Parameters
|
| 12 |
+
--mode full
|
| 13 |
+
--model cmp
|
| 14 |
+
--sim_limit none
|
| 15 |
+
|
| 16 |
+
## Core Parameters
|
| 17 |
+
|
| 18 |
+
# Femptoseconds, 3.2GHz, used for energy estimates.
|
| 19 |
+
--chip_cycle_time 312500
|
| 20 |
+
|
| 21 |
+
|
| 22 |
+
### Fetch Stage
|
| 23 |
+
--fetch_off_path_ops 1
|
| 24 |
+
|
| 25 |
+
#### ICache
|
| 26 |
+
--icache_size 32768
|
| 27 |
+
--icache_assoc 8
|
| 28 |
+
--icache_line_size 64
|
| 29 |
+
|
| 30 |
+
### Uop Cache
|
| 31 |
+
# inclusive w/ L1i
|
| 32 |
+
--uop_cache_enable 1
|
| 33 |
+
--uop_cache_width 8
|
| 34 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 35 |
+
--uop_cache_assoc 8
|
| 36 |
+
--iprf_on_uop_cache_hit 1
|
| 37 |
+
|
| 38 |
+
### Branch Predictor
|
| 39 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 40 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 41 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 42 |
+
--bp_mech tage64k
|
| 43 |
+
|
| 44 |
+
|
| 45 |
+
#### BTB
|
| 46 |
+
|
| 47 |
+
# TODO
|
| 48 |
+
# multi-level BTB
|
| 49 |
+
# 128 entry L0 BTB
|
| 50 |
+
# 6144 entry L1 BTB
|
| 51 |
+
# 12888 entry L2 BTB
|
| 52 |
+
# ~2 entry Return Stack
|
| 53 |
+
# roughly 2x8192 for now
|
| 54 |
+
# BTB model to use.
|
| 55 |
+
--btb_mech generic
|
| 56 |
+
--btb_entries 12288
|
| 57 |
+
--btb_assoc 4
|
| 58 |
+
--btb_main_latency 3
|
| 59 |
+
--btb_l0_present 1
|
| 60 |
+
--btb_l0_entries 128
|
| 61 |
+
--btb_l0_assoc 4
|
| 62 |
+
--btb_l0_latency 1
|
| 63 |
+
--btb_l1_present 1
|
| 64 |
+
--btb_l1_entries 6144
|
| 65 |
+
--btb_l1_assoc 4
|
| 66 |
+
--btb_l1_latency 2
|
| 67 |
+
|
| 68 |
+
# Allow the BTB to be updated by off path ops.
|
| 69 |
+
--btb_off_path_writes 1
|
| 70 |
+
|
| 71 |
+
# NT branches are not inserted in BTB, but do not trigger resteer
|
| 72 |
+
# since we continue without a control flow change
|
| 73 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 74 |
+
|
| 75 |
+
#### CRS
|
| 76 |
+
|
| 77 |
+
# Enable return stack
|
| 78 |
+
--enable_crs 1
|
| 79 |
+
--crs_entries 128
|
| 80 |
+
--crs_realistic 1
|
| 81 |
+
|
| 82 |
+
### iBP
|
| 83 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 84 |
+
--ibtb_mech tc_tagged
|
| 85 |
+
# iBTB Model. tc_tagless, tc_tagged, tc_hybrid.
|
| 86 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 87 |
+
--tc_entries 4096
|
| 88 |
+
--tc_assoc 4
|
| 89 |
+
|
| 90 |
+
### Decode Stage
|
| 91 |
+
--decode_width 6
|
| 92 |
+
--decode_cycles 5
|
| 93 |
+
|
| 94 |
+
### Instruction Decode Queue
|
| 95 |
+
--idq_size 144
|
| 96 |
+
|
| 97 |
+
### Map Stage
|
| 98 |
+
--map_cycles 5
|
| 99 |
+
|
| 100 |
+
# register renaming table
|
| 101 |
+
--reg_renaming_scheme 1
|
| 102 |
+
--reg_table_integer_physical_size 280
|
| 103 |
+
--reg_table_vector_physical_size 332
|
| 104 |
+
|
| 105 |
+
### Issue Stage
|
| 106 |
+
|
| 107 |
+
# Max number of instructions to be renamed, and issued per cycle.
|
| 108 |
+
--issue_width 6
|
| 109 |
+
|
| 110 |
+
--rs_fill_width 0
|
| 111 |
+
# rs_sizes ~205 in total, and they are split into three different reservation stations (RS1, RS2, RS3) where each has 97, 70, 38 entries respectively
|
| 112 |
+
# original architecture
|
| 113 |
+
# RS1 connected to port 0,1,5,6,10
|
| 114 |
+
# RS2 connected to port 2,3,11
|
| 115 |
+
# RS3 connected to port 7,8,4,9
|
| 116 |
+
# scarab does not split ST AGU port and ST port, merge them
|
| 117 |
+
# adjusted architecture to scarab ST AGU (port 4 and 9 removed. rs_size reduced to 186 from 205)
|
| 118 |
+
# RS1 connected to port 0,1,4,5,8
|
| 119 |
+
# RS2 connected to port 2,3,9
|
| 120 |
+
# RS3 connected to port 6,7 (port 4,9 removed, entries reduced to 19 from 38)
|
| 121 |
+
--rs_sizes 97 70 19
|
| 122 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 123 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 124 |
+
|
| 125 |
+
### Exec Stage
|
| 126 |
+
|
| 127 |
+
### DCache
|
| 128 |
+
--dcache_size 49152
|
| 129 |
+
--dcache_read_ports 1
|
| 130 |
+
--dcache_write_ports 1
|
| 131 |
+
--dcache_banks 8
|
| 132 |
+
--dcache_assoc 12
|
| 133 |
+
--dcache_line_size 64
|
| 134 |
+
--dcache_cycles 5
|
| 135 |
+
|
| 136 |
+
### Reorder/Retire Stage
|
| 137 |
+
|
| 138 |
+
# Max number of instructions to be retired per cycle.
|
| 139 |
+
--node_ret_width 8
|
| 140 |
+
--node_table_size 512
|
| 141 |
+
|
| 142 |
+
# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does
|
| 143 |
+
--stores_do_not_block_window 1
|
| 144 |
+
|
| 145 |
+
# TODO: confirm what this knob does
|
| 146 |
+
--prefs_do_not_block_window 1
|
| 147 |
+
|
| 148 |
+
|
| 149 |
+
## Uncore
|
| 150 |
+
|
| 151 |
+
### Mid-level cache
|
| 152 |
+
|
| 153 |
+
# Enable use of a midlevel cache between i/d and L1
|
| 154 |
+
# client 1.25 MiB (1310720 bytes) per core, 8-way, 15 cycles
|
| 155 |
+
# server 2 MiB (2097000 bytes) per core, 8-way, 16 cycles
|
| 156 |
+
--mlc_present 1
|
| 157 |
+
--mlc_size 2097000
|
| 158 |
+
--mlc_assoc 8
|
| 159 |
+
--mlc_cycles 16
|
| 160 |
+
|
| 161 |
+
|
| 162 |
+
### LLC
|
| 163 |
+
# 3 MiB per core, 16-way
|
| 164 |
+
--l1_size 3145728
|
| 165 |
+
--l1_banks 8
|
| 166 |
+
--l1_cycles 36 // just a guess
|
| 167 |
+
--l1_assoc 16
|
| 168 |
+
--l1_line_size 64
|
| 169 |
+
--l1_interleave_factor 64
|
| 170 |
+
|
| 171 |
+
|
| 172 |
+
### prefetcher
|
| 173 |
+
# Kept same as Kaby Lake
|
| 174 |
+
--pref_framework_on 1
|
| 175 |
+
--pref_stream_on 1
|
| 176 |
+
--pref_train_on_pref_misses 0
|
| 177 |
+
--pref_oracle_train 0
|
| 178 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 179 |
+
|
| 180 |
+
--stream_length 64
|
| 181 |
+
--stream_prefetch_n 4
|
| 182 |
+
--stream_start_dis 1
|
| 183 |
+
--stream_train_num 4
|
| 184 |
+
--stream_create_on_dc_miss 0
|
| 185 |
+
--stream_create_on_l1_miss 1
|
| 186 |
+
|
| 187 |
+
--pref_throttlefb_on=1
|
| 188 |
+
--pref_acc_thresh_1=0.75
|
| 189 |
+
--pref_acc_thresh_2=0.4
|
| 190 |
+
--pref_acc_thresh_3=0.4
|
| 191 |
+
--pref_timely_thresh=0.01
|
| 192 |
+
--pref_polpf_thresh=0.005
|
| 193 |
+
--pref_update_interval=8192
|
| 194 |
+
|
| 195 |
+
--mem_req_buffer_pref_watermark 4
|
| 196 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 197 |
+
|
| 198 |
+
### Memory
|
| 199 |
+
# Kept same as Kaby Lake
|
| 200 |
+
--addr_translation random
|
| 201 |
+
|
| 202 |
+
--mem_priority_ifetch 0
|
| 203 |
+
--mem_priority_dfetch 1
|
| 204 |
+
--mem_priority_dstore 2
|
| 205 |
+
--mem_priority_iprf 3
|
| 206 |
+
--mem_priority_dprf 4
|
| 207 |
+
--mem_priority_wb 5
|
| 208 |
+
--mem_priority_wb_nodirty 5
|
| 209 |
+
|
| 210 |
+
--mem_req_buffer_entries 32
|
| 211 |
+
--bus_width_in_bytes 8
|
| 212 |
+
|
| 213 |
+
--ramulator_standard DDR4
|
| 214 |
+
--ramulator_speed DDR4_2400R
|
| 215 |
+
--ramulator_org DDR4_8Gb_x8
|
| 216 |
+
--ramulator_channels 1
|
| 217 |
+
--ramulator_ranks 1
|
| 218 |
+
--ramulator_bankgroups 4
|
| 219 |
+
--ramulator_banks 4
|
| 220 |
+
--ramulator_chip_width 8
|
| 221 |
+
--ramulator_rows 65536
|
| 222 |
+
--ramulator_cols 1024
|
| 223 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 224 |
+
--ramulator_readq_entries 32
|
| 225 |
+
--ramulator_writeq_entries 32
|
| 226 |
+
--ramulator_record_cmd_trace FALSE
|
| 227 |
+
--ramulator_print_cmd_trace FALSE
|
| 228 |
+
--ramulator_tCK 833333
|
| 229 |
+
--ramulator_tCL 16
|
| 230 |
+
--ramulator_tCCD 6
|
| 231 |
+
--ramulator_tCCDS 4
|
| 232 |
+
--ramulator_tCCDL 6
|
| 233 |
+
--ramulator_tCWL 12
|
| 234 |
+
--ramulator_tBL 4
|
| 235 |
+
--ramulator_tWTR 9
|
| 236 |
+
--ramulator_tWTRS 3
|
| 237 |
+
--ramulator_tWTRL 9
|
| 238 |
+
--ramulator_tRP 16
|
| 239 |
+
--ramulator_tRPpb 16
|
| 240 |
+
--ramulator_tRPab 16
|
| 241 |
+
--ramulator_tRCD 16
|
| 242 |
+
--ramulator_tRCDR 16
|
| 243 |
+
--ramulator_tRCDW 16
|
| 244 |
+
--ramulator_tRAS 39
|
| 245 |
+
--dram_tech_in_nm 32
|
| 246 |
+
|
| 247 |
+
## Other
|
| 248 |
+
|
| 249 |
+
|
| 250 |
+
### Debug
|
| 251 |
+
--debug_inst_start 0
|
| 252 |
+
--debug_inst_stop -1
|
| 253 |
+
--debug_cycle_start 0
|
| 254 |
+
--debug_cycle_stop -1
|
| 255 |
+
|
| 256 |
+
|
| 257 |
+
## Stats and Params
|
| 258 |
+
--dump_params 1
|
| 259 |
+
--dump_stats 1
|
| 260 |
+
--dump_trace 0
|
| 261 |
+
|
| 262 |
+
####################################
|
| 263 |
+
--set_off_path_confirmed 1
|
| 264 |
+
|
| 265 |
+
--order_beyond_bus 1
|
| 266 |
+
|
| 267 |
+
--mem_ooo_stores 1
|
| 268 |
+
--mem_obey_store_dep 1
|
sssp_facebook/fingerprint/run_1/PARAMS.out
ADDED
|
@@ -0,0 +1,1102 @@
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|
|
| 1 |
+
--mode trace_bbv_distributed
|
| 2 |
+
--model cmp
|
| 3 |
+
--frontend memtrace
|
| 4 |
+
--sim_limit none
|
| 5 |
+
--memtrace_roi_begin 10000001
|
| 6 |
+
--memtrace_roi_end 20000000
|
| 7 |
+
--use_fetched_count 1
|
| 8 |
+
--dump_params 1
|
| 9 |
+
--dump_stats 1
|
| 10 |
+
--dump_trace 0
|
| 11 |
+
--trace_bbv_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.1
|
| 12 |
+
--trace_footprint_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.1
|
| 13 |
+
--segment_instr_count 10000000
|
| 14 |
+
--mlc_present 1
|
| 15 |
+
--mlc_size 2097000
|
| 16 |
+
--mlc_assoc 8
|
| 17 |
+
--mlc_cycles 16
|
| 18 |
+
--l1_size 3145728
|
| 19 |
+
--l1_assoc 16
|
| 20 |
+
--l1_line_size 64
|
| 21 |
+
--l1_cycles 36 // just a guess
|
| 22 |
+
--l1_banks 8
|
| 23 |
+
--l1_interleave_factor 64
|
| 24 |
+
--addr_translation random
|
| 25 |
+
--icache_size 32768
|
| 26 |
+
--icache_assoc 8
|
| 27 |
+
--icache_line_size 64
|
| 28 |
+
--uop_cache_enable 1
|
| 29 |
+
--uop_cache_width 8
|
| 30 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 31 |
+
--uop_cache_assoc 8
|
| 32 |
+
--iprf_on_uop_cache_hit 1
|
| 33 |
+
--dcache_size 49152
|
| 34 |
+
--dcache_assoc 12
|
| 35 |
+
--dcache_line_size 64
|
| 36 |
+
--dcache_cycles 5
|
| 37 |
+
--dcache_read_ports 1
|
| 38 |
+
--dcache_write_ports 1
|
| 39 |
+
--dcache_banks 8
|
| 40 |
+
--mem_ooo_stores 1
|
| 41 |
+
--mem_obey_store_dep 1
|
| 42 |
+
--mem_req_buffer_entries 32
|
| 43 |
+
--mem_priority_ifetch 0
|
| 44 |
+
--mem_priority_dfetch 1
|
| 45 |
+
--mem_priority_dstore 2
|
| 46 |
+
--mem_priority_iprf 3
|
| 47 |
+
--mem_priority_dprf 4
|
| 48 |
+
--mem_priority_wb 5
|
| 49 |
+
--mem_priority_wb_nodirty 5
|
| 50 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 51 |
+
--mem_req_buffer_pref_watermark 4
|
| 52 |
+
--order_beyond_bus 1
|
| 53 |
+
--set_off_path_confirmed 1
|
| 54 |
+
--ramulator_standard DDR4
|
| 55 |
+
--ramulator_speed DDR4_2400R
|
| 56 |
+
--ramulator_org DDR4_8Gb_x8
|
| 57 |
+
--ramulator_channels 1
|
| 58 |
+
--ramulator_ranks 1
|
| 59 |
+
--ramulator_bankgroups 4
|
| 60 |
+
--ramulator_banks 4
|
| 61 |
+
--ramulator_chip_width 8
|
| 62 |
+
--bus_width_in_bytes 8
|
| 63 |
+
--ramulator_rows 65536
|
| 64 |
+
--ramulator_cols 1024
|
| 65 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 66 |
+
--ramulator_readq_entries 32
|
| 67 |
+
--ramulator_writeq_entries 32
|
| 68 |
+
--ramulator_record_cmd_trace FALSE
|
| 69 |
+
--ramulator_print_cmd_trace FALSE
|
| 70 |
+
--ramulator_tCK 833333
|
| 71 |
+
--ramulator_tCL 16
|
| 72 |
+
--ramulator_tCCD 6
|
| 73 |
+
--ramulator_tCCDS 4
|
| 74 |
+
--ramulator_tCCDL 6
|
| 75 |
+
--ramulator_tCWL 12
|
| 76 |
+
--ramulator_tBL 4
|
| 77 |
+
--ramulator_tWTR 9
|
| 78 |
+
--ramulator_tWTRS 3
|
| 79 |
+
--ramulator_tWTRL 9
|
| 80 |
+
--ramulator_tRP 16
|
| 81 |
+
--ramulator_tRPpb 16
|
| 82 |
+
--ramulator_tRPab 16
|
| 83 |
+
--ramulator_tRCD 16
|
| 84 |
+
--ramulator_tRCDR 16
|
| 85 |
+
--ramulator_tRCDW 16
|
| 86 |
+
--ramulator_tRAS 39
|
| 87 |
+
--dram_tech_in_nm 32
|
| 88 |
+
--chip_cycle_time 312500
|
| 89 |
+
--issue_width 6
|
| 90 |
+
--rs_fill_width 0
|
| 91 |
+
--node_table_size 512
|
| 92 |
+
--node_ret_width 8
|
| 93 |
+
--decode_width 6
|
| 94 |
+
--idq_size 144
|
| 95 |
+
--reg_renaming_scheme 1
|
| 96 |
+
--reg_table_integer_physical_size 280
|
| 97 |
+
--reg_table_vector_physical_size 332
|
| 98 |
+
--rs_sizes 97 70 19
|
| 99 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 100 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 101 |
+
--decode_cycles 5
|
| 102 |
+
--map_cycles 5
|
| 103 |
+
--fetch_off_path_ops 1
|
| 104 |
+
--stores_do_not_block_window 1
|
| 105 |
+
--prefs_do_not_block_window 1
|
| 106 |
+
--cbp_trace_r0 /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 107 |
+
--debug_cycle_start 0
|
| 108 |
+
--debug_cycle_stop -1
|
| 109 |
+
--debug_inst_start 0
|
| 110 |
+
--debug_inst_stop -1
|
| 111 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 112 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 113 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 114 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 115 |
+
--bp_mech tage64k
|
| 116 |
+
--btb_mech generic
|
| 117 |
+
--btb_entries 12288
|
| 118 |
+
--btb_assoc 4
|
| 119 |
+
--btb_off_path_writes 1
|
| 120 |
+
--btb_main_latency 3
|
| 121 |
+
--btb_l0_present 1
|
| 122 |
+
--btb_l0_entries 128
|
| 123 |
+
--btb_l0_assoc 4
|
| 124 |
+
--btb_l0_latency 1
|
| 125 |
+
--btb_l1_present 1
|
| 126 |
+
--btb_l1_entries 6144
|
| 127 |
+
--btb_l1_assoc 4
|
| 128 |
+
--btb_l1_latency 2
|
| 129 |
+
--enable_crs 1
|
| 130 |
+
--crs_entries 128
|
| 131 |
+
--crs_realistic 1
|
| 132 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 133 |
+
--ibtb_mech tc_tagged
|
| 134 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 135 |
+
--tc_entries 4096
|
| 136 |
+
--tc_assoc 4
|
| 137 |
+
--pref_stream_on 1
|
| 138 |
+
--stream_prefetch_n 4
|
| 139 |
+
--stream_start_dis 1
|
| 140 |
+
--stream_length 64
|
| 141 |
+
--stream_train_num 4
|
| 142 |
+
--stream_create_on_dc_miss 0
|
| 143 |
+
--stream_create_on_l1_miss 1
|
| 144 |
+
--pref_framework_on 1
|
| 145 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 146 |
+
--pref_train_on_pref_misses 0
|
| 147 |
+
--pref_oracle_train_on 0
|
| 148 |
+
--pref_throttlefb_on 1
|
| 149 |
+
--pref_acc_thresh_1 0.75
|
| 150 |
+
--pref_acc_thresh_2 0.4
|
| 151 |
+
--pref_acc_thresh_3 0.4
|
| 152 |
+
--pref_update_interval 8192
|
| 153 |
+
--pref_timely_thresh 0.01
|
| 154 |
+
--pref_polpf_thresh 0.005
|
| 155 |
+
1 1 1 1 1 1 1
|
| 156 |
+
|
| 157 |
+
--- Cut out everything below to use this file as PARAMS.in ---
|
| 158 |
+
|
| 159 |
+
Parameter status at compile time and values supplied on the command line:
|
| 160 |
+
|
| 161 |
+
SIM_MODE 0 trace_bbv_distributed
|
| 162 |
+
SIM_MODEL 0 cmp
|
| 163 |
+
FRONTEND FE_PIN_EXEC_DRIVEN memtrace
|
| 164 |
+
INST_LIMIT NULL
|
| 165 |
+
SIM_LIMIT "none" none
|
| 166 |
+
FORWARD_PROGRESS_LIMIT 100000000
|
| 167 |
+
FORWARD_PROGRESS_INTERVAL 10000
|
| 168 |
+
FAST_FORWARD 0
|
| 169 |
+
FAST_FORWARD_TRACE_INS 0
|
| 170 |
+
FAST_FORWARD_UNTIL_ADDR 0
|
| 171 |
+
MEMTRACE_ROI_BEGIN 0 10000001
|
| 172 |
+
MEMTRACE_ROI_END 0 20000000
|
| 173 |
+
FULL_WARMUP 0
|
| 174 |
+
WARMUP 0
|
| 175 |
+
HEARTBEAT_INTERVAL 1000000
|
| 176 |
+
NUM_HEARTBEATS 0
|
| 177 |
+
USE_FETCHED_COUNT FALSE 1
|
| 178 |
+
PERIODIC_DUMP FALSE
|
| 179 |
+
FILE_TAG ""
|
| 180 |
+
OUTPUT_DIR "."
|
| 181 |
+
STATUS_FILE NULL
|
| 182 |
+
BINDIR NULL
|
| 183 |
+
DUMP_PARAMS TRUE 1
|
| 184 |
+
DUMP_STATS TRUE 1
|
| 185 |
+
DUMP_TRACE FALSE 0
|
| 186 |
+
CLEAR_STATS "never"
|
| 187 |
+
STATS_TO_TRACE NULL
|
| 188 |
+
STAT_TRACE_FILE "stats.trace"
|
| 189 |
+
STAT_TRACE_INTERVAL "i:100000"
|
| 190 |
+
PIPEVIEW FALSE
|
| 191 |
+
PIPEVIEW_FILE "pipeview"
|
| 192 |
+
MEMVIEW FALSE
|
| 193 |
+
MEMVIEW_FILE "memview.out"
|
| 194 |
+
MEMVIEW_START "never"
|
| 195 |
+
INST_HASH_TABLE_SIZE 524288 const
|
| 196 |
+
STDOUT_FILE NULL
|
| 197 |
+
STDERR_FILE NULL
|
| 198 |
+
PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp"
|
| 199 |
+
PRINT_PID FALSE
|
| 200 |
+
USE_UNSURE_FREE_LISTS FALSE
|
| 201 |
+
OPTIMIZER2_MAX_NUM_SLAVES 64
|
| 202 |
+
OPTIMIZER2_PERFECT_MEMORYLESS FALSE
|
| 203 |
+
EXIT_COND 0
|
| 204 |
+
NUM_NOPS 0
|
| 205 |
+
NOPS_BB_START 0x5000000
|
| 206 |
+
IGNORE_BAR_FETCH FALSE
|
| 207 |
+
TRACE_BBV_OUTPUT NULL /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.1
|
| 208 |
+
TRACE_FOOTPRINT_OUTPUT "" /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.1
|
| 209 |
+
SEGMENT_INSTR_COUNT 0 10000000
|
| 210 |
+
ENABLE_SWPRF FALSE
|
| 211 |
+
MLC_PRESENT FALSE 1
|
| 212 |
+
MLC_SIZE (512 * 1024) 2097000
|
| 213 |
+
MLC_ASSOC 4 8
|
| 214 |
+
MLC_LINE_SIZE 64
|
| 215 |
+
MLC_CYCLES 12 16
|
| 216 |
+
PERFECT_MLC FALSE
|
| 217 |
+
MLC_READ_PORTS 1
|
| 218 |
+
MLC_WRITE_PORTS 1
|
| 219 |
+
MLC_BANKS 8
|
| 220 |
+
MLC_INTERLEAVE_FACTOR 64
|
| 221 |
+
MLC_CACHE_REPL_POLICY 0
|
| 222 |
+
MLC_WRITE_THROUGH FALSE
|
| 223 |
+
PREFETCH_UPDATE_LRU_MLC TRUE
|
| 224 |
+
FORCE_L1_MISS FALSE
|
| 225 |
+
L1_SIZE (4 * 1024 * 1024) 3145728
|
| 226 |
+
L1_ASSOC 8 16
|
| 227 |
+
L1_LINE_SIZE 64 64
|
| 228 |
+
L1_CYCLES 24 36 // just a guess
|
| 229 |
+
PERFECT_L1 FALSE
|
| 230 |
+
PRIVATE_L1 FALSE
|
| 231 |
+
L1_READ_PORTS 1
|
| 232 |
+
L1_WRITE_PORTS 1
|
| 233 |
+
L1_BANKS 8 8
|
| 234 |
+
L1_INTERLEAVE_FACTOR 64 64
|
| 235 |
+
L1_CACHE_REPL_POLICY 0
|
| 236 |
+
L1_WRITE_THROUGH FALSE
|
| 237 |
+
L1_IGNORE_WB FALSE
|
| 238 |
+
L1_USE_CORE_FREQ FALSE
|
| 239 |
+
MARK_L1_MISSES TRUE
|
| 240 |
+
PREFETCH_UPDATE_LRU_L1 TRUE
|
| 241 |
+
MEMORY_RANDOM_ADDR FALSE
|
| 242 |
+
VA_PAGE_SIZE_BYTES 4096
|
| 243 |
+
NUM_ADDR_NON_SIGN_EXTEND_BITS 48
|
| 244 |
+
ADDR_TRANSLATION 0 random
|
| 245 |
+
CONSTANT_MEMORY_LATENCY FALSE
|
| 246 |
+
MEMORY_CYCLES 100
|
| 247 |
+
STALL_MEM_REQS_ONLY FALSE
|
| 248 |
+
ICACHE_SIZE (64 * 1024) 32768
|
| 249 |
+
ICACHE_ASSOC 4 8
|
| 250 |
+
ICACHE_LINE_SIZE 64 64
|
| 251 |
+
PERFECT_ICACHE FALSE
|
| 252 |
+
ICACHE_READ_PORTS 1
|
| 253 |
+
ICACHE_WRITE_PORTS 1
|
| 254 |
+
ICACHE_BANKS 8
|
| 255 |
+
ICACHE_REPL 0
|
| 256 |
+
UOP_CACHE_ENABLE 1 1
|
| 257 |
+
UOP_CACHE_WIDTH 6 8
|
| 258 |
+
ALWAYS_LOOKUP_ICACHE 0
|
| 259 |
+
UOP_CACHE_INSERT_ONLY_ONPATH FALSE
|
| 260 |
+
UOP_CACHE_READ_PORTS 1
|
| 261 |
+
UOP_CACHE_LINES 384 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 262 |
+
UOP_CACHE_ASSOC 8 8
|
| 263 |
+
UOP_CACHE_MAX_IMM_DISP_LINE 4
|
| 264 |
+
IPRF_ON_UOP_CACHE_HIT FALSE 1
|
| 265 |
+
UOP_CACHE_REPL 0
|
| 266 |
+
PRIORITY_LINE_STICKINESS_PERCENT 50
|
| 267 |
+
PW_PRIORITY_LIST_FILEPATH "pw_priority_list.csv"
|
| 268 |
+
NUM_PRIORITY_PWS 10
|
| 269 |
+
PRIORITIZE_PWS_AFTER_FIRST_STICKY_UNTIL_BACKEND_STALL FALSE
|
| 270 |
+
NO_REPL_AFTER_QUEUE_SIZE 0
|
| 271 |
+
FDIP_UC_SIZE 0
|
| 272 |
+
FDIP_UC_ASSOC 4
|
| 273 |
+
FDIP_UC_INSERT_REPLPOL 0
|
| 274 |
+
MAP_STAGE_CONSUME_FROM_ICACHE_AND_UOC_SAME_CYCLE TRUE
|
| 275 |
+
UOP_QUEUE_LENGTH 7
|
| 276 |
+
DCACHE_SIZE (64 * 1024) 49152
|
| 277 |
+
DCACHE_ASSOC 1 12
|
| 278 |
+
DCACHE_LINE_SIZE 64 64
|
| 279 |
+
DCACHE_CYCLES 2 5
|
| 280 |
+
PERFECT_DCACHE FALSE
|
| 281 |
+
DCACHE_READ_PORTS 8 1
|
| 282 |
+
DCACHE_WRITE_PORTS 1 1
|
| 283 |
+
DCACHE_BANKS 1 8
|
| 284 |
+
DCACHE_INTERLEAVE_FACTOR 4
|
| 285 |
+
DCACHE_REPL 0
|
| 286 |
+
DCACHE_REPL_PREF_THRESH 1
|
| 287 |
+
MEM_OOO_STORES TRUE 1
|
| 288 |
+
MEM_OBEY_STORE_DEP TRUE 1
|
| 289 |
+
PREF_INSERT_LRU FALSE
|
| 290 |
+
PREF_INSERT_MIDDLE FALSE
|
| 291 |
+
PREF_INSERT_LOWQTR FALSE
|
| 292 |
+
PREF_INSERT_DYNACC FALSE
|
| 293 |
+
MEM_REQ_BUFFER_ENTRIES 32 32
|
| 294 |
+
PRIVATE_MSHR_ON TRUE
|
| 295 |
+
MEM_PRIORITY_IFETCH 0 0
|
| 296 |
+
MEM_PRIORITY_DFETCH 0 1
|
| 297 |
+
MEM_PRIORITY_DSTORE 0 2
|
| 298 |
+
MEM_PRIORITY_IPRF 9 3
|
| 299 |
+
MEM_PRIORITY_UOCPRF 9
|
| 300 |
+
MEM_PRIORITY_FDIPPRFON 8
|
| 301 |
+
MEM_PRIORITY_FDIPPRFOFF 9
|
| 302 |
+
MEM_PRIORITY_DPRF 10 4
|
| 303 |
+
MEM_PRIORITY_WB 0 5
|
| 304 |
+
MEM_PRIORITY_WB_NODIRTY 0 5
|
| 305 |
+
PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1
|
| 306 |
+
MEM_REQ_BUFFER_PREF_WATERMARK 0 4
|
| 307 |
+
MEM_REQ_BUFFER_WB_VALVE 2
|
| 308 |
+
MEM_L1_FILL_QUEUE_ENTRIES 32
|
| 309 |
+
MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE
|
| 310 |
+
MEM_MEM_QUEUE_PARTITION_ENABLE FALSE
|
| 311 |
+
MEM_BUS_OUT_QUEUE_AS_FIFO TRUE
|
| 312 |
+
OLDEST_FIRST_TO_MEM_QUEUE TRUE
|
| 313 |
+
ROUND_ROBIN_TO_MEM_QUEUE FALSE
|
| 314 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE FALSE
|
| 315 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0
|
| 316 |
+
L1_CYCLE_TIME 312500
|
| 317 |
+
MLCQ_TO_L1Q_TRANSFER_LATENCY 1
|
| 318 |
+
L1Q_TO_FSB_TRANSFER_LATENCY 1
|
| 319 |
+
PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE
|
| 320 |
+
KICKOUT_PREFETCHES FALSE
|
| 321 |
+
KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE
|
| 322 |
+
KICKOUT_OLDEST_PREFETCH FALSE
|
| 323 |
+
KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE
|
| 324 |
+
ORDER_BEYOND_BUS FALSE 1
|
| 325 |
+
ALL_FIFO_QUEUES FALSE
|
| 326 |
+
QUEUE_MLC_SIZE 0
|
| 327 |
+
QUEUE_L1_SIZE 0
|
| 328 |
+
QUEUE_BUS_OUT_SIZE 0
|
| 329 |
+
QUEUE_CORE_FILL_SIZE 0
|
| 330 |
+
ALLOW_TYPE_MATCHES FALSE
|
| 331 |
+
STREAM_PREFETCH_ON FALSE
|
| 332 |
+
DC_PREF_CACHE_ENABLE FALSE
|
| 333 |
+
DC_PREF_CACHE_CYCLE 0
|
| 334 |
+
PREF_INSERT_DCACHE_IMM TRUE
|
| 335 |
+
DC_PREF_CACHE_SIZE (64 * 1024)
|
| 336 |
+
DC_PREF_CACHE_ASSOC 4
|
| 337 |
+
DC_PREF_ONLY_L1HIT FALSE
|
| 338 |
+
PREF_CACHE_USE_RDY_CYCLE FALSE
|
| 339 |
+
IC_PREF_CACHE_ENABLE FALSE
|
| 340 |
+
IC_PREF_CACHE_SIZE (64 * 1024)
|
| 341 |
+
IC_PREF_CACHE_ASSOC 4
|
| 342 |
+
L1_PREF_CACHE_ENABLE FALSE
|
| 343 |
+
L1_PREF_CACHE_SIZE (1024 * 1024)
|
| 344 |
+
L1_PREF_CACHE_ASSOC 8
|
| 345 |
+
SET_OFF_PATH_CONFIRMED FALSE 1
|
| 346 |
+
USE_CONFIRMED_OFF FALSE
|
| 347 |
+
PREFCACHE_MOVE_OFFPATH FALSE
|
| 348 |
+
CACHE_STAT_ENABLE FALSE
|
| 349 |
+
PREF_DCACHE_HIT_FILL_L1 TRUE
|
| 350 |
+
PREF_ICACHE_HIT_FILL_L1 TRUE
|
| 351 |
+
CRITICAL_ACCESS_PLOT_ENABLE FALSE
|
| 352 |
+
CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat"
|
| 353 |
+
ROUND_ROBIN_TO_L1 FALSE
|
| 354 |
+
PREF_I_TOGETHER FALSE
|
| 355 |
+
ONE_MORE_CACHE_LINE_ENABLE FALSE
|
| 356 |
+
L1_STATIC_PARTITION_ENABLE 0
|
| 357 |
+
L1_STATIC_PARTITION NULL
|
| 358 |
+
L1_DYNAMIC_PARTITION_ENABLE FALSE
|
| 359 |
+
L1_DYNAMIC_PARTITION_POLICY 0
|
| 360 |
+
PARTITION_UMON_DSS_PREF_ENABLE FALSE
|
| 361 |
+
L1_CACHE_HIT_POSITION_COLLECT FALSE
|
| 362 |
+
L1_PART_ON FALSE
|
| 363 |
+
L1_PART_TRIGGER "c:1000000"
|
| 364 |
+
L1_PART_START "t:0"
|
| 365 |
+
L1_PART_WARMUP FALSE
|
| 366 |
+
L1_PART_SHADOW_WARMUP FALSE
|
| 367 |
+
L1_PART_METRIC 0
|
| 368 |
+
L1_PART_SEARCH 0
|
| 369 |
+
L1_PART_USE_STALLING TRUE
|
| 370 |
+
L1_PART_FILL_DELAY 0
|
| 371 |
+
L1_SHADOW_TAGS_MODULO 1
|
| 372 |
+
HIER_MSHR_ON FALSE
|
| 373 |
+
PERF_PRED_ENABLE FALSE
|
| 374 |
+
PERF_PRED_MECH PERF_PRED_CP
|
| 375 |
+
PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY
|
| 376 |
+
PERF_PRED_COUNT_ALL FALSE
|
| 377 |
+
PERF_PRED_COUNT_INST_MISSES TRUE
|
| 378 |
+
PERF_PRED_COUNT_PREFETCHES FALSE
|
| 379 |
+
PERF_PRED_COUNT_OFFPATH_REQS FALSE
|
| 380 |
+
PERF_PRED_COUNT_BW_REQS TRUE
|
| 381 |
+
PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE
|
| 382 |
+
PERF_PRED_SLACK_PERIOD_SIZE 32
|
| 383 |
+
PERF_PRED_REQS_FINISH_AT_FILL FALSE
|
| 384 |
+
PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE
|
| 385 |
+
PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE
|
| 386 |
+
DUMB_MODEL_AVG_REQ_DISTANCE 100
|
| 387 |
+
DUMB_MODEL_RANDOMIZE_DISTANCE FALSE
|
| 388 |
+
DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL
|
| 389 |
+
DUMB_MODEL_AVG_ROW_HITS 1
|
| 390 |
+
DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL
|
| 391 |
+
DUMB_MODEL_MLP 1
|
| 392 |
+
DUMB_MODEL_MLP_PER_CORE NULL
|
| 393 |
+
RAMULATOR_STANDARD "DDR4" DDR4
|
| 394 |
+
RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R
|
| 395 |
+
RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8
|
| 396 |
+
RAMULATOR_CHANNELS 1 1
|
| 397 |
+
RAMULATOR_RANKS 1 1
|
| 398 |
+
RAMULATOR_BANKGROUPS 4 4
|
| 399 |
+
RAMULATOR_BANKS 4 4
|
| 400 |
+
RAMULATOR_CHIP_WIDTH 8 8
|
| 401 |
+
BUS_WIDTH_IN_BYTES 8 8
|
| 402 |
+
RAMULATOR_ROWS 65536 65536
|
| 403 |
+
RAMULATOR_COLS 1024 1024
|
| 404 |
+
RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap
|
| 405 |
+
RAMULATOR_READQ_ENTRIES 32 32
|
| 406 |
+
RAMULATOR_WRITEQ_ENTRIES 32 32
|
| 407 |
+
RAMULATOR_REC_CMD_TRACE "off" FALSE
|
| 408 |
+
RAMULATOR_PRINT_CMD_TRACE "off" FALSE
|
| 409 |
+
RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on"
|
| 410 |
+
RAMULATOR_TCK 833333 833333
|
| 411 |
+
RAMULATOR_TCL 16 16
|
| 412 |
+
RAMULATOR_TCCD 6 6
|
| 413 |
+
RAMULATOR_TCCDS 4 4
|
| 414 |
+
RAMULATOR_TCCDL 6 6
|
| 415 |
+
RAMULATOR_TCWL 12 12
|
| 416 |
+
RAMULATOR_TBL 4 4
|
| 417 |
+
RAMULATOR_TWTR 9 9
|
| 418 |
+
RAMULATOR_TWTRS 3 3
|
| 419 |
+
RAMULATOR_TWTRL 9 9
|
| 420 |
+
RAMULATOR_TRP 16 16
|
| 421 |
+
RAMULATOR_TRPpb 16 16
|
| 422 |
+
RAMULATOR_TRPab 16 16
|
| 423 |
+
RAMULATOR_TRCD 16 16
|
| 424 |
+
RAMULATOR_TRCDR 16 16
|
| 425 |
+
RAMULATOR_TRCDW 16 16
|
| 426 |
+
RAMULATOR_TRAS 39 39
|
| 427 |
+
DRAM_TECH_IN_NM 32 32
|
| 428 |
+
DVFS_ON FALSE
|
| 429 |
+
DVFS_METRIC DVFS_METRIC_NUM_ELEMS
|
| 430 |
+
DVFS_CONFIGS NULL
|
| 431 |
+
DVFS_CONFIG_FILE NULL
|
| 432 |
+
DVFS_START "t:0"
|
| 433 |
+
DVFS_PERIOD "t:312500000000"
|
| 434 |
+
DVFS_LOG TRUE
|
| 435 |
+
DVFS_INDIVIDUAL_CORES FALSE
|
| 436 |
+
DVFS_CHIP_LEVEL FALSE
|
| 437 |
+
DVFS_STATIC NULL
|
| 438 |
+
DVFS_FORCE_CONFIG NULL
|
| 439 |
+
DVFS_REPLAY_CONFIG_TRACE NULL
|
| 440 |
+
DVFS_USE_ORACLE FALSE
|
| 441 |
+
DVFS_USE_BW_SHARING FALSE
|
| 442 |
+
DVFS_USE_DRAM_SHARING FALSE
|
| 443 |
+
DVFS_USE_STALL_TIME FALSE
|
| 444 |
+
DVFS_DRAM_SHARING_SOLVER_BIN NULL
|
| 445 |
+
DVFS_DRAM_SHARING_SOLVER_STRICT TRUE
|
| 446 |
+
DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95
|
| 447 |
+
DVFS_BW_SHARING_MAX_REQS 28.0
|
| 448 |
+
DVFS_BW_SHARING_MAX_RW_COST 0.25
|
| 449 |
+
DVFS_BW_SHARING_NO_PREF_STALL TRUE
|
| 450 |
+
DVFS_BW_SHARING_CRIT_STATS TRUE
|
| 451 |
+
DVFS_COUNT_L1_ACCESS_STALL FALSE
|
| 452 |
+
NUM_CORES 1
|
| 453 |
+
CHIP_CYCLE_TIME 312500 312500
|
| 454 |
+
CORE_0_CYCLE_TIME 312500
|
| 455 |
+
CORE_1_CYCLE_TIME 312500
|
| 456 |
+
CORE_2_CYCLE_TIME 312500
|
| 457 |
+
CORE_3_CYCLE_TIME 312500
|
| 458 |
+
CORE_4_CYCLE_TIME 312500
|
| 459 |
+
CORE_5_CYCLE_TIME 312500
|
| 460 |
+
CORE_6_CYCLE_TIME 312500
|
| 461 |
+
CORE_7_CYCLE_TIME 312500
|
| 462 |
+
CORE_8_CYCLE_TIME 312500
|
| 463 |
+
CORE_9_CYCLE_TIME 312500
|
| 464 |
+
CORE_10_CYCLE_TIME 312500
|
| 465 |
+
CORE_11_CYCLE_TIME 312500
|
| 466 |
+
CORE_12_CYCLE_TIME 312500
|
| 467 |
+
CORE_13_CYCLE_TIME 312500
|
| 468 |
+
CORE_14_CYCLE_TIME 312500
|
| 469 |
+
CORE_15_CYCLE_TIME 312500
|
| 470 |
+
CORE_16_CYCLE_TIME 312500
|
| 471 |
+
CORE_17_CYCLE_TIME 312500
|
| 472 |
+
CORE_18_CYCLE_TIME 312500
|
| 473 |
+
CORE_19_CYCLE_TIME 312500
|
| 474 |
+
CORE_20_CYCLE_TIME 312500
|
| 475 |
+
CORE_21_CYCLE_TIME 312500
|
| 476 |
+
CORE_22_CYCLE_TIME 312500
|
| 477 |
+
CORE_23_CYCLE_TIME 312500
|
| 478 |
+
CORE_24_CYCLE_TIME 312500
|
| 479 |
+
CORE_25_CYCLE_TIME 312500
|
| 480 |
+
CORE_26_CYCLE_TIME 312500
|
| 481 |
+
CORE_27_CYCLE_TIME 312500
|
| 482 |
+
CORE_28_CYCLE_TIME 312500
|
| 483 |
+
CORE_29_CYCLE_TIME 312500
|
| 484 |
+
CORE_30_CYCLE_TIME 312500
|
| 485 |
+
CORE_31_CYCLE_TIME 312500
|
| 486 |
+
CORE_32_CYCLE_TIME 312500
|
| 487 |
+
CORE_33_CYCLE_TIME 312500
|
| 488 |
+
CORE_34_CYCLE_TIME 312500
|
| 489 |
+
CORE_35_CYCLE_TIME 312500
|
| 490 |
+
CORE_36_CYCLE_TIME 312500
|
| 491 |
+
CORE_37_CYCLE_TIME 312500
|
| 492 |
+
CORE_38_CYCLE_TIME 312500
|
| 493 |
+
CORE_39_CYCLE_TIME 312500
|
| 494 |
+
CORE_40_CYCLE_TIME 312500
|
| 495 |
+
CORE_41_CYCLE_TIME 312500
|
| 496 |
+
CORE_42_CYCLE_TIME 312500
|
| 497 |
+
CORE_43_CYCLE_TIME 312500
|
| 498 |
+
CORE_44_CYCLE_TIME 312500
|
| 499 |
+
CORE_45_CYCLE_TIME 312500
|
| 500 |
+
CORE_46_CYCLE_TIME 312500
|
| 501 |
+
CORE_47_CYCLE_TIME 312500
|
| 502 |
+
CORE_48_CYCLE_TIME 312500
|
| 503 |
+
CORE_49_CYCLE_TIME 312500
|
| 504 |
+
CORE_50_CYCLE_TIME 312500
|
| 505 |
+
CORE_51_CYCLE_TIME 312500
|
| 506 |
+
CORE_52_CYCLE_TIME 312500
|
| 507 |
+
CORE_53_CYCLE_TIME 312500
|
| 508 |
+
CORE_54_CYCLE_TIME 312500
|
| 509 |
+
CORE_55_CYCLE_TIME 312500
|
| 510 |
+
CORE_56_CYCLE_TIME 312500
|
| 511 |
+
CORE_57_CYCLE_TIME 312500
|
| 512 |
+
CORE_58_CYCLE_TIME 312500
|
| 513 |
+
CORE_59_CYCLE_TIME 312500
|
| 514 |
+
CORE_60_CYCLE_TIME 312500
|
| 515 |
+
CORE_61_CYCLE_TIME 312500
|
| 516 |
+
CORE_62_CYCLE_TIME 312500
|
| 517 |
+
CORE_63_CYCLE_TIME 312500
|
| 518 |
+
TOPDOWN_FU_EXEC_FEW 0
|
| 519 |
+
ISSUE_WIDTH 4 6
|
| 520 |
+
RS_FILL_WIDTH 8 0
|
| 521 |
+
NODE_TABLE_SIZE 256 512
|
| 522 |
+
NODE_RET_WIDTH 4 8
|
| 523 |
+
NODE_RETIRE_RATE 10
|
| 524 |
+
DECODE_WIDTH 4 6
|
| 525 |
+
IDQ_SIZE 140 144
|
| 526 |
+
REG_RENAMING_SCHEME 0 1
|
| 527 |
+
REG_TABLE_INTEGER_PHYSICAL_SIZE 256 280
|
| 528 |
+
REG_TABLE_VECTOR_PHYSICAL_SIZE 256 332
|
| 529 |
+
REG_TABLE_INTEGER_VIRTUAL_SIZE 256
|
| 530 |
+
REG_TABLE_VECTOR_VIRTUAL_SIZE 256
|
| 531 |
+
REG_RENAMING_MOVE_ELIMINATE FALSE
|
| 532 |
+
NODE_ISSUE_QUEUE_DISPATCH_SCHEME 0
|
| 533 |
+
NODE_ISSUE_QUEUE_SCHEDULE_SCHEME 0
|
| 534 |
+
ISSUE_QUEUE_PARALLEL_PICK FALSE
|
| 535 |
+
RS_SIZES "256" 97 70 19
|
| 536 |
+
RS_CONNECTIONS "xF" b0100110011 b1000001100 b0011000000
|
| 537 |
+
FU_TYPES "0, 0, 0, 0" b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 538 |
+
LSQ_ENABLE TRUE
|
| 539 |
+
LOAD_QUEUE_ENTRY_NUM 128
|
| 540 |
+
STORE_QUEUE_ENTRY_NUM 72
|
| 541 |
+
DECODE_CYCLES 1 5
|
| 542 |
+
MAP_CYCLES 1 5
|
| 543 |
+
ICACHE_LATENCY 3
|
| 544 |
+
EXTRA_REDIRECT_CYCLES 0
|
| 545 |
+
EXTRA_RECOVERY_CYCLES 0
|
| 546 |
+
EXTRA_CALLSYS_CYCLES 20 const
|
| 547 |
+
DIE_ON_CALLSYS FALSE
|
| 548 |
+
DIE_ON_RET_STALL_THRESH 0
|
| 549 |
+
DIE_ON_RET_STALL_CORE 0
|
| 550 |
+
DIE_ON_MEM_BLOCK_THRESH 0
|
| 551 |
+
DIE_ON_MEM_BLOCK_CORE 0
|
| 552 |
+
ICACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 553 |
+
UOP_CACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 554 |
+
FETCH_OFF_PATH_OPS TRUE 1
|
| 555 |
+
WP_COLLECT_STATS TRUE
|
| 556 |
+
OP_INV_DELAY 1
|
| 557 |
+
OP_NOP_DELAY 1
|
| 558 |
+
OP_CF_DELAY 1
|
| 559 |
+
OP_MOV_DELAY 1
|
| 560 |
+
OP_CMOV_DELAY 1
|
| 561 |
+
OP_LDA_DELAY 1
|
| 562 |
+
OP_ILD_DELAY 1
|
| 563 |
+
OP_IST_DELAY 1
|
| 564 |
+
OP_IADD_DELAY 1
|
| 565 |
+
OP_IMUL_DELAY 3
|
| 566 |
+
OP_IDIV_DELAY -20
|
| 567 |
+
OP_ICMP_DELAY 1
|
| 568 |
+
OP_LOGIC_DELAY 1
|
| 569 |
+
OP_SHIFT_DELAY 1
|
| 570 |
+
OP_FLD_DELAY 1
|
| 571 |
+
OP_FST_DELAY 1
|
| 572 |
+
OP_FCVT_DELAY 3
|
| 573 |
+
OP_FADD_DELAY 3
|
| 574 |
+
OP_FMUL_DELAY 5
|
| 575 |
+
OP_FMA_DELAY 5
|
| 576 |
+
OP_FDIV_DELAY -20
|
| 577 |
+
OP_FCMP_DELAY 3
|
| 578 |
+
OP_FCMOV_DELAY 1
|
| 579 |
+
OP_GATHER_DELAY 12
|
| 580 |
+
OP_SCATTER_DELAY 18
|
| 581 |
+
OP_PIPELINED_FAST_DELAY 2
|
| 582 |
+
OP_PIPELINED_MEDIUM_DELAY 5
|
| 583 |
+
OP_PIPELINED_SLOW_DELAY 10
|
| 584 |
+
OP_NOTPIPELINED_MEDIUM_DELAY -5
|
| 585 |
+
OP_NOTPIPELINED_SLOW_DELAY -20
|
| 586 |
+
OP_NOTPIPELINED_VERY_SLOW_DELAY -100
|
| 587 |
+
UNIFORM_OP_DELAY 0
|
| 588 |
+
STALL_ON_WAIT_MEM TRUE
|
| 589 |
+
STORES_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 590 |
+
PREFS_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 591 |
+
OBEY_REG_DEP TRUE
|
| 592 |
+
TRACK_L1_MISS_DEPS FALSE
|
| 593 |
+
CBP_TRACE_R0 NULL /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 594 |
+
CBP_TRACE_R1 NULL
|
| 595 |
+
CBP_TRACE_R2 NULL
|
| 596 |
+
CBP_TRACE_R3 NULL
|
| 597 |
+
CBP_TRACE_R4 NULL
|
| 598 |
+
CBP_TRACE_R5 NULL
|
| 599 |
+
CBP_TRACE_R6 NULL
|
| 600 |
+
CBP_TRACE_R7 NULL
|
| 601 |
+
CBP_TRACE_R8 NULL
|
| 602 |
+
CBP_TRACE_R9 NULL
|
| 603 |
+
CBP_TRACE_R10 NULL
|
| 604 |
+
CBP_TRACE_R11 NULL
|
| 605 |
+
CBP_TRACE_R12 NULL
|
| 606 |
+
CBP_TRACE_R13 NULL
|
| 607 |
+
CBP_TRACE_R14 NULL
|
| 608 |
+
CBP_TRACE_R15 NULL
|
| 609 |
+
CBP_TRACE_R16 NULL
|
| 610 |
+
CBP_TRACE_R17 NULL
|
| 611 |
+
CBP_TRACE_R18 NULL
|
| 612 |
+
CBP_TRACE_R19 NULL
|
| 613 |
+
CBP_TRACE_R20 NULL
|
| 614 |
+
CBP_TRACE_R21 NULL
|
| 615 |
+
CBP_TRACE_R22 NULL
|
| 616 |
+
CBP_TRACE_R23 NULL
|
| 617 |
+
CBP_TRACE_R24 NULL
|
| 618 |
+
CBP_TRACE_R25 NULL
|
| 619 |
+
CBP_TRACE_R26 NULL
|
| 620 |
+
CBP_TRACE_R27 NULL
|
| 621 |
+
CBP_TRACE_R28 NULL
|
| 622 |
+
CBP_TRACE_R29 NULL
|
| 623 |
+
CBP_TRACE_R30 NULL
|
| 624 |
+
CBP_TRACE_R31 NULL
|
| 625 |
+
CBP_TRACE_R32 NULL
|
| 626 |
+
CBP_TRACE_R33 NULL
|
| 627 |
+
CBP_TRACE_R34 NULL
|
| 628 |
+
CBP_TRACE_R35 NULL
|
| 629 |
+
CBP_TRACE_R36 NULL
|
| 630 |
+
CBP_TRACE_R37 NULL
|
| 631 |
+
CBP_TRACE_R38 NULL
|
| 632 |
+
CBP_TRACE_R39 NULL
|
| 633 |
+
CBP_TRACE_R40 NULL
|
| 634 |
+
CBP_TRACE_R41 NULL
|
| 635 |
+
CBP_TRACE_R42 NULL
|
| 636 |
+
CBP_TRACE_R43 NULL
|
| 637 |
+
CBP_TRACE_R44 NULL
|
| 638 |
+
CBP_TRACE_R45 NULL
|
| 639 |
+
CBP_TRACE_R46 NULL
|
| 640 |
+
CBP_TRACE_R47 NULL
|
| 641 |
+
CBP_TRACE_R48 NULL
|
| 642 |
+
CBP_TRACE_R49 NULL
|
| 643 |
+
CBP_TRACE_R50 NULL
|
| 644 |
+
CBP_TRACE_R51 NULL
|
| 645 |
+
CBP_TRACE_R52 NULL
|
| 646 |
+
CBP_TRACE_R53 NULL
|
| 647 |
+
CBP_TRACE_R54 NULL
|
| 648 |
+
CBP_TRACE_R55 NULL
|
| 649 |
+
CBP_TRACE_R56 NULL
|
| 650 |
+
CBP_TRACE_R57 NULL
|
| 651 |
+
CBP_TRACE_R58 NULL
|
| 652 |
+
CBP_TRACE_R59 NULL
|
| 653 |
+
CBP_TRACE_R60 NULL
|
| 654 |
+
CBP_TRACE_R61 NULL
|
| 655 |
+
CBP_TRACE_R62 NULL
|
| 656 |
+
CBP_TRACE_R63 NULL
|
| 657 |
+
FE_FTQ_BLOCK_NUM 32
|
| 658 |
+
FE_FTQ_TAKEN_CFS_PER_CYCLE 2
|
| 659 |
+
FE_FTQ_FT_PER_CYCLE 1
|
| 660 |
+
DUMB_CORE_ON FALSE
|
| 661 |
+
DUMB_CORE 1
|
| 662 |
+
DCACHE_MISS_RATE 10
|
| 663 |
+
L1_MISS_RATE 10
|
| 664 |
+
TRACE_BUF_SIZE 0
|
| 665 |
+
PERFECT_CONFIDENCE FALSE
|
| 666 |
+
CONFIDENCE_ENABLE FALSE
|
| 667 |
+
CONFIDENCE_MECH 0
|
| 668 |
+
CONF_OFF_PATH_THRESHOLD 15
|
| 669 |
+
CONF_OFF_PATH_INC 5
|
| 670 |
+
CONF_BTB_MISS_BP_TAKEN FALSE
|
| 671 |
+
CONF_IPC_RATE_CONF FALSE
|
| 672 |
+
CONF_BTB_MISS_BP_TAKEN_THRESHOLD 0
|
| 673 |
+
CONF_BTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 674 |
+
CONF_IBTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 675 |
+
CONF_MISFETCH_RATE_CYCLES_THRESHOLD 1.0
|
| 676 |
+
CONF_MISPRED_RATE_CYCLES_THRESHOLD 1.0
|
| 677 |
+
CONF_BTB_MISS_SAMPLE_RATE 100000
|
| 678 |
+
CONF_IBTB_MISS_SAMPLE_RATE 100000
|
| 679 |
+
CONF_MISFETCH_SAMPLE_RATE 100000
|
| 680 |
+
CONF_MISPRED_SAMPLE_RATE 100000
|
| 681 |
+
CONF_IPC_SAMPLE_RATE 100000
|
| 682 |
+
CONF_BTB_MISS_RATE_WEIGHT 200
|
| 683 |
+
CONF_BTB_MISS_BP_TAKEN_CONF TRUE
|
| 684 |
+
CONF_IBTB_MISS_BP_TAKEN_CONF TRUE
|
| 685 |
+
CONF_BTB_MISS_RATE_CONF TRUE
|
| 686 |
+
CONF_IBTB_MISS_RATE_CONF TRUE
|
| 687 |
+
CONF_MISFETCH_RATE_CONF TRUE
|
| 688 |
+
CONF_MISPRED_RATE_CONF TRUE
|
| 689 |
+
CONF_INV_BP_CONF TRUE
|
| 690 |
+
CONF_PERFECT_BTB_MISS_CONF FALSE
|
| 691 |
+
CONF_PERFECT_IBTB_MISS_CONF FALSE
|
| 692 |
+
CONF_PERFECT_MISFETCH_CONF FALSE
|
| 693 |
+
CONF_PERFECT_MISPRED_CONF FALSE
|
| 694 |
+
CONF_LOG_DFE_TO_REC FALSE
|
| 695 |
+
CONF_LOG_PHASE_CYCLES FALSE
|
| 696 |
+
NUM_BPS 1
|
| 697 |
+
DFE0_TRIGGER_POLICY 0
|
| 698 |
+
DFE1_TRIGGER_POLICY 1
|
| 699 |
+
DFE2_TRIGGER_POLICY 1
|
| 700 |
+
DFE3_TRIGGER_POLICY 1
|
| 701 |
+
DFE4_TRIGGER_POLICY 1
|
| 702 |
+
DFE0_STOP_POLICY 0
|
| 703 |
+
DFE1_STOP_POLICY 1
|
| 704 |
+
DFE2_STOP_POLICY 1
|
| 705 |
+
DFE3_STOP_POLICY 1
|
| 706 |
+
DFE4_STOP_POLICY 1
|
| 707 |
+
LOOKAHEAD_BUF_SIZE 0
|
| 708 |
+
DEBUG_CYCLE_START 0 0
|
| 709 |
+
DEBUG_CYCLE_STOP 0 -1
|
| 710 |
+
DEBUG_TIME_START 0
|
| 711 |
+
DEBUG_TIME_STOP 0
|
| 712 |
+
DEBUG_INST_START 0 0
|
| 713 |
+
DEBUG_INST_STOP 0 -1
|
| 714 |
+
DEBUG_OP_START 0
|
| 715 |
+
DEBUG_OP_STOP 0
|
| 716 |
+
DEBUG_CACHE_LIB FALSE
|
| 717 |
+
DEBUG_HASH_LIB FALSE
|
| 718 |
+
DEBUG_LIST_LIB FALSE
|
| 719 |
+
DEBUG_PORT_LIB FALSE
|
| 720 |
+
DEBUG_BUS_LIB FALSE
|
| 721 |
+
DEBUG_OP_POOL FALSE
|
| 722 |
+
DEBUG_ORACLE FALSE
|
| 723 |
+
DEBUG_FRONTEND FALSE
|
| 724 |
+
DEBUG_ADDR_TRANS FALSE
|
| 725 |
+
DEBUG_BP FALSE
|
| 726 |
+
DEBUG_BP_DIR FALSE
|
| 727 |
+
DEBUG_BTB FALSE
|
| 728 |
+
DEBUG_CRS FALSE
|
| 729 |
+
DEBUG_MAP FALSE
|
| 730 |
+
DEBUG_MEMORY FALSE
|
| 731 |
+
DEBUG_REPLAY FALSE
|
| 732 |
+
DEBUG_FREQ FALSE
|
| 733 |
+
DEBUG_MODEL FALSE
|
| 734 |
+
DEBUG_THREAD FALSE
|
| 735 |
+
DEBUG_DECOUPLED_FE FALSE
|
| 736 |
+
DEBUG_CONF FALSE
|
| 737 |
+
DEBUG_ICACHE_STAGE FALSE
|
| 738 |
+
DEBUG_DECODE_STAGE FALSE
|
| 739 |
+
DEBUG_CPP_CACHE FALSE
|
| 740 |
+
DEBUG_UOP_CACHE FALSE
|
| 741 |
+
DEBUG_UOP_QUEUE_STAGE FALSE
|
| 742 |
+
DEBUG_IDQ_STAGE FALSE
|
| 743 |
+
DEBUG_MAP_STAGE FALSE
|
| 744 |
+
DEBUG_NODE_STAGE FALSE
|
| 745 |
+
DEBUG_EXEC_STAGE FALSE
|
| 746 |
+
DEBUG_DCACHE_STAGE FALSE
|
| 747 |
+
DEBUG_RETIRED_UOPS FALSE
|
| 748 |
+
DEBUG_EXC_INSERTS FALSE
|
| 749 |
+
DEBUG_BP_CONF FALSE
|
| 750 |
+
DEBUG_ONPATH_CONF FALSE
|
| 751 |
+
DEBUG_STREAM FALSE
|
| 752 |
+
DEBUG_STREAM_MEM FALSE
|
| 753 |
+
DEBUG_WAY FALSE
|
| 754 |
+
DEBUG_L2MARKV FALSE
|
| 755 |
+
DEBUG_L2L1PREF FALSE
|
| 756 |
+
DEBUG_PERF_PRED FALSE
|
| 757 |
+
DEBUG_POWER_UTILS FALSE
|
| 758 |
+
DEBUG_DVFS FALSE
|
| 759 |
+
DEBUG_TRACE_READ FALSE
|
| 760 |
+
DEBUG_INST_FIELDS FALSE
|
| 761 |
+
DEBUG_OP_FIELDS FALSE
|
| 762 |
+
DEBUG_PIN_EXEC_DRIVEN FALSE
|
| 763 |
+
DEBUG_CACHE_PART FALSE
|
| 764 |
+
DEBUG_OPTIMIZER2 FALSE
|
| 765 |
+
DEBUG_PREF FALSE
|
| 766 |
+
DEBUG_FDIP FALSE
|
| 767 |
+
DEBUG_EIP FALSE
|
| 768 |
+
DEBUG_DJOLT FALSE
|
| 769 |
+
DEBUG_FNLMMA FALSE
|
| 770 |
+
PERFECT_BP FALSE
|
| 771 |
+
PERFECT_BTB FALSE
|
| 772 |
+
PERFECT_IBP FALSE
|
| 773 |
+
PERFECT_CRS FALSE
|
| 774 |
+
PERFECT_CBR_BTB FALSE
|
| 775 |
+
PERFECT_NT_BTB FALSE 0 # deprecated, effectively always true.
|
| 776 |
+
CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle
|
| 777 |
+
UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 778 |
+
BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec.
|
| 779 |
+
BP_MECH TAGE64K_BP tage64k
|
| 780 |
+
BP_MECH_L0 BIMODAL_BP
|
| 781 |
+
BP_L0_LATENCY 1
|
| 782 |
+
BP_MAIN_LATENCY 3
|
| 783 |
+
BIMODAL_ENTRIES (4 * 1024)
|
| 784 |
+
HIST_LENGTH 16
|
| 785 |
+
PHT_CTR_BITS 2 const
|
| 786 |
+
BHT_ENTRIES (4 * 1024)
|
| 787 |
+
BHT_ASSOC 4
|
| 788 |
+
HYBRIDS_INDEX_LENGTH 16
|
| 789 |
+
HYBRIDG_HIST_LENGTH 16
|
| 790 |
+
HYBRIDP_HIST_LENGTH 16
|
| 791 |
+
FILTER_INDEX_LENGTH 16
|
| 792 |
+
USE_FILTER FALSE
|
| 793 |
+
INF_HYBRIDGP FALSE
|
| 794 |
+
BP_HASH_TOS FALSE
|
| 795 |
+
IBTB_HASH_TOS FALSE
|
| 796 |
+
BTB_MECH GENERIC_BTB generic
|
| 797 |
+
BTB_ENTRIES 12288 12288
|
| 798 |
+
BTB_ASSOC 4 4
|
| 799 |
+
BTB_NUM_BRSLOT 1
|
| 800 |
+
BTB_BLOCK_SIZE 64
|
| 801 |
+
BTB_OFF_PATH_WRITES TRUE 1
|
| 802 |
+
BTB_MAIN_LATENCY 3 3
|
| 803 |
+
BTB_L0_PRESENT FALSE 1
|
| 804 |
+
BTB_L0_ENTRIES 128 128
|
| 805 |
+
BTB_L0_ASSOC 4 4
|
| 806 |
+
BTB_L0_LATENCY 1 1
|
| 807 |
+
BTB_L1_PRESENT FALSE 1
|
| 808 |
+
BTB_L1_ENTRIES 6144 6144
|
| 809 |
+
BTB_L1_ASSOC 4 4
|
| 810 |
+
BTB_L1_LATENCY 2 2
|
| 811 |
+
ENABLE_CRS TRUE 1
|
| 812 |
+
CRS_ENTRIES 32 128
|
| 813 |
+
CRS_REALISTIC 0 1
|
| 814 |
+
ENABLE_IBP TRUE 1 # Enable the indirect branch predictor
|
| 815 |
+
USE_PAT_HIST TRUE
|
| 816 |
+
IBTB_MECH 1 tc_tagged
|
| 817 |
+
IBTB_HIST_LENGTH 16
|
| 818 |
+
IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb.
|
| 819 |
+
TARGETS_IN_HIST 4
|
| 820 |
+
TC_ENTRIES (4 * 1024) 4096
|
| 821 |
+
TC_ASSOC 4 4
|
| 822 |
+
NUM_CORR_BRANCHES 3
|
| 823 |
+
SEL_HIST_BP_ENTRIES 8192
|
| 824 |
+
SEL_HIST_LENGTH 16
|
| 825 |
+
SEL_HIST_DYN_CNT_TH 16
|
| 826 |
+
SEL_HIST_MISPRED_TH 4
|
| 827 |
+
ENABLE_BP_CONF FALSE
|
| 828 |
+
CONF_MECH 0
|
| 829 |
+
PERF_BP_CONF_PRED FALSE
|
| 830 |
+
BPC_BITS 16
|
| 831 |
+
BPC_MECH 1
|
| 832 |
+
BPC_CTR_RESET TRUE
|
| 833 |
+
BPC_CIT_BITS 8
|
| 834 |
+
BPC_CIT_TH 50
|
| 835 |
+
BPC_CTR_BITS 3
|
| 836 |
+
OPC_COUNT_ZEROS FALSE
|
| 837 |
+
OPC_COUNT_THRESH 10
|
| 838 |
+
INF_LOOP FALSE
|
| 839 |
+
INF_LOOP_BUCKETS 811
|
| 840 |
+
LOOP_ENTRIES (4 * 1024)
|
| 841 |
+
LOOP_ASSOC 4
|
| 842 |
+
LOOP_COUNT_MAX 127
|
| 843 |
+
LOOP_REPEAT_MAX 15
|
| 844 |
+
KNOB_PRINT_BRINFO FALSE
|
| 845 |
+
BR_MISPRED_FILE NULL
|
| 846 |
+
SPEC_LEVEL 3
|
| 847 |
+
RANDOM_DETERMINISTIC TRUE
|
| 848 |
+
TAGESCL64KB_SC TRUE
|
| 849 |
+
TAGESCL64KB_LOOP TRUE
|
| 850 |
+
TAGESCL64KB_ALT TRUE
|
| 851 |
+
CONF_PERCEPTRON_TH 0
|
| 852 |
+
CONF_PERCEPTRON_CTR_BITS 8
|
| 853 |
+
CONF_PERCEPTRON_ENTRIES 127
|
| 854 |
+
CONF_PERCEPTRON_THRESH_OVRD 0
|
| 855 |
+
CONF_HIST_LENGTH 32
|
| 856 |
+
PERCEPTRON_CONF_USE_CONF FALSE
|
| 857 |
+
PERCEPTRON_CONF_TRAIN_HIS FALSE
|
| 858 |
+
PERCEPTRON_CONF_TRAIN_CONF FALSE
|
| 859 |
+
PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE
|
| 860 |
+
PERCEPTRON_TRAIN_MISP_FACTOR 1
|
| 861 |
+
PERCEPTRON_TRAIN_CORR_FACTOR 1
|
| 862 |
+
PERCEPTRON_CONF_HIS_BOTH FALSE
|
| 863 |
+
PERCEPTRON_CONF_HIS_BOTH_LENGTH 4
|
| 864 |
+
MTAGE_REALISTIC_SC_40K FALSE
|
| 865 |
+
MTAGE_REALISTIC_SC_100K FALSE
|
| 866 |
+
H2P_TABLE_BUCKETS 16384
|
| 867 |
+
H2P_MIN_EXEC 5000
|
| 868 |
+
H2P_MIN_MISPRED 333
|
| 869 |
+
H2P_MISPRED_RATIO_PERMIL 10
|
| 870 |
+
H2P_TRACK_CBR TRUE
|
| 871 |
+
H2P_TRACK_REP TRUE
|
| 872 |
+
H2P_TRACK_CALL FALSE
|
| 873 |
+
H2P_TRACK_IBR FALSE
|
| 874 |
+
H2P_TRACK_ICALL FALSE
|
| 875 |
+
H2P_TRACK_RET FALSE
|
| 876 |
+
POWER_INTF_ON FALSE
|
| 877 |
+
POWER_INTF_ENABLE_SCALING FALSE
|
| 878 |
+
POWER_INTF_EXEC "power/power_intf.py"
|
| 879 |
+
POWER_INTF_REF_CHIP_TECH_NM 22
|
| 880 |
+
POWER_INTF_REF_CHIP_FREQ (3.2e9)
|
| 881 |
+
POWER_INTF_REF_MEMORY_FREQ (0.8e9)
|
| 882 |
+
POWER_OTHER (0.0)
|
| 883 |
+
PREF_STREAM_ON FALSE 1
|
| 884 |
+
PREF_STREAM_PER_CORE_ENABLE FALSE
|
| 885 |
+
STREAM_BUFFER_N 16
|
| 886 |
+
STREAM_PREFETCH_N 2 4
|
| 887 |
+
STREAM_START_DIS 5 1
|
| 888 |
+
STREAM_LENGTH 16 64
|
| 889 |
+
STREAM_FULL_N 1
|
| 890 |
+
STREAM_TRAIN_LENGTH 16
|
| 891 |
+
STREAM_TRAIN_NUM 1 4
|
| 892 |
+
PREF_ACC_USE_CACHE FALSE
|
| 893 |
+
STREAM_STALL_ON_QUEUE_FULL FALSE
|
| 894 |
+
PREF_SCHEDULE_NUM 4
|
| 895 |
+
TRAIN_FILTER_SIZE 32
|
| 896 |
+
PREF_REQ_Q_SIZE 64
|
| 897 |
+
STREAM_CREATE_ON_DC_MISS FALSE 0
|
| 898 |
+
STREAM_CREATE_ON_L1_MISS TRUE 1
|
| 899 |
+
STREAM_TRAIN_ON_WRONGPATH TRUE
|
| 900 |
+
STREAM_CREATE_ON_WRONGPATH TRUE
|
| 901 |
+
STREAM_PREF_INTO_DCACHE FALSE
|
| 902 |
+
REMOVE_REDUNDANT_STREAM FALSE
|
| 903 |
+
L2HIT_STREAM_SCHEDULE_NUM 4
|
| 904 |
+
PREF_REQ_QUEUE_FILTER_ON FALSE
|
| 905 |
+
HW_PREF_HIT_TRAIN_STREAM FALSE
|
| 906 |
+
L2HIT_STREAM_BUFFER_N 32
|
| 907 |
+
L2HIT_STREAM_PREFETCH_N 2
|
| 908 |
+
L2HIT_STREAM_START_DIS 2
|
| 909 |
+
L2HIT_STREAM_LENGTH 8
|
| 910 |
+
L2HIT_PREF_REQ_Q_SIZE 128
|
| 911 |
+
L2HIT_L2ACCESS_REQ_Q_SIZE 64
|
| 912 |
+
PREF_STREAM_ACCPERSTREAM FALSE
|
| 913 |
+
PREF_ACC_DISTANCE_10 128
|
| 914 |
+
PREF_FRAMEWORK_ON FALSE 1
|
| 915 |
+
PREF_TRACE_ON FALSE
|
| 916 |
+
PREF_UMLC_ON FALSE
|
| 917 |
+
PREF_UL1_ON TRUE
|
| 918 |
+
PREF_DL0REQ_QUEUE_SIZE 32
|
| 919 |
+
PREF_UMLC_REQ_QUEUE_SIZE 64
|
| 920 |
+
PREF_UL1REQ_QUEUE_SIZE 128
|
| 921 |
+
PREF_SHARED_QUEUES TRUE
|
| 922 |
+
PREF_DL0_MISS_ON TRUE
|
| 923 |
+
PREF_DL0_HIT_ON TRUE
|
| 924 |
+
PREF_DL0REQ_QUEUE_FILTER_ON TRUE
|
| 925 |
+
PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE
|
| 926 |
+
PREF_UL1REQ_QUEUE_FILTER_ON TRUE
|
| 927 |
+
PREF_DL0REQ_ADD_FILTER_ON TRUE
|
| 928 |
+
PREF_UMLC_REQ_ADD_FILTER_ON TRUE
|
| 929 |
+
PREF_UL1REQ_ADD_FILTER_ON TRUE
|
| 930 |
+
PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 931 |
+
PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 932 |
+
PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1
|
| 933 |
+
PREF_DL0SCHEDULE_NUM 4
|
| 934 |
+
PREF_UMLC_SCHEDULE_NUM 4
|
| 935 |
+
PREF_UL1SCHEDULE_NUM 4
|
| 936 |
+
PREF_L1Q_DEMAND_RESERVE 0
|
| 937 |
+
PREF_REPORT_PREF_MATCH_AS_MISS FALSE
|
| 938 |
+
PREF_REPORT_PREF_MATCH_AS_HIT TRUE
|
| 939 |
+
PREF_UPDATE_ON_WRONGPATH TRUE
|
| 940 |
+
PREF_TRAIN_ON_PREF_MISSES FALSE 0
|
| 941 |
+
PREF_ORACLE_TRAIN_ON FALSE 0
|
| 942 |
+
PREF_REQ_DROP FALSE
|
| 943 |
+
PREF_THROTTLE_ON FALSE
|
| 944 |
+
PREF_THROTTLEFB_ON FALSE 1
|
| 945 |
+
PREF_ACC_THRESH_1 0.90 0.75
|
| 946 |
+
PREF_ACC_THRESH_2 0.70 0.4
|
| 947 |
+
PREF_ACC_THRESH_3 0.60 0.4
|
| 948 |
+
PREF_ACC_THRESH_4 0.40
|
| 949 |
+
PREF_UPDATE_INTERVAL 0 8192
|
| 950 |
+
PREF_ANALYZE_LOAD FALSE
|
| 951 |
+
PREF_POL_THRESH_1 0.25
|
| 952 |
+
PREF_POL_THRESH_2 0.10
|
| 953 |
+
PREF_POLBV_ON FALSE
|
| 954 |
+
PREF_POLBV_SIZE 1024
|
| 955 |
+
PREF_TIMELY_THRESH 0.05 0.01
|
| 956 |
+
PREF_POLPF_THRESH 0.01 0.005
|
| 957 |
+
PREF_DEGFB_USEONLYACC FALSE
|
| 958 |
+
PREF_DEGFB_USEONLYPOL FALSE
|
| 959 |
+
PREF_DEGFB_USEONLYLATE FALSE
|
| 960 |
+
PREF_TIMELY_THRESH_2 0.005
|
| 961 |
+
PREF_DEGFB_STATPHASEFILE FALSE
|
| 962 |
+
PREF_MAX_DEGFB 4
|
| 963 |
+
PREF_DHAL FALSE
|
| 964 |
+
PREF_DHAL_SENTTHRESH 16
|
| 965 |
+
PREF_DHAL_USETHRESH_MAX 12
|
| 966 |
+
PREF_DHAL_USETHRESH_MIN2 8
|
| 967 |
+
PREF_DHAL_USETHRESH_MIN1 4
|
| 968 |
+
PREF_DHAL_MAXDEG 64
|
| 969 |
+
PREF_HFILTER_ON FALSE
|
| 970 |
+
PREF_HFILTER_INDEX_BITS 12
|
| 971 |
+
PREF_HFILTER_USE_PC FALSE
|
| 972 |
+
PREF_HFILTER_PRED_USELESS_THRES 2
|
| 973 |
+
PREF_HFILTER_RESET_ENABLE FALSE
|
| 974 |
+
PREF_HFILTER_RESET_INTERVAL 100000
|
| 975 |
+
EIP_ENABLE 0
|
| 976 |
+
L1I_ENTANGLED_TABLE_INDEX_BITS 9
|
| 977 |
+
L1I_ENTANGLED_TABLE_WAYS 16
|
| 978 |
+
DJOLT_ENABLE 0
|
| 979 |
+
FNLMMA_ENABLE 0
|
| 980 |
+
FDIP_ENABLE 1
|
| 981 |
+
FDIP_ALWAYS_PREFETCH FALSE
|
| 982 |
+
PERFECT_FDIP FALSE
|
| 983 |
+
IPRF_MAX_FTQ_ENTRY_CYC 2
|
| 984 |
+
FDIP_BLOOM_FILTER FALSE
|
| 985 |
+
FDIP_BLOOM_ENTRIES 4000
|
| 986 |
+
FDIP_BLOOM2_ENTRIES 1000
|
| 987 |
+
FDIP_BLOOM4_ENTRIES 1000
|
| 988 |
+
FDIP_BLOOM_SIZE 16384
|
| 989 |
+
FDIP_BLOOM_HASHES 6
|
| 990 |
+
FDIP_BLOOM_CLEAR_UNUSEFUL_RATIO 0.95
|
| 991 |
+
FDIP_BLOOM_CLEAR_CYC_PERIOD 10000
|
| 992 |
+
FDIP_UTILITY_HASH_ENABLE 0
|
| 993 |
+
FDIP_UTILITY_PREF_POLICY 0
|
| 994 |
+
FDIP_ADJUSTABLE_FTQ 0
|
| 995 |
+
FDIP_ADJUSTABLE_FTQ_CYC 100000
|
| 996 |
+
UTILITY_RATIO_THRESHOLD 0.58
|
| 997 |
+
TIMELINESS_RATIO_THRESHOLD 0.82
|
| 998 |
+
FDIP_PREF_NO_LATENCY FALSE
|
| 999 |
+
UDP_USEFUL_THRESHOLD 0
|
| 1000 |
+
UDP_WEIGHT_USEFUL 4
|
| 1001 |
+
UDP_WEIGHT_UNUSEFUL 1
|
| 1002 |
+
UDP_WEIGHT_POSITIVE_SATURATION 2147483647
|
| 1003 |
+
FDIP_GHIST_HASHING FALSE
|
| 1004 |
+
FDIP_UTILITY_ONLY_TRAIN_OFF_PATH FALSE
|
| 1005 |
+
FDIP_GHIST_BITS 8
|
| 1006 |
+
UFTQ_MIN_FTQ_BLOCK_NUM 4
|
| 1007 |
+
UFTQ_MAX_FTQ_BLOCK_NUM 64
|
| 1008 |
+
FDIP_SENIORITY_FTQ_HOLD_CYC 30000
|
| 1009 |
+
FDIP_PERFECT_PREFETCH FALSE
|
| 1010 |
+
FDIP_FREEZE_AT_MEM_BUF_LIMIT TRUE
|
| 1011 |
+
FDIP_DUAL_PATH_PREF_IC_ENABLE FALSE
|
| 1012 |
+
FDIP_DUAL_PATH_PREF_UOC_ENABLE FALSE
|
| 1013 |
+
TOP_MISPRED_BR_FILEPATH "br_resteer_coverage.csv"
|
| 1014 |
+
TOP_MISPRED_BR_RESTEER_COVERAGE 0
|
| 1015 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_ENABLE FALSE
|
| 1016 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_MISPRED_THRESHOLD 1
|
| 1017 |
+
FDIP_PRINT_CL_INFO FALSE
|
| 1018 |
+
BRANCH_MISPREDICTION_TABLE_SIZE 0
|
| 1019 |
+
UOC_PREF FALSE
|
| 1020 |
+
UOC_ORACLE_PREF FALSE
|
| 1021 |
+
UOC_ZERO_LATENCY_PREF FALSE
|
| 1022 |
+
L2L1PREF_ON FALSE
|
| 1023 |
+
L2WAY_PREF FALSE
|
| 1024 |
+
L2MARKV_PREF_ON FALSE
|
| 1025 |
+
L2NEXT_PREF_ON FALSE
|
| 1026 |
+
L2HIT_STREAM_PREF_ON FALSE
|
| 1027 |
+
L2L1_DC_HIT_TRAIN FALSE
|
| 1028 |
+
L1_HIT_DUMP_FILE_ON FALSE
|
| 1029 |
+
L1_HIT_DUMP_WO_TXT FALSE
|
| 1030 |
+
L1_HIT_DUMPFILE "l1hit_dump.out"
|
| 1031 |
+
IDEAL_L2_L1_PREFETCHER FALSE
|
| 1032 |
+
IDEAL_L2_ICACHE_PREFETCHER FALSE
|
| 1033 |
+
L1WAY_PREF_SEND_QUEUE 4
|
| 1034 |
+
L1PREF_REQ_QUEUE_SIZE 1024
|
| 1035 |
+
L1PREF_IMMEDIATE FALSE
|
| 1036 |
+
L1WAY_PREF_TIMER_DIS 1000
|
| 1037 |
+
L1MARKV_PREF_SEND_QUEUE 4
|
| 1038 |
+
L1PREF_MARKV_REQ_QUEUE_SIZE 1024
|
| 1039 |
+
MARKV_L2ACCESS_REQ_Q_SIZE 64
|
| 1040 |
+
L1MARKV_PREF_IMMEDIATE FALSE
|
| 1041 |
+
L1MARKV_PREF_TIMER_DIS 1
|
| 1042 |
+
L2L1_HIT_TRAIN TRUE
|
| 1043 |
+
L1MARKV_REQ_TH 1
|
| 1044 |
+
L2L1_IMMEDIATE_PREF_CACHE FALSE
|
| 1045 |
+
L2L1_FILL_PREF_CACHE FALSE
|
| 1046 |
+
L2L1_L2_HIT_STAT FALSE
|
| 1047 |
+
PREF_GHB_ON FALSE
|
| 1048 |
+
DEBUG_PREF_GHB FALSE
|
| 1049 |
+
PREF_GHB_BUFFER_N 1024
|
| 1050 |
+
PREF_GHB_INDEX_N 128
|
| 1051 |
+
PREF_GHB_CZONE_BITS 12
|
| 1052 |
+
PREF_GHB_DEGREE 16
|
| 1053 |
+
PREF_GHB_MAX_DEGREE 32
|
| 1054 |
+
PREF_STRIDE_ON FALSE
|
| 1055 |
+
DEBUG_PREF_STRIDE FALSE
|
| 1056 |
+
PREF_STRIDE_TABLE_N 1024
|
| 1057 |
+
PREF_STRIDE_REGION_BITS 16
|
| 1058 |
+
PREF_STRIDE_DEGREE 4
|
| 1059 |
+
PREF_STRIDE_DISTANCE 16
|
| 1060 |
+
PREF_STRIDE_STARTDISTANCE 1
|
| 1061 |
+
PREF_STRIDE_SINGLE_THRESH 6
|
| 1062 |
+
PREF_STRIDE_MULTI_THRESH 6
|
| 1063 |
+
PREF_STRIDE_SINGLE_STRIDE_MODE FALSE
|
| 1064 |
+
PREF_STRIDEPC_ON FALSE
|
| 1065 |
+
DEBUG_PREF_STRIDEPC FALSE
|
| 1066 |
+
PREF_STRIDEPC_TABLE_N 1024
|
| 1067 |
+
PREF_STRIDEPC_DEGREE 4
|
| 1068 |
+
PREF_STRIDEPC_DISTANCE 16
|
| 1069 |
+
PREF_STRIDEPC_USELOADADDR FALSE
|
| 1070 |
+
PREF_STRIDEPC_TRAINNUM 2
|
| 1071 |
+
PREF_STRIDEPC_STARTDIS 4
|
| 1072 |
+
PREF_PHASE_ON FALSE
|
| 1073 |
+
PREF_PHASE_STUDY FALSE
|
| 1074 |
+
DEBUG_PREF_PHASE FALSE
|
| 1075 |
+
PREF_PHASE_PRIME_HASH 16381
|
| 1076 |
+
PREF_PHASE_INFOSIZE 16384
|
| 1077 |
+
PREF_PHASE_LOG2REGIONSIZE 12
|
| 1078 |
+
PREF_PHASE_REGIONENTRIES 64
|
| 1079 |
+
PREF_PHASE_TRACKEDREGIONS 32
|
| 1080 |
+
PREF_PHASE_INTERVAL 100000
|
| 1081 |
+
PREF_PHASE_TABLE_SIZE 64
|
| 1082 |
+
PREF_PHASE_MAXDIFF_THRESH 64
|
| 1083 |
+
PREF_PHASE_MIN_MISSES 64
|
| 1084 |
+
PREF_PHASE_MISSPER 0.4
|
| 1085 |
+
PREF_2DC_ON FALSE
|
| 1086 |
+
DEBUG_PREF_2DC FALSE
|
| 1087 |
+
PREF_2DC_CACHE_SIZE (1 * 1024)
|
| 1088 |
+
PREF_2DC_CACHE_ASSOC 4
|
| 1089 |
+
PREF_2DC_CACHE_LINE_SIZE 1
|
| 1090 |
+
PREF_2DC_DEGREE 16
|
| 1091 |
+
PREF_2DC_ZONE_SHIFT 10
|
| 1092 |
+
PREF_2DC_TAG_SIZE 16
|
| 1093 |
+
PREF_2DC_NUM_REGIONS 64
|
| 1094 |
+
PREF_2DC_REGION_HASH 61
|
| 1095 |
+
PREF_MARKOV_ON FALSE
|
| 1096 |
+
DEBUG_PREF_MARKOV FALSE
|
| 1097 |
+
PREF_MARKOV_NUM_ENTRIES 65536
|
| 1098 |
+
PREF_MARKOV_NUM_NEXT_STATES 8
|
| 1099 |
+
PREF_MARKOV_SEND_ON_PREF_HIT TRUE
|
| 1100 |
+
PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE
|
| 1101 |
+
PREF_MARKOV_TABLE_UPDATE_POLICY 0
|
| 1102 |
+
PREF_MARKOV_SEND_THRESHOLD 0
|
sssp_facebook/fingerprint/run_1/sim.log
ADDED
|
@@ -0,0 +1,44 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
[0]: ad: 0x7ffff3d9b7c1, op: 427
|
| 2 |
+
[0]: ad: 0x7ffff3d9b7c8, op: 427
|
| 3 |
+
[0]: ad: 0x7ffff3d9b7cc, op: 847
|
| 4 |
+
[0]: ad: 0x7ffff3d9b7cf, op: 330
|
| 5 |
+
new bb detected: 1
|
| 6 |
+
[1]: ad: 0x7ffff3d9b7b0, op: 388
|
| 7 |
+
[1]: ad: 0x7ffff3d9b7b3, op: 8
|
| 8 |
+
[1]: ad: 0x7ffff3d9b7b7, op: 109
|
| 9 |
+
[1]: ad: 0x7ffff3d9b7bb, op: 315
|
| 10 |
+
new bb detected: 2
|
| 11 |
+
Scarab gitrev: 7185dea
|
| 12 |
+
Warning: Scarab expects the trace file type to include OFFLINE_FILE_TYPE_ARCH_REGDEPS (0x20000), but got type: 0xe40
|
| 13 |
+
Scarab started at Fri Jul 17 23:07:24 2026
|
| 14 |
+
|
| 15 |
+
read from initialization: 0x7ffff3d9b7c1
|
| 16 |
+
advanceReader: ROI end reached (ordinal 20000002 > roi_end 20000000)
|
| 17 |
+
Reached end of trace (last_inst) pc=0x7ffff3d9b7c1
|
| 18 |
+
to be appened segment num 1
|
| 19 |
+
10000000
|
| 20 |
+
10000000
|
| 21 |
+
====================================
|
| 22 |
+
TRACE_INST_TAKEN_NOT_CF:0
|
| 23 |
+
TRACE_INST_TAKEN_CF_BR:0
|
| 24 |
+
TRACE_INST_TAKEN_CF_CBR:1250000
|
| 25 |
+
TRACE_INST_TAKEN_CF_REP:0
|
| 26 |
+
TRACE_INST_TAKEN_CF_CALL:0
|
| 27 |
+
TRACE_INST_TAKEN_CF_IBR:0
|
| 28 |
+
TRACE_INST_TAKEN_CF_ICALL:0
|
| 29 |
+
TRACE_INST_TAKEN_CF_ICO:0
|
| 30 |
+
TRACE_INST_TAKEN_CF_RET:0
|
| 31 |
+
TRACE_INST_TAKEN_CF_SYS:0
|
| 32 |
+
====================================
|
| 33 |
+
identity within this segment
|
| 34 |
+
0 / 2
|
| 35 |
+
========================================================
|
| 36 |
+
Number of blocks built : 2
|
| 37 |
+
Average size : 4.00 instructions
|
| 38 |
+
Number of blocks executed : 2500000
|
| 39 |
+
Average weighted size : 4.00 instructions
|
| 40 |
+
Number of total instructions : 10000000
|
| 41 |
+
Number of fetched instruction : 10000000
|
| 42 |
+
========================================================
|
| 43 |
+
Scarab finished at Fri Jul 17 23:07:28 2026
|
| 44 |
+
|
sssp_facebook/fingerprint/run_2/PARAMS.in
ADDED
|
@@ -0,0 +1,268 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
| 1 |
+
# File : PARAMS.golden_cove
|
| 2 |
+
# Date : 02/27/25
|
| 3 |
+
# Description : Golden Cove Configuration
|
| 4 |
+
# Author : Surim Oh <[email protected]>
|
| 5 |
+
#
|
| 6 |
+
# Based on documentation found here:
|
| 7 |
+
# https://en.wikipedia.org/wiki/Golden_Cove
|
| 8 |
+
# https://en.wikichip.org/wiki/intel/microarchitectures/golden_cove
|
| 9 |
+
# https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/3
|
| 10 |
+
|
| 11 |
+
## Simulation Parameters
|
| 12 |
+
--mode full
|
| 13 |
+
--model cmp
|
| 14 |
+
--sim_limit none
|
| 15 |
+
|
| 16 |
+
## Core Parameters
|
| 17 |
+
|
| 18 |
+
# Femptoseconds, 3.2GHz, used for energy estimates.
|
| 19 |
+
--chip_cycle_time 312500
|
| 20 |
+
|
| 21 |
+
|
| 22 |
+
### Fetch Stage
|
| 23 |
+
--fetch_off_path_ops 1
|
| 24 |
+
|
| 25 |
+
#### ICache
|
| 26 |
+
--icache_size 32768
|
| 27 |
+
--icache_assoc 8
|
| 28 |
+
--icache_line_size 64
|
| 29 |
+
|
| 30 |
+
### Uop Cache
|
| 31 |
+
# inclusive w/ L1i
|
| 32 |
+
--uop_cache_enable 1
|
| 33 |
+
--uop_cache_width 8
|
| 34 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 35 |
+
--uop_cache_assoc 8
|
| 36 |
+
--iprf_on_uop_cache_hit 1
|
| 37 |
+
|
| 38 |
+
### Branch Predictor
|
| 39 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 40 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 41 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 42 |
+
--bp_mech tage64k
|
| 43 |
+
|
| 44 |
+
|
| 45 |
+
#### BTB
|
| 46 |
+
|
| 47 |
+
# TODO
|
| 48 |
+
# multi-level BTB
|
| 49 |
+
# 128 entry L0 BTB
|
| 50 |
+
# 6144 entry L1 BTB
|
| 51 |
+
# 12888 entry L2 BTB
|
| 52 |
+
# ~2 entry Return Stack
|
| 53 |
+
# roughly 2x8192 for now
|
| 54 |
+
# BTB model to use.
|
| 55 |
+
--btb_mech generic
|
| 56 |
+
--btb_entries 12288
|
| 57 |
+
--btb_assoc 4
|
| 58 |
+
--btb_main_latency 3
|
| 59 |
+
--btb_l0_present 1
|
| 60 |
+
--btb_l0_entries 128
|
| 61 |
+
--btb_l0_assoc 4
|
| 62 |
+
--btb_l0_latency 1
|
| 63 |
+
--btb_l1_present 1
|
| 64 |
+
--btb_l1_entries 6144
|
| 65 |
+
--btb_l1_assoc 4
|
| 66 |
+
--btb_l1_latency 2
|
| 67 |
+
|
| 68 |
+
# Allow the BTB to be updated by off path ops.
|
| 69 |
+
--btb_off_path_writes 1
|
| 70 |
+
|
| 71 |
+
# NT branches are not inserted in BTB, but do not trigger resteer
|
| 72 |
+
# since we continue without a control flow change
|
| 73 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 74 |
+
|
| 75 |
+
#### CRS
|
| 76 |
+
|
| 77 |
+
# Enable return stack
|
| 78 |
+
--enable_crs 1
|
| 79 |
+
--crs_entries 128
|
| 80 |
+
--crs_realistic 1
|
| 81 |
+
|
| 82 |
+
### iBP
|
| 83 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 84 |
+
--ibtb_mech tc_tagged
|
| 85 |
+
# iBTB Model. tc_tagless, tc_tagged, tc_hybrid.
|
| 86 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 87 |
+
--tc_entries 4096
|
| 88 |
+
--tc_assoc 4
|
| 89 |
+
|
| 90 |
+
### Decode Stage
|
| 91 |
+
--decode_width 6
|
| 92 |
+
--decode_cycles 5
|
| 93 |
+
|
| 94 |
+
### Instruction Decode Queue
|
| 95 |
+
--idq_size 144
|
| 96 |
+
|
| 97 |
+
### Map Stage
|
| 98 |
+
--map_cycles 5
|
| 99 |
+
|
| 100 |
+
# register renaming table
|
| 101 |
+
--reg_renaming_scheme 1
|
| 102 |
+
--reg_table_integer_physical_size 280
|
| 103 |
+
--reg_table_vector_physical_size 332
|
| 104 |
+
|
| 105 |
+
### Issue Stage
|
| 106 |
+
|
| 107 |
+
# Max number of instructions to be renamed, and issued per cycle.
|
| 108 |
+
--issue_width 6
|
| 109 |
+
|
| 110 |
+
--rs_fill_width 0
|
| 111 |
+
# rs_sizes ~205 in total, and they are split into three different reservation stations (RS1, RS2, RS3) where each has 97, 70, 38 entries respectively
|
| 112 |
+
# original architecture
|
| 113 |
+
# RS1 connected to port 0,1,5,6,10
|
| 114 |
+
# RS2 connected to port 2,3,11
|
| 115 |
+
# RS3 connected to port 7,8,4,9
|
| 116 |
+
# scarab does not split ST AGU port and ST port, merge them
|
| 117 |
+
# adjusted architecture to scarab ST AGU (port 4 and 9 removed. rs_size reduced to 186 from 205)
|
| 118 |
+
# RS1 connected to port 0,1,4,5,8
|
| 119 |
+
# RS2 connected to port 2,3,9
|
| 120 |
+
# RS3 connected to port 6,7 (port 4,9 removed, entries reduced to 19 from 38)
|
| 121 |
+
--rs_sizes 97 70 19
|
| 122 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 123 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 124 |
+
|
| 125 |
+
### Exec Stage
|
| 126 |
+
|
| 127 |
+
### DCache
|
| 128 |
+
--dcache_size 49152
|
| 129 |
+
--dcache_read_ports 1
|
| 130 |
+
--dcache_write_ports 1
|
| 131 |
+
--dcache_banks 8
|
| 132 |
+
--dcache_assoc 12
|
| 133 |
+
--dcache_line_size 64
|
| 134 |
+
--dcache_cycles 5
|
| 135 |
+
|
| 136 |
+
### Reorder/Retire Stage
|
| 137 |
+
|
| 138 |
+
# Max number of instructions to be retired per cycle.
|
| 139 |
+
--node_ret_width 8
|
| 140 |
+
--node_table_size 512
|
| 141 |
+
|
| 142 |
+
# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does
|
| 143 |
+
--stores_do_not_block_window 1
|
| 144 |
+
|
| 145 |
+
# TODO: confirm what this knob does
|
| 146 |
+
--prefs_do_not_block_window 1
|
| 147 |
+
|
| 148 |
+
|
| 149 |
+
## Uncore
|
| 150 |
+
|
| 151 |
+
### Mid-level cache
|
| 152 |
+
|
| 153 |
+
# Enable use of a midlevel cache between i/d and L1
|
| 154 |
+
# client 1.25 MiB (1310720 bytes) per core, 8-way, 15 cycles
|
| 155 |
+
# server 2 MiB (2097000 bytes) per core, 8-way, 16 cycles
|
| 156 |
+
--mlc_present 1
|
| 157 |
+
--mlc_size 2097000
|
| 158 |
+
--mlc_assoc 8
|
| 159 |
+
--mlc_cycles 16
|
| 160 |
+
|
| 161 |
+
|
| 162 |
+
### LLC
|
| 163 |
+
# 3 MiB per core, 16-way
|
| 164 |
+
--l1_size 3145728
|
| 165 |
+
--l1_banks 8
|
| 166 |
+
--l1_cycles 36 // just a guess
|
| 167 |
+
--l1_assoc 16
|
| 168 |
+
--l1_line_size 64
|
| 169 |
+
--l1_interleave_factor 64
|
| 170 |
+
|
| 171 |
+
|
| 172 |
+
### prefetcher
|
| 173 |
+
# Kept same as Kaby Lake
|
| 174 |
+
--pref_framework_on 1
|
| 175 |
+
--pref_stream_on 1
|
| 176 |
+
--pref_train_on_pref_misses 0
|
| 177 |
+
--pref_oracle_train 0
|
| 178 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 179 |
+
|
| 180 |
+
--stream_length 64
|
| 181 |
+
--stream_prefetch_n 4
|
| 182 |
+
--stream_start_dis 1
|
| 183 |
+
--stream_train_num 4
|
| 184 |
+
--stream_create_on_dc_miss 0
|
| 185 |
+
--stream_create_on_l1_miss 1
|
| 186 |
+
|
| 187 |
+
--pref_throttlefb_on=1
|
| 188 |
+
--pref_acc_thresh_1=0.75
|
| 189 |
+
--pref_acc_thresh_2=0.4
|
| 190 |
+
--pref_acc_thresh_3=0.4
|
| 191 |
+
--pref_timely_thresh=0.01
|
| 192 |
+
--pref_polpf_thresh=0.005
|
| 193 |
+
--pref_update_interval=8192
|
| 194 |
+
|
| 195 |
+
--mem_req_buffer_pref_watermark 4
|
| 196 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 197 |
+
|
| 198 |
+
### Memory
|
| 199 |
+
# Kept same as Kaby Lake
|
| 200 |
+
--addr_translation random
|
| 201 |
+
|
| 202 |
+
--mem_priority_ifetch 0
|
| 203 |
+
--mem_priority_dfetch 1
|
| 204 |
+
--mem_priority_dstore 2
|
| 205 |
+
--mem_priority_iprf 3
|
| 206 |
+
--mem_priority_dprf 4
|
| 207 |
+
--mem_priority_wb 5
|
| 208 |
+
--mem_priority_wb_nodirty 5
|
| 209 |
+
|
| 210 |
+
--mem_req_buffer_entries 32
|
| 211 |
+
--bus_width_in_bytes 8
|
| 212 |
+
|
| 213 |
+
--ramulator_standard DDR4
|
| 214 |
+
--ramulator_speed DDR4_2400R
|
| 215 |
+
--ramulator_org DDR4_8Gb_x8
|
| 216 |
+
--ramulator_channels 1
|
| 217 |
+
--ramulator_ranks 1
|
| 218 |
+
--ramulator_bankgroups 4
|
| 219 |
+
--ramulator_banks 4
|
| 220 |
+
--ramulator_chip_width 8
|
| 221 |
+
--ramulator_rows 65536
|
| 222 |
+
--ramulator_cols 1024
|
| 223 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 224 |
+
--ramulator_readq_entries 32
|
| 225 |
+
--ramulator_writeq_entries 32
|
| 226 |
+
--ramulator_record_cmd_trace FALSE
|
| 227 |
+
--ramulator_print_cmd_trace FALSE
|
| 228 |
+
--ramulator_tCK 833333
|
| 229 |
+
--ramulator_tCL 16
|
| 230 |
+
--ramulator_tCCD 6
|
| 231 |
+
--ramulator_tCCDS 4
|
| 232 |
+
--ramulator_tCCDL 6
|
| 233 |
+
--ramulator_tCWL 12
|
| 234 |
+
--ramulator_tBL 4
|
| 235 |
+
--ramulator_tWTR 9
|
| 236 |
+
--ramulator_tWTRS 3
|
| 237 |
+
--ramulator_tWTRL 9
|
| 238 |
+
--ramulator_tRP 16
|
| 239 |
+
--ramulator_tRPpb 16
|
| 240 |
+
--ramulator_tRPab 16
|
| 241 |
+
--ramulator_tRCD 16
|
| 242 |
+
--ramulator_tRCDR 16
|
| 243 |
+
--ramulator_tRCDW 16
|
| 244 |
+
--ramulator_tRAS 39
|
| 245 |
+
--dram_tech_in_nm 32
|
| 246 |
+
|
| 247 |
+
## Other
|
| 248 |
+
|
| 249 |
+
|
| 250 |
+
### Debug
|
| 251 |
+
--debug_inst_start 0
|
| 252 |
+
--debug_inst_stop -1
|
| 253 |
+
--debug_cycle_start 0
|
| 254 |
+
--debug_cycle_stop -1
|
| 255 |
+
|
| 256 |
+
|
| 257 |
+
## Stats and Params
|
| 258 |
+
--dump_params 1
|
| 259 |
+
--dump_stats 1
|
| 260 |
+
--dump_trace 0
|
| 261 |
+
|
| 262 |
+
####################################
|
| 263 |
+
--set_off_path_confirmed 1
|
| 264 |
+
|
| 265 |
+
--order_beyond_bus 1
|
| 266 |
+
|
| 267 |
+
--mem_ooo_stores 1
|
| 268 |
+
--mem_obey_store_dep 1
|
sssp_facebook/fingerprint/run_2/PARAMS.out
ADDED
|
@@ -0,0 +1,1102 @@
|
|
|
|
|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
--mode trace_bbv_distributed
|
| 2 |
+
--model cmp
|
| 3 |
+
--frontend memtrace
|
| 4 |
+
--sim_limit none
|
| 5 |
+
--memtrace_roi_begin 20000001
|
| 6 |
+
--memtrace_roi_end 30000000
|
| 7 |
+
--use_fetched_count 1
|
| 8 |
+
--dump_params 1
|
| 9 |
+
--dump_stats 1
|
| 10 |
+
--dump_trace 0
|
| 11 |
+
--trace_bbv_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.2
|
| 12 |
+
--trace_footprint_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.2
|
| 13 |
+
--segment_instr_count 10000000
|
| 14 |
+
--mlc_present 1
|
| 15 |
+
--mlc_size 2097000
|
| 16 |
+
--mlc_assoc 8
|
| 17 |
+
--mlc_cycles 16
|
| 18 |
+
--l1_size 3145728
|
| 19 |
+
--l1_assoc 16
|
| 20 |
+
--l1_line_size 64
|
| 21 |
+
--l1_cycles 36 // just a guess
|
| 22 |
+
--l1_banks 8
|
| 23 |
+
--l1_interleave_factor 64
|
| 24 |
+
--addr_translation random
|
| 25 |
+
--icache_size 32768
|
| 26 |
+
--icache_assoc 8
|
| 27 |
+
--icache_line_size 64
|
| 28 |
+
--uop_cache_enable 1
|
| 29 |
+
--uop_cache_width 8
|
| 30 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 31 |
+
--uop_cache_assoc 8
|
| 32 |
+
--iprf_on_uop_cache_hit 1
|
| 33 |
+
--dcache_size 49152
|
| 34 |
+
--dcache_assoc 12
|
| 35 |
+
--dcache_line_size 64
|
| 36 |
+
--dcache_cycles 5
|
| 37 |
+
--dcache_read_ports 1
|
| 38 |
+
--dcache_write_ports 1
|
| 39 |
+
--dcache_banks 8
|
| 40 |
+
--mem_ooo_stores 1
|
| 41 |
+
--mem_obey_store_dep 1
|
| 42 |
+
--mem_req_buffer_entries 32
|
| 43 |
+
--mem_priority_ifetch 0
|
| 44 |
+
--mem_priority_dfetch 1
|
| 45 |
+
--mem_priority_dstore 2
|
| 46 |
+
--mem_priority_iprf 3
|
| 47 |
+
--mem_priority_dprf 4
|
| 48 |
+
--mem_priority_wb 5
|
| 49 |
+
--mem_priority_wb_nodirty 5
|
| 50 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 51 |
+
--mem_req_buffer_pref_watermark 4
|
| 52 |
+
--order_beyond_bus 1
|
| 53 |
+
--set_off_path_confirmed 1
|
| 54 |
+
--ramulator_standard DDR4
|
| 55 |
+
--ramulator_speed DDR4_2400R
|
| 56 |
+
--ramulator_org DDR4_8Gb_x8
|
| 57 |
+
--ramulator_channels 1
|
| 58 |
+
--ramulator_ranks 1
|
| 59 |
+
--ramulator_bankgroups 4
|
| 60 |
+
--ramulator_banks 4
|
| 61 |
+
--ramulator_chip_width 8
|
| 62 |
+
--bus_width_in_bytes 8
|
| 63 |
+
--ramulator_rows 65536
|
| 64 |
+
--ramulator_cols 1024
|
| 65 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 66 |
+
--ramulator_readq_entries 32
|
| 67 |
+
--ramulator_writeq_entries 32
|
| 68 |
+
--ramulator_record_cmd_trace FALSE
|
| 69 |
+
--ramulator_print_cmd_trace FALSE
|
| 70 |
+
--ramulator_tCK 833333
|
| 71 |
+
--ramulator_tCL 16
|
| 72 |
+
--ramulator_tCCD 6
|
| 73 |
+
--ramulator_tCCDS 4
|
| 74 |
+
--ramulator_tCCDL 6
|
| 75 |
+
--ramulator_tCWL 12
|
| 76 |
+
--ramulator_tBL 4
|
| 77 |
+
--ramulator_tWTR 9
|
| 78 |
+
--ramulator_tWTRS 3
|
| 79 |
+
--ramulator_tWTRL 9
|
| 80 |
+
--ramulator_tRP 16
|
| 81 |
+
--ramulator_tRPpb 16
|
| 82 |
+
--ramulator_tRPab 16
|
| 83 |
+
--ramulator_tRCD 16
|
| 84 |
+
--ramulator_tRCDR 16
|
| 85 |
+
--ramulator_tRCDW 16
|
| 86 |
+
--ramulator_tRAS 39
|
| 87 |
+
--dram_tech_in_nm 32
|
| 88 |
+
--chip_cycle_time 312500
|
| 89 |
+
--issue_width 6
|
| 90 |
+
--rs_fill_width 0
|
| 91 |
+
--node_table_size 512
|
| 92 |
+
--node_ret_width 8
|
| 93 |
+
--decode_width 6
|
| 94 |
+
--idq_size 144
|
| 95 |
+
--reg_renaming_scheme 1
|
| 96 |
+
--reg_table_integer_physical_size 280
|
| 97 |
+
--reg_table_vector_physical_size 332
|
| 98 |
+
--rs_sizes 97 70 19
|
| 99 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 100 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 101 |
+
--decode_cycles 5
|
| 102 |
+
--map_cycles 5
|
| 103 |
+
--fetch_off_path_ops 1
|
| 104 |
+
--stores_do_not_block_window 1
|
| 105 |
+
--prefs_do_not_block_window 1
|
| 106 |
+
--cbp_trace_r0 /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 107 |
+
--debug_cycle_start 0
|
| 108 |
+
--debug_cycle_stop -1
|
| 109 |
+
--debug_inst_start 0
|
| 110 |
+
--debug_inst_stop -1
|
| 111 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 112 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 113 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 114 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 115 |
+
--bp_mech tage64k
|
| 116 |
+
--btb_mech generic
|
| 117 |
+
--btb_entries 12288
|
| 118 |
+
--btb_assoc 4
|
| 119 |
+
--btb_off_path_writes 1
|
| 120 |
+
--btb_main_latency 3
|
| 121 |
+
--btb_l0_present 1
|
| 122 |
+
--btb_l0_entries 128
|
| 123 |
+
--btb_l0_assoc 4
|
| 124 |
+
--btb_l0_latency 1
|
| 125 |
+
--btb_l1_present 1
|
| 126 |
+
--btb_l1_entries 6144
|
| 127 |
+
--btb_l1_assoc 4
|
| 128 |
+
--btb_l1_latency 2
|
| 129 |
+
--enable_crs 1
|
| 130 |
+
--crs_entries 128
|
| 131 |
+
--crs_realistic 1
|
| 132 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 133 |
+
--ibtb_mech tc_tagged
|
| 134 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 135 |
+
--tc_entries 4096
|
| 136 |
+
--tc_assoc 4
|
| 137 |
+
--pref_stream_on 1
|
| 138 |
+
--stream_prefetch_n 4
|
| 139 |
+
--stream_start_dis 1
|
| 140 |
+
--stream_length 64
|
| 141 |
+
--stream_train_num 4
|
| 142 |
+
--stream_create_on_dc_miss 0
|
| 143 |
+
--stream_create_on_l1_miss 1
|
| 144 |
+
--pref_framework_on 1
|
| 145 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 146 |
+
--pref_train_on_pref_misses 0
|
| 147 |
+
--pref_oracle_train_on 0
|
| 148 |
+
--pref_throttlefb_on 1
|
| 149 |
+
--pref_acc_thresh_1 0.75
|
| 150 |
+
--pref_acc_thresh_2 0.4
|
| 151 |
+
--pref_acc_thresh_3 0.4
|
| 152 |
+
--pref_update_interval 8192
|
| 153 |
+
--pref_timely_thresh 0.01
|
| 154 |
+
--pref_polpf_thresh 0.005
|
| 155 |
+
1 1 1 1 1 1 1
|
| 156 |
+
|
| 157 |
+
--- Cut out everything below to use this file as PARAMS.in ---
|
| 158 |
+
|
| 159 |
+
Parameter status at compile time and values supplied on the command line:
|
| 160 |
+
|
| 161 |
+
SIM_MODE 0 trace_bbv_distributed
|
| 162 |
+
SIM_MODEL 0 cmp
|
| 163 |
+
FRONTEND FE_PIN_EXEC_DRIVEN memtrace
|
| 164 |
+
INST_LIMIT NULL
|
| 165 |
+
SIM_LIMIT "none" none
|
| 166 |
+
FORWARD_PROGRESS_LIMIT 100000000
|
| 167 |
+
FORWARD_PROGRESS_INTERVAL 10000
|
| 168 |
+
FAST_FORWARD 0
|
| 169 |
+
FAST_FORWARD_TRACE_INS 0
|
| 170 |
+
FAST_FORWARD_UNTIL_ADDR 0
|
| 171 |
+
MEMTRACE_ROI_BEGIN 0 20000001
|
| 172 |
+
MEMTRACE_ROI_END 0 30000000
|
| 173 |
+
FULL_WARMUP 0
|
| 174 |
+
WARMUP 0
|
| 175 |
+
HEARTBEAT_INTERVAL 1000000
|
| 176 |
+
NUM_HEARTBEATS 0
|
| 177 |
+
USE_FETCHED_COUNT FALSE 1
|
| 178 |
+
PERIODIC_DUMP FALSE
|
| 179 |
+
FILE_TAG ""
|
| 180 |
+
OUTPUT_DIR "."
|
| 181 |
+
STATUS_FILE NULL
|
| 182 |
+
BINDIR NULL
|
| 183 |
+
DUMP_PARAMS TRUE 1
|
| 184 |
+
DUMP_STATS TRUE 1
|
| 185 |
+
DUMP_TRACE FALSE 0
|
| 186 |
+
CLEAR_STATS "never"
|
| 187 |
+
STATS_TO_TRACE NULL
|
| 188 |
+
STAT_TRACE_FILE "stats.trace"
|
| 189 |
+
STAT_TRACE_INTERVAL "i:100000"
|
| 190 |
+
PIPEVIEW FALSE
|
| 191 |
+
PIPEVIEW_FILE "pipeview"
|
| 192 |
+
MEMVIEW FALSE
|
| 193 |
+
MEMVIEW_FILE "memview.out"
|
| 194 |
+
MEMVIEW_START "never"
|
| 195 |
+
INST_HASH_TABLE_SIZE 524288 const
|
| 196 |
+
STDOUT_FILE NULL
|
| 197 |
+
STDERR_FILE NULL
|
| 198 |
+
PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp"
|
| 199 |
+
PRINT_PID FALSE
|
| 200 |
+
USE_UNSURE_FREE_LISTS FALSE
|
| 201 |
+
OPTIMIZER2_MAX_NUM_SLAVES 64
|
| 202 |
+
OPTIMIZER2_PERFECT_MEMORYLESS FALSE
|
| 203 |
+
EXIT_COND 0
|
| 204 |
+
NUM_NOPS 0
|
| 205 |
+
NOPS_BB_START 0x5000000
|
| 206 |
+
IGNORE_BAR_FETCH FALSE
|
| 207 |
+
TRACE_BBV_OUTPUT NULL /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.2
|
| 208 |
+
TRACE_FOOTPRINT_OUTPUT "" /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.2
|
| 209 |
+
SEGMENT_INSTR_COUNT 0 10000000
|
| 210 |
+
ENABLE_SWPRF FALSE
|
| 211 |
+
MLC_PRESENT FALSE 1
|
| 212 |
+
MLC_SIZE (512 * 1024) 2097000
|
| 213 |
+
MLC_ASSOC 4 8
|
| 214 |
+
MLC_LINE_SIZE 64
|
| 215 |
+
MLC_CYCLES 12 16
|
| 216 |
+
PERFECT_MLC FALSE
|
| 217 |
+
MLC_READ_PORTS 1
|
| 218 |
+
MLC_WRITE_PORTS 1
|
| 219 |
+
MLC_BANKS 8
|
| 220 |
+
MLC_INTERLEAVE_FACTOR 64
|
| 221 |
+
MLC_CACHE_REPL_POLICY 0
|
| 222 |
+
MLC_WRITE_THROUGH FALSE
|
| 223 |
+
PREFETCH_UPDATE_LRU_MLC TRUE
|
| 224 |
+
FORCE_L1_MISS FALSE
|
| 225 |
+
L1_SIZE (4 * 1024 * 1024) 3145728
|
| 226 |
+
L1_ASSOC 8 16
|
| 227 |
+
L1_LINE_SIZE 64 64
|
| 228 |
+
L1_CYCLES 24 36 // just a guess
|
| 229 |
+
PERFECT_L1 FALSE
|
| 230 |
+
PRIVATE_L1 FALSE
|
| 231 |
+
L1_READ_PORTS 1
|
| 232 |
+
L1_WRITE_PORTS 1
|
| 233 |
+
L1_BANKS 8 8
|
| 234 |
+
L1_INTERLEAVE_FACTOR 64 64
|
| 235 |
+
L1_CACHE_REPL_POLICY 0
|
| 236 |
+
L1_WRITE_THROUGH FALSE
|
| 237 |
+
L1_IGNORE_WB FALSE
|
| 238 |
+
L1_USE_CORE_FREQ FALSE
|
| 239 |
+
MARK_L1_MISSES TRUE
|
| 240 |
+
PREFETCH_UPDATE_LRU_L1 TRUE
|
| 241 |
+
MEMORY_RANDOM_ADDR FALSE
|
| 242 |
+
VA_PAGE_SIZE_BYTES 4096
|
| 243 |
+
NUM_ADDR_NON_SIGN_EXTEND_BITS 48
|
| 244 |
+
ADDR_TRANSLATION 0 random
|
| 245 |
+
CONSTANT_MEMORY_LATENCY FALSE
|
| 246 |
+
MEMORY_CYCLES 100
|
| 247 |
+
STALL_MEM_REQS_ONLY FALSE
|
| 248 |
+
ICACHE_SIZE (64 * 1024) 32768
|
| 249 |
+
ICACHE_ASSOC 4 8
|
| 250 |
+
ICACHE_LINE_SIZE 64 64
|
| 251 |
+
PERFECT_ICACHE FALSE
|
| 252 |
+
ICACHE_READ_PORTS 1
|
| 253 |
+
ICACHE_WRITE_PORTS 1
|
| 254 |
+
ICACHE_BANKS 8
|
| 255 |
+
ICACHE_REPL 0
|
| 256 |
+
UOP_CACHE_ENABLE 1 1
|
| 257 |
+
UOP_CACHE_WIDTH 6 8
|
| 258 |
+
ALWAYS_LOOKUP_ICACHE 0
|
| 259 |
+
UOP_CACHE_INSERT_ONLY_ONPATH FALSE
|
| 260 |
+
UOP_CACHE_READ_PORTS 1
|
| 261 |
+
UOP_CACHE_LINES 384 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 262 |
+
UOP_CACHE_ASSOC 8 8
|
| 263 |
+
UOP_CACHE_MAX_IMM_DISP_LINE 4
|
| 264 |
+
IPRF_ON_UOP_CACHE_HIT FALSE 1
|
| 265 |
+
UOP_CACHE_REPL 0
|
| 266 |
+
PRIORITY_LINE_STICKINESS_PERCENT 50
|
| 267 |
+
PW_PRIORITY_LIST_FILEPATH "pw_priority_list.csv"
|
| 268 |
+
NUM_PRIORITY_PWS 10
|
| 269 |
+
PRIORITIZE_PWS_AFTER_FIRST_STICKY_UNTIL_BACKEND_STALL FALSE
|
| 270 |
+
NO_REPL_AFTER_QUEUE_SIZE 0
|
| 271 |
+
FDIP_UC_SIZE 0
|
| 272 |
+
FDIP_UC_ASSOC 4
|
| 273 |
+
FDIP_UC_INSERT_REPLPOL 0
|
| 274 |
+
MAP_STAGE_CONSUME_FROM_ICACHE_AND_UOC_SAME_CYCLE TRUE
|
| 275 |
+
UOP_QUEUE_LENGTH 7
|
| 276 |
+
DCACHE_SIZE (64 * 1024) 49152
|
| 277 |
+
DCACHE_ASSOC 1 12
|
| 278 |
+
DCACHE_LINE_SIZE 64 64
|
| 279 |
+
DCACHE_CYCLES 2 5
|
| 280 |
+
PERFECT_DCACHE FALSE
|
| 281 |
+
DCACHE_READ_PORTS 8 1
|
| 282 |
+
DCACHE_WRITE_PORTS 1 1
|
| 283 |
+
DCACHE_BANKS 1 8
|
| 284 |
+
DCACHE_INTERLEAVE_FACTOR 4
|
| 285 |
+
DCACHE_REPL 0
|
| 286 |
+
DCACHE_REPL_PREF_THRESH 1
|
| 287 |
+
MEM_OOO_STORES TRUE 1
|
| 288 |
+
MEM_OBEY_STORE_DEP TRUE 1
|
| 289 |
+
PREF_INSERT_LRU FALSE
|
| 290 |
+
PREF_INSERT_MIDDLE FALSE
|
| 291 |
+
PREF_INSERT_LOWQTR FALSE
|
| 292 |
+
PREF_INSERT_DYNACC FALSE
|
| 293 |
+
MEM_REQ_BUFFER_ENTRIES 32 32
|
| 294 |
+
PRIVATE_MSHR_ON TRUE
|
| 295 |
+
MEM_PRIORITY_IFETCH 0 0
|
| 296 |
+
MEM_PRIORITY_DFETCH 0 1
|
| 297 |
+
MEM_PRIORITY_DSTORE 0 2
|
| 298 |
+
MEM_PRIORITY_IPRF 9 3
|
| 299 |
+
MEM_PRIORITY_UOCPRF 9
|
| 300 |
+
MEM_PRIORITY_FDIPPRFON 8
|
| 301 |
+
MEM_PRIORITY_FDIPPRFOFF 9
|
| 302 |
+
MEM_PRIORITY_DPRF 10 4
|
| 303 |
+
MEM_PRIORITY_WB 0 5
|
| 304 |
+
MEM_PRIORITY_WB_NODIRTY 0 5
|
| 305 |
+
PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1
|
| 306 |
+
MEM_REQ_BUFFER_PREF_WATERMARK 0 4
|
| 307 |
+
MEM_REQ_BUFFER_WB_VALVE 2
|
| 308 |
+
MEM_L1_FILL_QUEUE_ENTRIES 32
|
| 309 |
+
MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE
|
| 310 |
+
MEM_MEM_QUEUE_PARTITION_ENABLE FALSE
|
| 311 |
+
MEM_BUS_OUT_QUEUE_AS_FIFO TRUE
|
| 312 |
+
OLDEST_FIRST_TO_MEM_QUEUE TRUE
|
| 313 |
+
ROUND_ROBIN_TO_MEM_QUEUE FALSE
|
| 314 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE FALSE
|
| 315 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0
|
| 316 |
+
L1_CYCLE_TIME 312500
|
| 317 |
+
MLCQ_TO_L1Q_TRANSFER_LATENCY 1
|
| 318 |
+
L1Q_TO_FSB_TRANSFER_LATENCY 1
|
| 319 |
+
PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE
|
| 320 |
+
KICKOUT_PREFETCHES FALSE
|
| 321 |
+
KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE
|
| 322 |
+
KICKOUT_OLDEST_PREFETCH FALSE
|
| 323 |
+
KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE
|
| 324 |
+
ORDER_BEYOND_BUS FALSE 1
|
| 325 |
+
ALL_FIFO_QUEUES FALSE
|
| 326 |
+
QUEUE_MLC_SIZE 0
|
| 327 |
+
QUEUE_L1_SIZE 0
|
| 328 |
+
QUEUE_BUS_OUT_SIZE 0
|
| 329 |
+
QUEUE_CORE_FILL_SIZE 0
|
| 330 |
+
ALLOW_TYPE_MATCHES FALSE
|
| 331 |
+
STREAM_PREFETCH_ON FALSE
|
| 332 |
+
DC_PREF_CACHE_ENABLE FALSE
|
| 333 |
+
DC_PREF_CACHE_CYCLE 0
|
| 334 |
+
PREF_INSERT_DCACHE_IMM TRUE
|
| 335 |
+
DC_PREF_CACHE_SIZE (64 * 1024)
|
| 336 |
+
DC_PREF_CACHE_ASSOC 4
|
| 337 |
+
DC_PREF_ONLY_L1HIT FALSE
|
| 338 |
+
PREF_CACHE_USE_RDY_CYCLE FALSE
|
| 339 |
+
IC_PREF_CACHE_ENABLE FALSE
|
| 340 |
+
IC_PREF_CACHE_SIZE (64 * 1024)
|
| 341 |
+
IC_PREF_CACHE_ASSOC 4
|
| 342 |
+
L1_PREF_CACHE_ENABLE FALSE
|
| 343 |
+
L1_PREF_CACHE_SIZE (1024 * 1024)
|
| 344 |
+
L1_PREF_CACHE_ASSOC 8
|
| 345 |
+
SET_OFF_PATH_CONFIRMED FALSE 1
|
| 346 |
+
USE_CONFIRMED_OFF FALSE
|
| 347 |
+
PREFCACHE_MOVE_OFFPATH FALSE
|
| 348 |
+
CACHE_STAT_ENABLE FALSE
|
| 349 |
+
PREF_DCACHE_HIT_FILL_L1 TRUE
|
| 350 |
+
PREF_ICACHE_HIT_FILL_L1 TRUE
|
| 351 |
+
CRITICAL_ACCESS_PLOT_ENABLE FALSE
|
| 352 |
+
CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat"
|
| 353 |
+
ROUND_ROBIN_TO_L1 FALSE
|
| 354 |
+
PREF_I_TOGETHER FALSE
|
| 355 |
+
ONE_MORE_CACHE_LINE_ENABLE FALSE
|
| 356 |
+
L1_STATIC_PARTITION_ENABLE 0
|
| 357 |
+
L1_STATIC_PARTITION NULL
|
| 358 |
+
L1_DYNAMIC_PARTITION_ENABLE FALSE
|
| 359 |
+
L1_DYNAMIC_PARTITION_POLICY 0
|
| 360 |
+
PARTITION_UMON_DSS_PREF_ENABLE FALSE
|
| 361 |
+
L1_CACHE_HIT_POSITION_COLLECT FALSE
|
| 362 |
+
L1_PART_ON FALSE
|
| 363 |
+
L1_PART_TRIGGER "c:1000000"
|
| 364 |
+
L1_PART_START "t:0"
|
| 365 |
+
L1_PART_WARMUP FALSE
|
| 366 |
+
L1_PART_SHADOW_WARMUP FALSE
|
| 367 |
+
L1_PART_METRIC 0
|
| 368 |
+
L1_PART_SEARCH 0
|
| 369 |
+
L1_PART_USE_STALLING TRUE
|
| 370 |
+
L1_PART_FILL_DELAY 0
|
| 371 |
+
L1_SHADOW_TAGS_MODULO 1
|
| 372 |
+
HIER_MSHR_ON FALSE
|
| 373 |
+
PERF_PRED_ENABLE FALSE
|
| 374 |
+
PERF_PRED_MECH PERF_PRED_CP
|
| 375 |
+
PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY
|
| 376 |
+
PERF_PRED_COUNT_ALL FALSE
|
| 377 |
+
PERF_PRED_COUNT_INST_MISSES TRUE
|
| 378 |
+
PERF_PRED_COUNT_PREFETCHES FALSE
|
| 379 |
+
PERF_PRED_COUNT_OFFPATH_REQS FALSE
|
| 380 |
+
PERF_PRED_COUNT_BW_REQS TRUE
|
| 381 |
+
PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE
|
| 382 |
+
PERF_PRED_SLACK_PERIOD_SIZE 32
|
| 383 |
+
PERF_PRED_REQS_FINISH_AT_FILL FALSE
|
| 384 |
+
PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE
|
| 385 |
+
PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE
|
| 386 |
+
DUMB_MODEL_AVG_REQ_DISTANCE 100
|
| 387 |
+
DUMB_MODEL_RANDOMIZE_DISTANCE FALSE
|
| 388 |
+
DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL
|
| 389 |
+
DUMB_MODEL_AVG_ROW_HITS 1
|
| 390 |
+
DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL
|
| 391 |
+
DUMB_MODEL_MLP 1
|
| 392 |
+
DUMB_MODEL_MLP_PER_CORE NULL
|
| 393 |
+
RAMULATOR_STANDARD "DDR4" DDR4
|
| 394 |
+
RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R
|
| 395 |
+
RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8
|
| 396 |
+
RAMULATOR_CHANNELS 1 1
|
| 397 |
+
RAMULATOR_RANKS 1 1
|
| 398 |
+
RAMULATOR_BANKGROUPS 4 4
|
| 399 |
+
RAMULATOR_BANKS 4 4
|
| 400 |
+
RAMULATOR_CHIP_WIDTH 8 8
|
| 401 |
+
BUS_WIDTH_IN_BYTES 8 8
|
| 402 |
+
RAMULATOR_ROWS 65536 65536
|
| 403 |
+
RAMULATOR_COLS 1024 1024
|
| 404 |
+
RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap
|
| 405 |
+
RAMULATOR_READQ_ENTRIES 32 32
|
| 406 |
+
RAMULATOR_WRITEQ_ENTRIES 32 32
|
| 407 |
+
RAMULATOR_REC_CMD_TRACE "off" FALSE
|
| 408 |
+
RAMULATOR_PRINT_CMD_TRACE "off" FALSE
|
| 409 |
+
RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on"
|
| 410 |
+
RAMULATOR_TCK 833333 833333
|
| 411 |
+
RAMULATOR_TCL 16 16
|
| 412 |
+
RAMULATOR_TCCD 6 6
|
| 413 |
+
RAMULATOR_TCCDS 4 4
|
| 414 |
+
RAMULATOR_TCCDL 6 6
|
| 415 |
+
RAMULATOR_TCWL 12 12
|
| 416 |
+
RAMULATOR_TBL 4 4
|
| 417 |
+
RAMULATOR_TWTR 9 9
|
| 418 |
+
RAMULATOR_TWTRS 3 3
|
| 419 |
+
RAMULATOR_TWTRL 9 9
|
| 420 |
+
RAMULATOR_TRP 16 16
|
| 421 |
+
RAMULATOR_TRPpb 16 16
|
| 422 |
+
RAMULATOR_TRPab 16 16
|
| 423 |
+
RAMULATOR_TRCD 16 16
|
| 424 |
+
RAMULATOR_TRCDR 16 16
|
| 425 |
+
RAMULATOR_TRCDW 16 16
|
| 426 |
+
RAMULATOR_TRAS 39 39
|
| 427 |
+
DRAM_TECH_IN_NM 32 32
|
| 428 |
+
DVFS_ON FALSE
|
| 429 |
+
DVFS_METRIC DVFS_METRIC_NUM_ELEMS
|
| 430 |
+
DVFS_CONFIGS NULL
|
| 431 |
+
DVFS_CONFIG_FILE NULL
|
| 432 |
+
DVFS_START "t:0"
|
| 433 |
+
DVFS_PERIOD "t:312500000000"
|
| 434 |
+
DVFS_LOG TRUE
|
| 435 |
+
DVFS_INDIVIDUAL_CORES FALSE
|
| 436 |
+
DVFS_CHIP_LEVEL FALSE
|
| 437 |
+
DVFS_STATIC NULL
|
| 438 |
+
DVFS_FORCE_CONFIG NULL
|
| 439 |
+
DVFS_REPLAY_CONFIG_TRACE NULL
|
| 440 |
+
DVFS_USE_ORACLE FALSE
|
| 441 |
+
DVFS_USE_BW_SHARING FALSE
|
| 442 |
+
DVFS_USE_DRAM_SHARING FALSE
|
| 443 |
+
DVFS_USE_STALL_TIME FALSE
|
| 444 |
+
DVFS_DRAM_SHARING_SOLVER_BIN NULL
|
| 445 |
+
DVFS_DRAM_SHARING_SOLVER_STRICT TRUE
|
| 446 |
+
DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95
|
| 447 |
+
DVFS_BW_SHARING_MAX_REQS 28.0
|
| 448 |
+
DVFS_BW_SHARING_MAX_RW_COST 0.25
|
| 449 |
+
DVFS_BW_SHARING_NO_PREF_STALL TRUE
|
| 450 |
+
DVFS_BW_SHARING_CRIT_STATS TRUE
|
| 451 |
+
DVFS_COUNT_L1_ACCESS_STALL FALSE
|
| 452 |
+
NUM_CORES 1
|
| 453 |
+
CHIP_CYCLE_TIME 312500 312500
|
| 454 |
+
CORE_0_CYCLE_TIME 312500
|
| 455 |
+
CORE_1_CYCLE_TIME 312500
|
| 456 |
+
CORE_2_CYCLE_TIME 312500
|
| 457 |
+
CORE_3_CYCLE_TIME 312500
|
| 458 |
+
CORE_4_CYCLE_TIME 312500
|
| 459 |
+
CORE_5_CYCLE_TIME 312500
|
| 460 |
+
CORE_6_CYCLE_TIME 312500
|
| 461 |
+
CORE_7_CYCLE_TIME 312500
|
| 462 |
+
CORE_8_CYCLE_TIME 312500
|
| 463 |
+
CORE_9_CYCLE_TIME 312500
|
| 464 |
+
CORE_10_CYCLE_TIME 312500
|
| 465 |
+
CORE_11_CYCLE_TIME 312500
|
| 466 |
+
CORE_12_CYCLE_TIME 312500
|
| 467 |
+
CORE_13_CYCLE_TIME 312500
|
| 468 |
+
CORE_14_CYCLE_TIME 312500
|
| 469 |
+
CORE_15_CYCLE_TIME 312500
|
| 470 |
+
CORE_16_CYCLE_TIME 312500
|
| 471 |
+
CORE_17_CYCLE_TIME 312500
|
| 472 |
+
CORE_18_CYCLE_TIME 312500
|
| 473 |
+
CORE_19_CYCLE_TIME 312500
|
| 474 |
+
CORE_20_CYCLE_TIME 312500
|
| 475 |
+
CORE_21_CYCLE_TIME 312500
|
| 476 |
+
CORE_22_CYCLE_TIME 312500
|
| 477 |
+
CORE_23_CYCLE_TIME 312500
|
| 478 |
+
CORE_24_CYCLE_TIME 312500
|
| 479 |
+
CORE_25_CYCLE_TIME 312500
|
| 480 |
+
CORE_26_CYCLE_TIME 312500
|
| 481 |
+
CORE_27_CYCLE_TIME 312500
|
| 482 |
+
CORE_28_CYCLE_TIME 312500
|
| 483 |
+
CORE_29_CYCLE_TIME 312500
|
| 484 |
+
CORE_30_CYCLE_TIME 312500
|
| 485 |
+
CORE_31_CYCLE_TIME 312500
|
| 486 |
+
CORE_32_CYCLE_TIME 312500
|
| 487 |
+
CORE_33_CYCLE_TIME 312500
|
| 488 |
+
CORE_34_CYCLE_TIME 312500
|
| 489 |
+
CORE_35_CYCLE_TIME 312500
|
| 490 |
+
CORE_36_CYCLE_TIME 312500
|
| 491 |
+
CORE_37_CYCLE_TIME 312500
|
| 492 |
+
CORE_38_CYCLE_TIME 312500
|
| 493 |
+
CORE_39_CYCLE_TIME 312500
|
| 494 |
+
CORE_40_CYCLE_TIME 312500
|
| 495 |
+
CORE_41_CYCLE_TIME 312500
|
| 496 |
+
CORE_42_CYCLE_TIME 312500
|
| 497 |
+
CORE_43_CYCLE_TIME 312500
|
| 498 |
+
CORE_44_CYCLE_TIME 312500
|
| 499 |
+
CORE_45_CYCLE_TIME 312500
|
| 500 |
+
CORE_46_CYCLE_TIME 312500
|
| 501 |
+
CORE_47_CYCLE_TIME 312500
|
| 502 |
+
CORE_48_CYCLE_TIME 312500
|
| 503 |
+
CORE_49_CYCLE_TIME 312500
|
| 504 |
+
CORE_50_CYCLE_TIME 312500
|
| 505 |
+
CORE_51_CYCLE_TIME 312500
|
| 506 |
+
CORE_52_CYCLE_TIME 312500
|
| 507 |
+
CORE_53_CYCLE_TIME 312500
|
| 508 |
+
CORE_54_CYCLE_TIME 312500
|
| 509 |
+
CORE_55_CYCLE_TIME 312500
|
| 510 |
+
CORE_56_CYCLE_TIME 312500
|
| 511 |
+
CORE_57_CYCLE_TIME 312500
|
| 512 |
+
CORE_58_CYCLE_TIME 312500
|
| 513 |
+
CORE_59_CYCLE_TIME 312500
|
| 514 |
+
CORE_60_CYCLE_TIME 312500
|
| 515 |
+
CORE_61_CYCLE_TIME 312500
|
| 516 |
+
CORE_62_CYCLE_TIME 312500
|
| 517 |
+
CORE_63_CYCLE_TIME 312500
|
| 518 |
+
TOPDOWN_FU_EXEC_FEW 0
|
| 519 |
+
ISSUE_WIDTH 4 6
|
| 520 |
+
RS_FILL_WIDTH 8 0
|
| 521 |
+
NODE_TABLE_SIZE 256 512
|
| 522 |
+
NODE_RET_WIDTH 4 8
|
| 523 |
+
NODE_RETIRE_RATE 10
|
| 524 |
+
DECODE_WIDTH 4 6
|
| 525 |
+
IDQ_SIZE 140 144
|
| 526 |
+
REG_RENAMING_SCHEME 0 1
|
| 527 |
+
REG_TABLE_INTEGER_PHYSICAL_SIZE 256 280
|
| 528 |
+
REG_TABLE_VECTOR_PHYSICAL_SIZE 256 332
|
| 529 |
+
REG_TABLE_INTEGER_VIRTUAL_SIZE 256
|
| 530 |
+
REG_TABLE_VECTOR_VIRTUAL_SIZE 256
|
| 531 |
+
REG_RENAMING_MOVE_ELIMINATE FALSE
|
| 532 |
+
NODE_ISSUE_QUEUE_DISPATCH_SCHEME 0
|
| 533 |
+
NODE_ISSUE_QUEUE_SCHEDULE_SCHEME 0
|
| 534 |
+
ISSUE_QUEUE_PARALLEL_PICK FALSE
|
| 535 |
+
RS_SIZES "256" 97 70 19
|
| 536 |
+
RS_CONNECTIONS "xF" b0100110011 b1000001100 b0011000000
|
| 537 |
+
FU_TYPES "0, 0, 0, 0" b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 538 |
+
LSQ_ENABLE TRUE
|
| 539 |
+
LOAD_QUEUE_ENTRY_NUM 128
|
| 540 |
+
STORE_QUEUE_ENTRY_NUM 72
|
| 541 |
+
DECODE_CYCLES 1 5
|
| 542 |
+
MAP_CYCLES 1 5
|
| 543 |
+
ICACHE_LATENCY 3
|
| 544 |
+
EXTRA_REDIRECT_CYCLES 0
|
| 545 |
+
EXTRA_RECOVERY_CYCLES 0
|
| 546 |
+
EXTRA_CALLSYS_CYCLES 20 const
|
| 547 |
+
DIE_ON_CALLSYS FALSE
|
| 548 |
+
DIE_ON_RET_STALL_THRESH 0
|
| 549 |
+
DIE_ON_RET_STALL_CORE 0
|
| 550 |
+
DIE_ON_MEM_BLOCK_THRESH 0
|
| 551 |
+
DIE_ON_MEM_BLOCK_CORE 0
|
| 552 |
+
ICACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 553 |
+
UOP_CACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 554 |
+
FETCH_OFF_PATH_OPS TRUE 1
|
| 555 |
+
WP_COLLECT_STATS TRUE
|
| 556 |
+
OP_INV_DELAY 1
|
| 557 |
+
OP_NOP_DELAY 1
|
| 558 |
+
OP_CF_DELAY 1
|
| 559 |
+
OP_MOV_DELAY 1
|
| 560 |
+
OP_CMOV_DELAY 1
|
| 561 |
+
OP_LDA_DELAY 1
|
| 562 |
+
OP_ILD_DELAY 1
|
| 563 |
+
OP_IST_DELAY 1
|
| 564 |
+
OP_IADD_DELAY 1
|
| 565 |
+
OP_IMUL_DELAY 3
|
| 566 |
+
OP_IDIV_DELAY -20
|
| 567 |
+
OP_ICMP_DELAY 1
|
| 568 |
+
OP_LOGIC_DELAY 1
|
| 569 |
+
OP_SHIFT_DELAY 1
|
| 570 |
+
OP_FLD_DELAY 1
|
| 571 |
+
OP_FST_DELAY 1
|
| 572 |
+
OP_FCVT_DELAY 3
|
| 573 |
+
OP_FADD_DELAY 3
|
| 574 |
+
OP_FMUL_DELAY 5
|
| 575 |
+
OP_FMA_DELAY 5
|
| 576 |
+
OP_FDIV_DELAY -20
|
| 577 |
+
OP_FCMP_DELAY 3
|
| 578 |
+
OP_FCMOV_DELAY 1
|
| 579 |
+
OP_GATHER_DELAY 12
|
| 580 |
+
OP_SCATTER_DELAY 18
|
| 581 |
+
OP_PIPELINED_FAST_DELAY 2
|
| 582 |
+
OP_PIPELINED_MEDIUM_DELAY 5
|
| 583 |
+
OP_PIPELINED_SLOW_DELAY 10
|
| 584 |
+
OP_NOTPIPELINED_MEDIUM_DELAY -5
|
| 585 |
+
OP_NOTPIPELINED_SLOW_DELAY -20
|
| 586 |
+
OP_NOTPIPELINED_VERY_SLOW_DELAY -100
|
| 587 |
+
UNIFORM_OP_DELAY 0
|
| 588 |
+
STALL_ON_WAIT_MEM TRUE
|
| 589 |
+
STORES_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 590 |
+
PREFS_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 591 |
+
OBEY_REG_DEP TRUE
|
| 592 |
+
TRACK_L1_MISS_DEPS FALSE
|
| 593 |
+
CBP_TRACE_R0 NULL /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 594 |
+
CBP_TRACE_R1 NULL
|
| 595 |
+
CBP_TRACE_R2 NULL
|
| 596 |
+
CBP_TRACE_R3 NULL
|
| 597 |
+
CBP_TRACE_R4 NULL
|
| 598 |
+
CBP_TRACE_R5 NULL
|
| 599 |
+
CBP_TRACE_R6 NULL
|
| 600 |
+
CBP_TRACE_R7 NULL
|
| 601 |
+
CBP_TRACE_R8 NULL
|
| 602 |
+
CBP_TRACE_R9 NULL
|
| 603 |
+
CBP_TRACE_R10 NULL
|
| 604 |
+
CBP_TRACE_R11 NULL
|
| 605 |
+
CBP_TRACE_R12 NULL
|
| 606 |
+
CBP_TRACE_R13 NULL
|
| 607 |
+
CBP_TRACE_R14 NULL
|
| 608 |
+
CBP_TRACE_R15 NULL
|
| 609 |
+
CBP_TRACE_R16 NULL
|
| 610 |
+
CBP_TRACE_R17 NULL
|
| 611 |
+
CBP_TRACE_R18 NULL
|
| 612 |
+
CBP_TRACE_R19 NULL
|
| 613 |
+
CBP_TRACE_R20 NULL
|
| 614 |
+
CBP_TRACE_R21 NULL
|
| 615 |
+
CBP_TRACE_R22 NULL
|
| 616 |
+
CBP_TRACE_R23 NULL
|
| 617 |
+
CBP_TRACE_R24 NULL
|
| 618 |
+
CBP_TRACE_R25 NULL
|
| 619 |
+
CBP_TRACE_R26 NULL
|
| 620 |
+
CBP_TRACE_R27 NULL
|
| 621 |
+
CBP_TRACE_R28 NULL
|
| 622 |
+
CBP_TRACE_R29 NULL
|
| 623 |
+
CBP_TRACE_R30 NULL
|
| 624 |
+
CBP_TRACE_R31 NULL
|
| 625 |
+
CBP_TRACE_R32 NULL
|
| 626 |
+
CBP_TRACE_R33 NULL
|
| 627 |
+
CBP_TRACE_R34 NULL
|
| 628 |
+
CBP_TRACE_R35 NULL
|
| 629 |
+
CBP_TRACE_R36 NULL
|
| 630 |
+
CBP_TRACE_R37 NULL
|
| 631 |
+
CBP_TRACE_R38 NULL
|
| 632 |
+
CBP_TRACE_R39 NULL
|
| 633 |
+
CBP_TRACE_R40 NULL
|
| 634 |
+
CBP_TRACE_R41 NULL
|
| 635 |
+
CBP_TRACE_R42 NULL
|
| 636 |
+
CBP_TRACE_R43 NULL
|
| 637 |
+
CBP_TRACE_R44 NULL
|
| 638 |
+
CBP_TRACE_R45 NULL
|
| 639 |
+
CBP_TRACE_R46 NULL
|
| 640 |
+
CBP_TRACE_R47 NULL
|
| 641 |
+
CBP_TRACE_R48 NULL
|
| 642 |
+
CBP_TRACE_R49 NULL
|
| 643 |
+
CBP_TRACE_R50 NULL
|
| 644 |
+
CBP_TRACE_R51 NULL
|
| 645 |
+
CBP_TRACE_R52 NULL
|
| 646 |
+
CBP_TRACE_R53 NULL
|
| 647 |
+
CBP_TRACE_R54 NULL
|
| 648 |
+
CBP_TRACE_R55 NULL
|
| 649 |
+
CBP_TRACE_R56 NULL
|
| 650 |
+
CBP_TRACE_R57 NULL
|
| 651 |
+
CBP_TRACE_R58 NULL
|
| 652 |
+
CBP_TRACE_R59 NULL
|
| 653 |
+
CBP_TRACE_R60 NULL
|
| 654 |
+
CBP_TRACE_R61 NULL
|
| 655 |
+
CBP_TRACE_R62 NULL
|
| 656 |
+
CBP_TRACE_R63 NULL
|
| 657 |
+
FE_FTQ_BLOCK_NUM 32
|
| 658 |
+
FE_FTQ_TAKEN_CFS_PER_CYCLE 2
|
| 659 |
+
FE_FTQ_FT_PER_CYCLE 1
|
| 660 |
+
DUMB_CORE_ON FALSE
|
| 661 |
+
DUMB_CORE 1
|
| 662 |
+
DCACHE_MISS_RATE 10
|
| 663 |
+
L1_MISS_RATE 10
|
| 664 |
+
TRACE_BUF_SIZE 0
|
| 665 |
+
PERFECT_CONFIDENCE FALSE
|
| 666 |
+
CONFIDENCE_ENABLE FALSE
|
| 667 |
+
CONFIDENCE_MECH 0
|
| 668 |
+
CONF_OFF_PATH_THRESHOLD 15
|
| 669 |
+
CONF_OFF_PATH_INC 5
|
| 670 |
+
CONF_BTB_MISS_BP_TAKEN FALSE
|
| 671 |
+
CONF_IPC_RATE_CONF FALSE
|
| 672 |
+
CONF_BTB_MISS_BP_TAKEN_THRESHOLD 0
|
| 673 |
+
CONF_BTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 674 |
+
CONF_IBTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 675 |
+
CONF_MISFETCH_RATE_CYCLES_THRESHOLD 1.0
|
| 676 |
+
CONF_MISPRED_RATE_CYCLES_THRESHOLD 1.0
|
| 677 |
+
CONF_BTB_MISS_SAMPLE_RATE 100000
|
| 678 |
+
CONF_IBTB_MISS_SAMPLE_RATE 100000
|
| 679 |
+
CONF_MISFETCH_SAMPLE_RATE 100000
|
| 680 |
+
CONF_MISPRED_SAMPLE_RATE 100000
|
| 681 |
+
CONF_IPC_SAMPLE_RATE 100000
|
| 682 |
+
CONF_BTB_MISS_RATE_WEIGHT 200
|
| 683 |
+
CONF_BTB_MISS_BP_TAKEN_CONF TRUE
|
| 684 |
+
CONF_IBTB_MISS_BP_TAKEN_CONF TRUE
|
| 685 |
+
CONF_BTB_MISS_RATE_CONF TRUE
|
| 686 |
+
CONF_IBTB_MISS_RATE_CONF TRUE
|
| 687 |
+
CONF_MISFETCH_RATE_CONF TRUE
|
| 688 |
+
CONF_MISPRED_RATE_CONF TRUE
|
| 689 |
+
CONF_INV_BP_CONF TRUE
|
| 690 |
+
CONF_PERFECT_BTB_MISS_CONF FALSE
|
| 691 |
+
CONF_PERFECT_IBTB_MISS_CONF FALSE
|
| 692 |
+
CONF_PERFECT_MISFETCH_CONF FALSE
|
| 693 |
+
CONF_PERFECT_MISPRED_CONF FALSE
|
| 694 |
+
CONF_LOG_DFE_TO_REC FALSE
|
| 695 |
+
CONF_LOG_PHASE_CYCLES FALSE
|
| 696 |
+
NUM_BPS 1
|
| 697 |
+
DFE0_TRIGGER_POLICY 0
|
| 698 |
+
DFE1_TRIGGER_POLICY 1
|
| 699 |
+
DFE2_TRIGGER_POLICY 1
|
| 700 |
+
DFE3_TRIGGER_POLICY 1
|
| 701 |
+
DFE4_TRIGGER_POLICY 1
|
| 702 |
+
DFE0_STOP_POLICY 0
|
| 703 |
+
DFE1_STOP_POLICY 1
|
| 704 |
+
DFE2_STOP_POLICY 1
|
| 705 |
+
DFE3_STOP_POLICY 1
|
| 706 |
+
DFE4_STOP_POLICY 1
|
| 707 |
+
LOOKAHEAD_BUF_SIZE 0
|
| 708 |
+
DEBUG_CYCLE_START 0 0
|
| 709 |
+
DEBUG_CYCLE_STOP 0 -1
|
| 710 |
+
DEBUG_TIME_START 0
|
| 711 |
+
DEBUG_TIME_STOP 0
|
| 712 |
+
DEBUG_INST_START 0 0
|
| 713 |
+
DEBUG_INST_STOP 0 -1
|
| 714 |
+
DEBUG_OP_START 0
|
| 715 |
+
DEBUG_OP_STOP 0
|
| 716 |
+
DEBUG_CACHE_LIB FALSE
|
| 717 |
+
DEBUG_HASH_LIB FALSE
|
| 718 |
+
DEBUG_LIST_LIB FALSE
|
| 719 |
+
DEBUG_PORT_LIB FALSE
|
| 720 |
+
DEBUG_BUS_LIB FALSE
|
| 721 |
+
DEBUG_OP_POOL FALSE
|
| 722 |
+
DEBUG_ORACLE FALSE
|
| 723 |
+
DEBUG_FRONTEND FALSE
|
| 724 |
+
DEBUG_ADDR_TRANS FALSE
|
| 725 |
+
DEBUG_BP FALSE
|
| 726 |
+
DEBUG_BP_DIR FALSE
|
| 727 |
+
DEBUG_BTB FALSE
|
| 728 |
+
DEBUG_CRS FALSE
|
| 729 |
+
DEBUG_MAP FALSE
|
| 730 |
+
DEBUG_MEMORY FALSE
|
| 731 |
+
DEBUG_REPLAY FALSE
|
| 732 |
+
DEBUG_FREQ FALSE
|
| 733 |
+
DEBUG_MODEL FALSE
|
| 734 |
+
DEBUG_THREAD FALSE
|
| 735 |
+
DEBUG_DECOUPLED_FE FALSE
|
| 736 |
+
DEBUG_CONF FALSE
|
| 737 |
+
DEBUG_ICACHE_STAGE FALSE
|
| 738 |
+
DEBUG_DECODE_STAGE FALSE
|
| 739 |
+
DEBUG_CPP_CACHE FALSE
|
| 740 |
+
DEBUG_UOP_CACHE FALSE
|
| 741 |
+
DEBUG_UOP_QUEUE_STAGE FALSE
|
| 742 |
+
DEBUG_IDQ_STAGE FALSE
|
| 743 |
+
DEBUG_MAP_STAGE FALSE
|
| 744 |
+
DEBUG_NODE_STAGE FALSE
|
| 745 |
+
DEBUG_EXEC_STAGE FALSE
|
| 746 |
+
DEBUG_DCACHE_STAGE FALSE
|
| 747 |
+
DEBUG_RETIRED_UOPS FALSE
|
| 748 |
+
DEBUG_EXC_INSERTS FALSE
|
| 749 |
+
DEBUG_BP_CONF FALSE
|
| 750 |
+
DEBUG_ONPATH_CONF FALSE
|
| 751 |
+
DEBUG_STREAM FALSE
|
| 752 |
+
DEBUG_STREAM_MEM FALSE
|
| 753 |
+
DEBUG_WAY FALSE
|
| 754 |
+
DEBUG_L2MARKV FALSE
|
| 755 |
+
DEBUG_L2L1PREF FALSE
|
| 756 |
+
DEBUG_PERF_PRED FALSE
|
| 757 |
+
DEBUG_POWER_UTILS FALSE
|
| 758 |
+
DEBUG_DVFS FALSE
|
| 759 |
+
DEBUG_TRACE_READ FALSE
|
| 760 |
+
DEBUG_INST_FIELDS FALSE
|
| 761 |
+
DEBUG_OP_FIELDS FALSE
|
| 762 |
+
DEBUG_PIN_EXEC_DRIVEN FALSE
|
| 763 |
+
DEBUG_CACHE_PART FALSE
|
| 764 |
+
DEBUG_OPTIMIZER2 FALSE
|
| 765 |
+
DEBUG_PREF FALSE
|
| 766 |
+
DEBUG_FDIP FALSE
|
| 767 |
+
DEBUG_EIP FALSE
|
| 768 |
+
DEBUG_DJOLT FALSE
|
| 769 |
+
DEBUG_FNLMMA FALSE
|
| 770 |
+
PERFECT_BP FALSE
|
| 771 |
+
PERFECT_BTB FALSE
|
| 772 |
+
PERFECT_IBP FALSE
|
| 773 |
+
PERFECT_CRS FALSE
|
| 774 |
+
PERFECT_CBR_BTB FALSE
|
| 775 |
+
PERFECT_NT_BTB FALSE 0 # deprecated, effectively always true.
|
| 776 |
+
CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle
|
| 777 |
+
UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 778 |
+
BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec.
|
| 779 |
+
BP_MECH TAGE64K_BP tage64k
|
| 780 |
+
BP_MECH_L0 BIMODAL_BP
|
| 781 |
+
BP_L0_LATENCY 1
|
| 782 |
+
BP_MAIN_LATENCY 3
|
| 783 |
+
BIMODAL_ENTRIES (4 * 1024)
|
| 784 |
+
HIST_LENGTH 16
|
| 785 |
+
PHT_CTR_BITS 2 const
|
| 786 |
+
BHT_ENTRIES (4 * 1024)
|
| 787 |
+
BHT_ASSOC 4
|
| 788 |
+
HYBRIDS_INDEX_LENGTH 16
|
| 789 |
+
HYBRIDG_HIST_LENGTH 16
|
| 790 |
+
HYBRIDP_HIST_LENGTH 16
|
| 791 |
+
FILTER_INDEX_LENGTH 16
|
| 792 |
+
USE_FILTER FALSE
|
| 793 |
+
INF_HYBRIDGP FALSE
|
| 794 |
+
BP_HASH_TOS FALSE
|
| 795 |
+
IBTB_HASH_TOS FALSE
|
| 796 |
+
BTB_MECH GENERIC_BTB generic
|
| 797 |
+
BTB_ENTRIES 12288 12288
|
| 798 |
+
BTB_ASSOC 4 4
|
| 799 |
+
BTB_NUM_BRSLOT 1
|
| 800 |
+
BTB_BLOCK_SIZE 64
|
| 801 |
+
BTB_OFF_PATH_WRITES TRUE 1
|
| 802 |
+
BTB_MAIN_LATENCY 3 3
|
| 803 |
+
BTB_L0_PRESENT FALSE 1
|
| 804 |
+
BTB_L0_ENTRIES 128 128
|
| 805 |
+
BTB_L0_ASSOC 4 4
|
| 806 |
+
BTB_L0_LATENCY 1 1
|
| 807 |
+
BTB_L1_PRESENT FALSE 1
|
| 808 |
+
BTB_L1_ENTRIES 6144 6144
|
| 809 |
+
BTB_L1_ASSOC 4 4
|
| 810 |
+
BTB_L1_LATENCY 2 2
|
| 811 |
+
ENABLE_CRS TRUE 1
|
| 812 |
+
CRS_ENTRIES 32 128
|
| 813 |
+
CRS_REALISTIC 0 1
|
| 814 |
+
ENABLE_IBP TRUE 1 # Enable the indirect branch predictor
|
| 815 |
+
USE_PAT_HIST TRUE
|
| 816 |
+
IBTB_MECH 1 tc_tagged
|
| 817 |
+
IBTB_HIST_LENGTH 16
|
| 818 |
+
IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb.
|
| 819 |
+
TARGETS_IN_HIST 4
|
| 820 |
+
TC_ENTRIES (4 * 1024) 4096
|
| 821 |
+
TC_ASSOC 4 4
|
| 822 |
+
NUM_CORR_BRANCHES 3
|
| 823 |
+
SEL_HIST_BP_ENTRIES 8192
|
| 824 |
+
SEL_HIST_LENGTH 16
|
| 825 |
+
SEL_HIST_DYN_CNT_TH 16
|
| 826 |
+
SEL_HIST_MISPRED_TH 4
|
| 827 |
+
ENABLE_BP_CONF FALSE
|
| 828 |
+
CONF_MECH 0
|
| 829 |
+
PERF_BP_CONF_PRED FALSE
|
| 830 |
+
BPC_BITS 16
|
| 831 |
+
BPC_MECH 1
|
| 832 |
+
BPC_CTR_RESET TRUE
|
| 833 |
+
BPC_CIT_BITS 8
|
| 834 |
+
BPC_CIT_TH 50
|
| 835 |
+
BPC_CTR_BITS 3
|
| 836 |
+
OPC_COUNT_ZEROS FALSE
|
| 837 |
+
OPC_COUNT_THRESH 10
|
| 838 |
+
INF_LOOP FALSE
|
| 839 |
+
INF_LOOP_BUCKETS 811
|
| 840 |
+
LOOP_ENTRIES (4 * 1024)
|
| 841 |
+
LOOP_ASSOC 4
|
| 842 |
+
LOOP_COUNT_MAX 127
|
| 843 |
+
LOOP_REPEAT_MAX 15
|
| 844 |
+
KNOB_PRINT_BRINFO FALSE
|
| 845 |
+
BR_MISPRED_FILE NULL
|
| 846 |
+
SPEC_LEVEL 3
|
| 847 |
+
RANDOM_DETERMINISTIC TRUE
|
| 848 |
+
TAGESCL64KB_SC TRUE
|
| 849 |
+
TAGESCL64KB_LOOP TRUE
|
| 850 |
+
TAGESCL64KB_ALT TRUE
|
| 851 |
+
CONF_PERCEPTRON_TH 0
|
| 852 |
+
CONF_PERCEPTRON_CTR_BITS 8
|
| 853 |
+
CONF_PERCEPTRON_ENTRIES 127
|
| 854 |
+
CONF_PERCEPTRON_THRESH_OVRD 0
|
| 855 |
+
CONF_HIST_LENGTH 32
|
| 856 |
+
PERCEPTRON_CONF_USE_CONF FALSE
|
| 857 |
+
PERCEPTRON_CONF_TRAIN_HIS FALSE
|
| 858 |
+
PERCEPTRON_CONF_TRAIN_CONF FALSE
|
| 859 |
+
PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE
|
| 860 |
+
PERCEPTRON_TRAIN_MISP_FACTOR 1
|
| 861 |
+
PERCEPTRON_TRAIN_CORR_FACTOR 1
|
| 862 |
+
PERCEPTRON_CONF_HIS_BOTH FALSE
|
| 863 |
+
PERCEPTRON_CONF_HIS_BOTH_LENGTH 4
|
| 864 |
+
MTAGE_REALISTIC_SC_40K FALSE
|
| 865 |
+
MTAGE_REALISTIC_SC_100K FALSE
|
| 866 |
+
H2P_TABLE_BUCKETS 16384
|
| 867 |
+
H2P_MIN_EXEC 5000
|
| 868 |
+
H2P_MIN_MISPRED 333
|
| 869 |
+
H2P_MISPRED_RATIO_PERMIL 10
|
| 870 |
+
H2P_TRACK_CBR TRUE
|
| 871 |
+
H2P_TRACK_REP TRUE
|
| 872 |
+
H2P_TRACK_CALL FALSE
|
| 873 |
+
H2P_TRACK_IBR FALSE
|
| 874 |
+
H2P_TRACK_ICALL FALSE
|
| 875 |
+
H2P_TRACK_RET FALSE
|
| 876 |
+
POWER_INTF_ON FALSE
|
| 877 |
+
POWER_INTF_ENABLE_SCALING FALSE
|
| 878 |
+
POWER_INTF_EXEC "power/power_intf.py"
|
| 879 |
+
POWER_INTF_REF_CHIP_TECH_NM 22
|
| 880 |
+
POWER_INTF_REF_CHIP_FREQ (3.2e9)
|
| 881 |
+
POWER_INTF_REF_MEMORY_FREQ (0.8e9)
|
| 882 |
+
POWER_OTHER (0.0)
|
| 883 |
+
PREF_STREAM_ON FALSE 1
|
| 884 |
+
PREF_STREAM_PER_CORE_ENABLE FALSE
|
| 885 |
+
STREAM_BUFFER_N 16
|
| 886 |
+
STREAM_PREFETCH_N 2 4
|
| 887 |
+
STREAM_START_DIS 5 1
|
| 888 |
+
STREAM_LENGTH 16 64
|
| 889 |
+
STREAM_FULL_N 1
|
| 890 |
+
STREAM_TRAIN_LENGTH 16
|
| 891 |
+
STREAM_TRAIN_NUM 1 4
|
| 892 |
+
PREF_ACC_USE_CACHE FALSE
|
| 893 |
+
STREAM_STALL_ON_QUEUE_FULL FALSE
|
| 894 |
+
PREF_SCHEDULE_NUM 4
|
| 895 |
+
TRAIN_FILTER_SIZE 32
|
| 896 |
+
PREF_REQ_Q_SIZE 64
|
| 897 |
+
STREAM_CREATE_ON_DC_MISS FALSE 0
|
| 898 |
+
STREAM_CREATE_ON_L1_MISS TRUE 1
|
| 899 |
+
STREAM_TRAIN_ON_WRONGPATH TRUE
|
| 900 |
+
STREAM_CREATE_ON_WRONGPATH TRUE
|
| 901 |
+
STREAM_PREF_INTO_DCACHE FALSE
|
| 902 |
+
REMOVE_REDUNDANT_STREAM FALSE
|
| 903 |
+
L2HIT_STREAM_SCHEDULE_NUM 4
|
| 904 |
+
PREF_REQ_QUEUE_FILTER_ON FALSE
|
| 905 |
+
HW_PREF_HIT_TRAIN_STREAM FALSE
|
| 906 |
+
L2HIT_STREAM_BUFFER_N 32
|
| 907 |
+
L2HIT_STREAM_PREFETCH_N 2
|
| 908 |
+
L2HIT_STREAM_START_DIS 2
|
| 909 |
+
L2HIT_STREAM_LENGTH 8
|
| 910 |
+
L2HIT_PREF_REQ_Q_SIZE 128
|
| 911 |
+
L2HIT_L2ACCESS_REQ_Q_SIZE 64
|
| 912 |
+
PREF_STREAM_ACCPERSTREAM FALSE
|
| 913 |
+
PREF_ACC_DISTANCE_10 128
|
| 914 |
+
PREF_FRAMEWORK_ON FALSE 1
|
| 915 |
+
PREF_TRACE_ON FALSE
|
| 916 |
+
PREF_UMLC_ON FALSE
|
| 917 |
+
PREF_UL1_ON TRUE
|
| 918 |
+
PREF_DL0REQ_QUEUE_SIZE 32
|
| 919 |
+
PREF_UMLC_REQ_QUEUE_SIZE 64
|
| 920 |
+
PREF_UL1REQ_QUEUE_SIZE 128
|
| 921 |
+
PREF_SHARED_QUEUES TRUE
|
| 922 |
+
PREF_DL0_MISS_ON TRUE
|
| 923 |
+
PREF_DL0_HIT_ON TRUE
|
| 924 |
+
PREF_DL0REQ_QUEUE_FILTER_ON TRUE
|
| 925 |
+
PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE
|
| 926 |
+
PREF_UL1REQ_QUEUE_FILTER_ON TRUE
|
| 927 |
+
PREF_DL0REQ_ADD_FILTER_ON TRUE
|
| 928 |
+
PREF_UMLC_REQ_ADD_FILTER_ON TRUE
|
| 929 |
+
PREF_UL1REQ_ADD_FILTER_ON TRUE
|
| 930 |
+
PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 931 |
+
PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 932 |
+
PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1
|
| 933 |
+
PREF_DL0SCHEDULE_NUM 4
|
| 934 |
+
PREF_UMLC_SCHEDULE_NUM 4
|
| 935 |
+
PREF_UL1SCHEDULE_NUM 4
|
| 936 |
+
PREF_L1Q_DEMAND_RESERVE 0
|
| 937 |
+
PREF_REPORT_PREF_MATCH_AS_MISS FALSE
|
| 938 |
+
PREF_REPORT_PREF_MATCH_AS_HIT TRUE
|
| 939 |
+
PREF_UPDATE_ON_WRONGPATH TRUE
|
| 940 |
+
PREF_TRAIN_ON_PREF_MISSES FALSE 0
|
| 941 |
+
PREF_ORACLE_TRAIN_ON FALSE 0
|
| 942 |
+
PREF_REQ_DROP FALSE
|
| 943 |
+
PREF_THROTTLE_ON FALSE
|
| 944 |
+
PREF_THROTTLEFB_ON FALSE 1
|
| 945 |
+
PREF_ACC_THRESH_1 0.90 0.75
|
| 946 |
+
PREF_ACC_THRESH_2 0.70 0.4
|
| 947 |
+
PREF_ACC_THRESH_3 0.60 0.4
|
| 948 |
+
PREF_ACC_THRESH_4 0.40
|
| 949 |
+
PREF_UPDATE_INTERVAL 0 8192
|
| 950 |
+
PREF_ANALYZE_LOAD FALSE
|
| 951 |
+
PREF_POL_THRESH_1 0.25
|
| 952 |
+
PREF_POL_THRESH_2 0.10
|
| 953 |
+
PREF_POLBV_ON FALSE
|
| 954 |
+
PREF_POLBV_SIZE 1024
|
| 955 |
+
PREF_TIMELY_THRESH 0.05 0.01
|
| 956 |
+
PREF_POLPF_THRESH 0.01 0.005
|
| 957 |
+
PREF_DEGFB_USEONLYACC FALSE
|
| 958 |
+
PREF_DEGFB_USEONLYPOL FALSE
|
| 959 |
+
PREF_DEGFB_USEONLYLATE FALSE
|
| 960 |
+
PREF_TIMELY_THRESH_2 0.005
|
| 961 |
+
PREF_DEGFB_STATPHASEFILE FALSE
|
| 962 |
+
PREF_MAX_DEGFB 4
|
| 963 |
+
PREF_DHAL FALSE
|
| 964 |
+
PREF_DHAL_SENTTHRESH 16
|
| 965 |
+
PREF_DHAL_USETHRESH_MAX 12
|
| 966 |
+
PREF_DHAL_USETHRESH_MIN2 8
|
| 967 |
+
PREF_DHAL_USETHRESH_MIN1 4
|
| 968 |
+
PREF_DHAL_MAXDEG 64
|
| 969 |
+
PREF_HFILTER_ON FALSE
|
| 970 |
+
PREF_HFILTER_INDEX_BITS 12
|
| 971 |
+
PREF_HFILTER_USE_PC FALSE
|
| 972 |
+
PREF_HFILTER_PRED_USELESS_THRES 2
|
| 973 |
+
PREF_HFILTER_RESET_ENABLE FALSE
|
| 974 |
+
PREF_HFILTER_RESET_INTERVAL 100000
|
| 975 |
+
EIP_ENABLE 0
|
| 976 |
+
L1I_ENTANGLED_TABLE_INDEX_BITS 9
|
| 977 |
+
L1I_ENTANGLED_TABLE_WAYS 16
|
| 978 |
+
DJOLT_ENABLE 0
|
| 979 |
+
FNLMMA_ENABLE 0
|
| 980 |
+
FDIP_ENABLE 1
|
| 981 |
+
FDIP_ALWAYS_PREFETCH FALSE
|
| 982 |
+
PERFECT_FDIP FALSE
|
| 983 |
+
IPRF_MAX_FTQ_ENTRY_CYC 2
|
| 984 |
+
FDIP_BLOOM_FILTER FALSE
|
| 985 |
+
FDIP_BLOOM_ENTRIES 4000
|
| 986 |
+
FDIP_BLOOM2_ENTRIES 1000
|
| 987 |
+
FDIP_BLOOM4_ENTRIES 1000
|
| 988 |
+
FDIP_BLOOM_SIZE 16384
|
| 989 |
+
FDIP_BLOOM_HASHES 6
|
| 990 |
+
FDIP_BLOOM_CLEAR_UNUSEFUL_RATIO 0.95
|
| 991 |
+
FDIP_BLOOM_CLEAR_CYC_PERIOD 10000
|
| 992 |
+
FDIP_UTILITY_HASH_ENABLE 0
|
| 993 |
+
FDIP_UTILITY_PREF_POLICY 0
|
| 994 |
+
FDIP_ADJUSTABLE_FTQ 0
|
| 995 |
+
FDIP_ADJUSTABLE_FTQ_CYC 100000
|
| 996 |
+
UTILITY_RATIO_THRESHOLD 0.58
|
| 997 |
+
TIMELINESS_RATIO_THRESHOLD 0.82
|
| 998 |
+
FDIP_PREF_NO_LATENCY FALSE
|
| 999 |
+
UDP_USEFUL_THRESHOLD 0
|
| 1000 |
+
UDP_WEIGHT_USEFUL 4
|
| 1001 |
+
UDP_WEIGHT_UNUSEFUL 1
|
| 1002 |
+
UDP_WEIGHT_POSITIVE_SATURATION 2147483647
|
| 1003 |
+
FDIP_GHIST_HASHING FALSE
|
| 1004 |
+
FDIP_UTILITY_ONLY_TRAIN_OFF_PATH FALSE
|
| 1005 |
+
FDIP_GHIST_BITS 8
|
| 1006 |
+
UFTQ_MIN_FTQ_BLOCK_NUM 4
|
| 1007 |
+
UFTQ_MAX_FTQ_BLOCK_NUM 64
|
| 1008 |
+
FDIP_SENIORITY_FTQ_HOLD_CYC 30000
|
| 1009 |
+
FDIP_PERFECT_PREFETCH FALSE
|
| 1010 |
+
FDIP_FREEZE_AT_MEM_BUF_LIMIT TRUE
|
| 1011 |
+
FDIP_DUAL_PATH_PREF_IC_ENABLE FALSE
|
| 1012 |
+
FDIP_DUAL_PATH_PREF_UOC_ENABLE FALSE
|
| 1013 |
+
TOP_MISPRED_BR_FILEPATH "br_resteer_coverage.csv"
|
| 1014 |
+
TOP_MISPRED_BR_RESTEER_COVERAGE 0
|
| 1015 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_ENABLE FALSE
|
| 1016 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_MISPRED_THRESHOLD 1
|
| 1017 |
+
FDIP_PRINT_CL_INFO FALSE
|
| 1018 |
+
BRANCH_MISPREDICTION_TABLE_SIZE 0
|
| 1019 |
+
UOC_PREF FALSE
|
| 1020 |
+
UOC_ORACLE_PREF FALSE
|
| 1021 |
+
UOC_ZERO_LATENCY_PREF FALSE
|
| 1022 |
+
L2L1PREF_ON FALSE
|
| 1023 |
+
L2WAY_PREF FALSE
|
| 1024 |
+
L2MARKV_PREF_ON FALSE
|
| 1025 |
+
L2NEXT_PREF_ON FALSE
|
| 1026 |
+
L2HIT_STREAM_PREF_ON FALSE
|
| 1027 |
+
L2L1_DC_HIT_TRAIN FALSE
|
| 1028 |
+
L1_HIT_DUMP_FILE_ON FALSE
|
| 1029 |
+
L1_HIT_DUMP_WO_TXT FALSE
|
| 1030 |
+
L1_HIT_DUMPFILE "l1hit_dump.out"
|
| 1031 |
+
IDEAL_L2_L1_PREFETCHER FALSE
|
| 1032 |
+
IDEAL_L2_ICACHE_PREFETCHER FALSE
|
| 1033 |
+
L1WAY_PREF_SEND_QUEUE 4
|
| 1034 |
+
L1PREF_REQ_QUEUE_SIZE 1024
|
| 1035 |
+
L1PREF_IMMEDIATE FALSE
|
| 1036 |
+
L1WAY_PREF_TIMER_DIS 1000
|
| 1037 |
+
L1MARKV_PREF_SEND_QUEUE 4
|
| 1038 |
+
L1PREF_MARKV_REQ_QUEUE_SIZE 1024
|
| 1039 |
+
MARKV_L2ACCESS_REQ_Q_SIZE 64
|
| 1040 |
+
L1MARKV_PREF_IMMEDIATE FALSE
|
| 1041 |
+
L1MARKV_PREF_TIMER_DIS 1
|
| 1042 |
+
L2L1_HIT_TRAIN TRUE
|
| 1043 |
+
L1MARKV_REQ_TH 1
|
| 1044 |
+
L2L1_IMMEDIATE_PREF_CACHE FALSE
|
| 1045 |
+
L2L1_FILL_PREF_CACHE FALSE
|
| 1046 |
+
L2L1_L2_HIT_STAT FALSE
|
| 1047 |
+
PREF_GHB_ON FALSE
|
| 1048 |
+
DEBUG_PREF_GHB FALSE
|
| 1049 |
+
PREF_GHB_BUFFER_N 1024
|
| 1050 |
+
PREF_GHB_INDEX_N 128
|
| 1051 |
+
PREF_GHB_CZONE_BITS 12
|
| 1052 |
+
PREF_GHB_DEGREE 16
|
| 1053 |
+
PREF_GHB_MAX_DEGREE 32
|
| 1054 |
+
PREF_STRIDE_ON FALSE
|
| 1055 |
+
DEBUG_PREF_STRIDE FALSE
|
| 1056 |
+
PREF_STRIDE_TABLE_N 1024
|
| 1057 |
+
PREF_STRIDE_REGION_BITS 16
|
| 1058 |
+
PREF_STRIDE_DEGREE 4
|
| 1059 |
+
PREF_STRIDE_DISTANCE 16
|
| 1060 |
+
PREF_STRIDE_STARTDISTANCE 1
|
| 1061 |
+
PREF_STRIDE_SINGLE_THRESH 6
|
| 1062 |
+
PREF_STRIDE_MULTI_THRESH 6
|
| 1063 |
+
PREF_STRIDE_SINGLE_STRIDE_MODE FALSE
|
| 1064 |
+
PREF_STRIDEPC_ON FALSE
|
| 1065 |
+
DEBUG_PREF_STRIDEPC FALSE
|
| 1066 |
+
PREF_STRIDEPC_TABLE_N 1024
|
| 1067 |
+
PREF_STRIDEPC_DEGREE 4
|
| 1068 |
+
PREF_STRIDEPC_DISTANCE 16
|
| 1069 |
+
PREF_STRIDEPC_USELOADADDR FALSE
|
| 1070 |
+
PREF_STRIDEPC_TRAINNUM 2
|
| 1071 |
+
PREF_STRIDEPC_STARTDIS 4
|
| 1072 |
+
PREF_PHASE_ON FALSE
|
| 1073 |
+
PREF_PHASE_STUDY FALSE
|
| 1074 |
+
DEBUG_PREF_PHASE FALSE
|
| 1075 |
+
PREF_PHASE_PRIME_HASH 16381
|
| 1076 |
+
PREF_PHASE_INFOSIZE 16384
|
| 1077 |
+
PREF_PHASE_LOG2REGIONSIZE 12
|
| 1078 |
+
PREF_PHASE_REGIONENTRIES 64
|
| 1079 |
+
PREF_PHASE_TRACKEDREGIONS 32
|
| 1080 |
+
PREF_PHASE_INTERVAL 100000
|
| 1081 |
+
PREF_PHASE_TABLE_SIZE 64
|
| 1082 |
+
PREF_PHASE_MAXDIFF_THRESH 64
|
| 1083 |
+
PREF_PHASE_MIN_MISSES 64
|
| 1084 |
+
PREF_PHASE_MISSPER 0.4
|
| 1085 |
+
PREF_2DC_ON FALSE
|
| 1086 |
+
DEBUG_PREF_2DC FALSE
|
| 1087 |
+
PREF_2DC_CACHE_SIZE (1 * 1024)
|
| 1088 |
+
PREF_2DC_CACHE_ASSOC 4
|
| 1089 |
+
PREF_2DC_CACHE_LINE_SIZE 1
|
| 1090 |
+
PREF_2DC_DEGREE 16
|
| 1091 |
+
PREF_2DC_ZONE_SHIFT 10
|
| 1092 |
+
PREF_2DC_TAG_SIZE 16
|
| 1093 |
+
PREF_2DC_NUM_REGIONS 64
|
| 1094 |
+
PREF_2DC_REGION_HASH 61
|
| 1095 |
+
PREF_MARKOV_ON FALSE
|
| 1096 |
+
DEBUG_PREF_MARKOV FALSE
|
| 1097 |
+
PREF_MARKOV_NUM_ENTRIES 65536
|
| 1098 |
+
PREF_MARKOV_NUM_NEXT_STATES 8
|
| 1099 |
+
PREF_MARKOV_SEND_ON_PREF_HIT TRUE
|
| 1100 |
+
PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE
|
| 1101 |
+
PREF_MARKOV_TABLE_UPDATE_POLICY 0
|
| 1102 |
+
PREF_MARKOV_SEND_THRESHOLD 0
|
sssp_facebook/fingerprint/run_2/sim.log
ADDED
|
@@ -0,0 +1,279 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
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|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
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|
|
|
|
|
|
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|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
[0]: ad: 0x7ffff3d9b7c1, op: 427
|
| 2 |
+
[0]: ad: 0x7ffff3d9b7c8, op: 427
|
| 3 |
+
[0]: ad: 0x7ffff3d9b7cc, op: 847
|
| 4 |
+
[0]: ad: 0x7ffff3d9b7cf, op: 330
|
| 5 |
+
new bb detected: 1
|
| 6 |
+
[1]: ad: 0x7ffff3d9b7b0, op: 388
|
| 7 |
+
[1]: ad: 0x7ffff3d9b7b3, op: 8
|
| 8 |
+
[1]: ad: 0x7ffff3d9b7b7, op: 109
|
| 9 |
+
[1]: ad: 0x7ffff3d9b7bb, op: 315
|
| 10 |
+
new bb detected: 2
|
| 11 |
+
[2]: ad: 0x7ffff3d9b88d, op: 427
|
| 12 |
+
[2]: ad: 0x7ffff3d9b890, op: 427
|
| 13 |
+
[2]: ad: 0x7ffff3d9b894, op: 427
|
| 14 |
+
[2]: ad: 0x7ffff3d9b897, op: 427
|
| 15 |
+
[2]: ad: 0x7ffff3d9b89a, op: 109
|
| 16 |
+
[2]: ad: 0x7ffff3d9b89e, op: 315
|
| 17 |
+
new bb detected: 3
|
| 18 |
+
[3]: ad: 0x7ffff3d9b9ba, op: 427
|
| 19 |
+
[3]: ad: 0x7ffff3d9b9bf, op: 427
|
| 20 |
+
[3]: ad: 0x7ffff3d9b9c3, op: 75
|
| 21 |
+
new bb detected: 4
|
| 22 |
+
[4]: ad: 0x7ffff3d9a250, op: 482
|
| 23 |
+
[4]: ad: 0x7ffff3d9a254, op: 316
|
| 24 |
+
new bb detected: 5
|
| 25 |
+
[5]: ad: 0x7ffff7345910, op: 482
|
| 26 |
+
[5]: ad: 0x7ffff7345914, op: 671
|
| 27 |
+
[5]: ad: 0x7ffff7345916, op: 427
|
| 28 |
+
[5]: ad: 0x7ffff7345919, op: 671
|
| 29 |
+
[5]: ad: 0x7ffff734591b, op: 427
|
| 30 |
+
[5]: ad: 0x7ffff7345921, op: 671
|
| 31 |
+
[5]: ad: 0x7ffff7345923, op: 427
|
| 32 |
+
[5]: ad: 0x7ffff7345929, op: 671
|
| 33 |
+
[5]: ad: 0x7ffff734592a, op: 427
|
| 34 |
+
[5]: ad: 0x7ffff734592f, op: 671
|
| 35 |
+
[5]: ad: 0x7ffff7345930, op: 427
|
| 36 |
+
[5]: ad: 0x7ffff7345936, op: 1717
|
| 37 |
+
[5]: ad: 0x7ffff734593b, op: 1723
|
| 38 |
+
[5]: ad: 0x7ffff734593d, op: 427
|
| 39 |
+
[5]: ad: 0x7ffff7345941, op: 427
|
| 40 |
+
[5]: ad: 0x7ffff7345944, op: 427
|
| 41 |
+
[5]: ad: 0x7ffff7345947, op: 8
|
| 42 |
+
[5]: ad: 0x7ffff734594b, op: 157
|
| 43 |
+
[5]: ad: 0x7ffff734594e, op: 826
|
| 44 |
+
[5]: ad: 0x7ffff7345950, op: 109
|
| 45 |
+
[5]: ad: 0x7ffff7345953, op: 319
|
| 46 |
+
new bb detected: 6
|
| 47 |
+
[6]: ad: 0x7ffff7345955, op: 316
|
| 48 |
+
new bb detected: 7
|
| 49 |
+
[7]: ad: 0x7ffff734599f, op: 427
|
| 50 |
+
[7]: ad: 0x7ffff73459a3, op: 388
|
| 51 |
+
[7]: ad: 0x7ffff73459a7, op: 388
|
| 52 |
+
[7]: ad: 0x7ffff73459ab, op: 109
|
| 53 |
+
[7]: ad: 0x7ffff73459ae, op: 319
|
| 54 |
+
new bb detected: 8
|
| 55 |
+
[8]: ad: 0x7ffff73459b4, op: 427
|
| 56 |
+
[8]: ad: 0x7ffff73459b7, op: 1723
|
| 57 |
+
[8]: ad: 0x7ffff73459b9, op: 427
|
| 58 |
+
[8]: ad: 0x7ffff73459bc, op: 157
|
| 59 |
+
[8]: ad: 0x7ffff73459bf, op: 427
|
| 60 |
+
[8]: ad: 0x7ffff73459c1, op: 826
|
| 61 |
+
[8]: ad: 0x7ffff73459c4, op: 123
|
| 62 |
+
[8]: ad: 0x7ffff73459c9, op: 427
|
| 63 |
+
[8]: ad: 0x7ffff73459cb, op: 325
|
| 64 |
+
new bb detected: 9
|
| 65 |
+
[9]: ad: 0x7ffff73459cd, op: 427
|
| 66 |
+
[9]: ad: 0x7ffff73459d1, op: 1723
|
| 67 |
+
[9]: ad: 0x7ffff73459d4, op: 427
|
| 68 |
+
[9]: ad: 0x7ffff73459d9, op: 427
|
| 69 |
+
[9]: ad: 0x7ffff73459de, op: 1723
|
| 70 |
+
[9]: ad: 0x7ffff73459e2, op: 833
|
| 71 |
+
new bb detected: 10
|
| 72 |
+
[10]: ad: 0x7ffff73459e4, op: 109
|
| 73 |
+
[10]: ad: 0x7ffff73459ea, op: 319
|
| 74 |
+
new bb detected: 11
|
| 75 |
+
[11]: ad: 0x7ffff73459ec, op: 109
|
| 76 |
+
[11]: ad: 0x7ffff73459ef, op: 311
|
| 77 |
+
new bb detected: 12
|
| 78 |
+
[12]: ad: 0x7ffff7345a40, op: 388
|
| 79 |
+
[12]: ad: 0x7ffff7345a44, op: 427
|
| 80 |
+
[12]: ad: 0x7ffff7345a49, op: 1717
|
| 81 |
+
[12]: ad: 0x7ffff7345a4d, op: 8
|
| 82 |
+
[12]: ad: 0x7ffff7345a50, op: 109
|
| 83 |
+
[12]: ad: 0x7ffff7345a52, op: 330
|
| 84 |
+
new bb detected: 13
|
| 85 |
+
[13]: ad: 0x7ffff7345a54, op: 1723
|
| 86 |
+
[13]: ad: 0x7ffff7345a56, op: 427
|
| 87 |
+
[13]: ad: 0x7ffff7345a59, op: 616
|
| 88 |
+
[13]: ad: 0x7ffff7345a5a, op: 616
|
| 89 |
+
[13]: ad: 0x7ffff7345a5b, op: 157
|
| 90 |
+
[13]: ad: 0x7ffff7345a5e, op: 616
|
| 91 |
+
[13]: ad: 0x7ffff7345a60, op: 616
|
| 92 |
+
[13]: ad: 0x7ffff7345a62, op: 616
|
| 93 |
+
[13]: ad: 0x7ffff7345a64, op: 109
|
| 94 |
+
[13]: ad: 0x7ffff7345a67, op: 759
|
| 95 |
+
[13]: ad: 0x7ffff7345a69, op: 740
|
| 96 |
+
new bb detected: 14
|
| 97 |
+
[14]: ad: 0x7ffff3d9b9c8, op: 427
|
| 98 |
+
[14]: ad: 0x7ffff3d9b9cc, op: 847
|
| 99 |
+
[14]: ad: 0x7ffff3d9b9ce, op: 325
|
| 100 |
+
new bb detected: 15
|
| 101 |
+
[15]: ad: 0x7ffff3d9b9d0, op: 427
|
| 102 |
+
[15]: ad: 0x7ffff3d9b9d4, op: 285
|
| 103 |
+
[15]: ad: 0x7ffff3d9b9db, op: 109
|
| 104 |
+
[15]: ad: 0x7ffff3d9b9dd, op: 100
|
| 105 |
+
[15]: ad: 0x7ffff3d9b9e0, op: 427
|
| 106 |
+
[15]: ad: 0x7ffff3d9b9e6, op: 427
|
| 107 |
+
[15]: ad: 0x7ffff3d9b9eb, op: 427
|
| 108 |
+
[15]: ad: 0x7ffff3d9b9ef, op: 75
|
| 109 |
+
new bb detected: 16
|
| 110 |
+
[16]: ad: 0x7ffff3d9b9f4, op: 458
|
| 111 |
+
[16]: ad: 0x7ffff3d9b9fa, op: 427
|
| 112 |
+
[16]: ad: 0x7ffff3d9ba00, op: 678
|
| 113 |
+
[16]: ad: 0x7ffff3d9ba04, op: 428
|
| 114 |
+
[16]: ad: 0x7ffff3d9ba08, op: 141
|
| 115 |
+
[16]: ad: 0x7ffff3d9ba0c, op: 160
|
| 116 |
+
[16]: ad: 0x7ffff3d9ba12, op: 475
|
| 117 |
+
[16]: ad: 0x7ffff3d9ba16, op: 149
|
| 118 |
+
[16]: ad: 0x7ffff3d9ba1a, op: 458
|
| 119 |
+
[16]: ad: 0x7ffff3d9ba22, op: 11
|
| 120 |
+
[16]: ad: 0x7ffff3d9ba26, op: 475
|
| 121 |
+
[16]: ad: 0x7ffff3d9ba2a, op: 149
|
| 122 |
+
[16]: ad: 0x7ffff3d9ba2e, op: 109
|
| 123 |
+
[16]: ad: 0x7ffff3d9ba30, op: 96
|
| 124 |
+
[16]: ad: 0x7ffff3d9ba33, op: 427
|
| 125 |
+
[16]: ad: 0x7ffff3d9ba35, op: 109
|
| 126 |
+
[16]: ad: 0x7ffff3d9ba37, op: 330
|
| 127 |
+
new bb detected: 17
|
| 128 |
+
[17]: ad: 0x7ffff3d9ba39, op: 109
|
| 129 |
+
[17]: ad: 0x7ffff3d9ba3d, op: 315
|
| 130 |
+
new bb detected: 18
|
| 131 |
+
[18]: ad: 0x7ffff3d9ba80, op: 427
|
| 132 |
+
[18]: ad: 0x7ffff3d9ba84, op: 427
|
| 133 |
+
[18]: ad: 0x7ffff3d9ba8e, op: 316
|
| 134 |
+
new bb detected: 19
|
| 135 |
+
[19]: ad: 0x7ffff3d9ba43, op: 427
|
| 136 |
+
[19]: ad: 0x7ffff3d9ba48, op: 427
|
| 137 |
+
[19]: ad: 0x7ffff3d9ba4c, op: 75
|
| 138 |
+
new bb detected: 20
|
| 139 |
+
[20]: ad: 0x7ffff3d9ba51, op: 427
|
| 140 |
+
[20]: ad: 0x7ffff3d9ba57, op: 847
|
| 141 |
+
[20]: ad: 0x7ffff3d9ba59, op: 427
|
| 142 |
+
[20]: ad: 0x7ffff3d9ba5d, op: 325
|
| 143 |
+
new bb detected: 21
|
| 144 |
+
[21]: ad: 0x7ffff3d9ba90, op: 427
|
| 145 |
+
[21]: ad: 0x7ffff3d9ba95, op: 427
|
| 146 |
+
[21]: ad: 0x7ffff3d9ba99, op: 75
|
| 147 |
+
new bb detected: 22
|
| 148 |
+
[22]: ad: 0x7ffff3d9ba9e, op: 427
|
| 149 |
+
[22]: ad: 0x7ffff3d9baa2, op: 847
|
| 150 |
+
[22]: ad: 0x7ffff3d9baa4, op: 325
|
| 151 |
+
new bb detected: 23
|
| 152 |
+
[23]: ad: 0x7ffff3d9baa6, op: 8
|
| 153 |
+
[23]: ad: 0x7ffff3d9baab, op: 427
|
| 154 |
+
[23]: ad: 0x7ffff3d9baaf, op: 109
|
| 155 |
+
[23]: ad: 0x7ffff3d9bab5, op: 315
|
| 156 |
+
new bb detected: 24
|
| 157 |
+
[24]: ad: 0x7ffff3d9bab7, op: 427
|
| 158 |
+
[24]: ad: 0x7ffff3d9bac1, op: 427
|
| 159 |
+
[24]: ad: 0x7ffff3d9bacb, op: 427
|
| 160 |
+
[24]: ad: 0x7ffff3d9bad0, op: 427
|
| 161 |
+
[24]: ad: 0x7ffff3d9bad4, op: 75
|
| 162 |
+
new bb detected: 25
|
| 163 |
+
[25]: ad: 0x7ffff3d9bad9, op: 427
|
| 164 |
+
[25]: ad: 0x7ffff3d9badf, op: 847
|
| 165 |
+
[25]: ad: 0x7ffff3d9bae1, op: 330
|
| 166 |
+
new bb detected: 26
|
| 167 |
+
[26]: ad: 0x7ffff3d9b769, op: 427
|
| 168 |
+
[26]: ad: 0x7ffff3d9b771, op: 1723
|
| 169 |
+
[26]: ad: 0x7ffff3d9b773, op: 109
|
| 170 |
+
[26]: ad: 0x7ffff3d9b777, op: 320
|
| 171 |
+
new bb detected: 27
|
| 172 |
+
[27]: ad: 0x7ffff3d9b77d, op: 482
|
| 173 |
+
[27]: ad: 0x7ffff3d9b780, op: 109
|
| 174 |
+
[27]: ad: 0x7ffff3d9b782, op: 315
|
| 175 |
+
new bb detected: 28
|
| 176 |
+
[28]: ad: 0x7ffff3d9b788, op: 427
|
| 177 |
+
[28]: ad: 0x7ffff3d9b78c, op: 465
|
| 178 |
+
[28]: ad: 0x7ffff3d9b78f, op: 427
|
| 179 |
+
[28]: ad: 0x7ffff3d9b793, op: 109
|
| 180 |
+
[28]: ad: 0x7ffff3d9b795, op: 96
|
| 181 |
+
[28]: ad: 0x7ffff3d9b798, op: 427
|
| 182 |
+
[28]: ad: 0x7ffff3d9b79b, op: 427
|
| 183 |
+
[28]: ad: 0x7ffff3d9b79f, op: 427
|
| 184 |
+
[28]: ad: 0x7ffff3d9b7a2, op: 427
|
| 185 |
+
[28]: ad: 0x7ffff3d9b7a5, op: 427
|
| 186 |
+
[28]: ad: 0x7ffff3d9b7a8, op: 316
|
| 187 |
+
new bb detected: 29
|
| 188 |
+
[29]: ad: 0x7ffff3d9b7d1, op: 427
|
| 189 |
+
[29]: ad: 0x7ffff3d9b7d6, op: 847
|
| 190 |
+
[29]: ad: 0x7ffff3d9b7d9, op: 315
|
| 191 |
+
new bb detected: 30
|
| 192 |
+
[30]: ad: 0x7ffff3d9b7db, op: 427
|
| 193 |
+
[30]: ad: 0x7ffff3d9b7de, op: 1723
|
| 194 |
+
[30]: ad: 0x7ffff3d9b7e0, op: 427
|
| 195 |
+
[30]: ad: 0x7ffff3d9b7e3, op: 316
|
| 196 |
+
new bb detected: 31
|
| 197 |
+
[31]: ad: 0x7ffff3d9b7f2, op: 427
|
| 198 |
+
[31]: ad: 0x7ffff3d9b7f6, op: 427
|
| 199 |
+
[31]: ad: 0x7ffff3d9b7fa, op: 109
|
| 200 |
+
[31]: ad: 0x7ffff3d9b7ff, op: 315
|
| 201 |
+
new bb detected: 32
|
| 202 |
+
[32]: ad: 0x7ffff3d9b801, op: 427
|
| 203 |
+
[32]: ad: 0x7ffff3d9b805, op: 465
|
| 204 |
+
[32]: ad: 0x7ffff3d9b808, op: 427
|
| 205 |
+
[32]: ad: 0x7ffff3d9b80c, op: 8
|
| 206 |
+
[32]: ad: 0x7ffff3d9b80f, op: 109
|
| 207 |
+
[32]: ad: 0x7ffff3d9b813, op: 315
|
| 208 |
+
new bb detected: 33
|
| 209 |
+
[33]: ad: 0x7ffff3d9b7e8, op: 8
|
| 210 |
+
[33]: ad: 0x7ffff3d9b7ec, op: 109
|
| 211 |
+
[33]: ad: 0x7ffff3d9b7f0, op: 330
|
| 212 |
+
new bb detected: 34
|
| 213 |
+
[34]: ad: 0x7ffff3d9b870, op: 427
|
| 214 |
+
[34]: ad: 0x7ffff3d9b873, op: 388
|
| 215 |
+
[34]: ad: 0x7ffff3d9b876, op: 427
|
| 216 |
+
[34]: ad: 0x7ffff3d9b879, op: 8
|
| 217 |
+
[34]: ad: 0x7ffff3d9b87d, op: 427
|
| 218 |
+
[34]: ad: 0x7ffff3d9b880, op: 427
|
| 219 |
+
[34]: ad: 0x7ffff3d9b883, op: 109
|
| 220 |
+
[34]: ad: 0x7ffff3d9b887, op: 321
|
| 221 |
+
new bb detected: 35
|
| 222 |
+
[35]: ad: 0x7ffff3d9ba3f, op: 427
|
| 223 |
+
[35]: ad: 0x7ffff3d9ba43, op: 427
|
| 224 |
+
[35]: ad: 0x7ffff3d9ba48, op: 427
|
| 225 |
+
[35]: ad: 0x7ffff3d9ba4c, op: 75
|
| 226 |
+
new bb detected: 36
|
| 227 |
+
[36]: ad: 0x7ffff3d9ba5f, op: 427
|
| 228 |
+
[36]: ad: 0x7ffff3d9ba63, op: 109
|
| 229 |
+
[36]: ad: 0x7ffff3d9ba67, op: 314
|
| 230 |
+
new bb detected: 37
|
| 231 |
+
[37]: ad: 0x7ffff3d9b780, op: 109
|
| 232 |
+
[37]: ad: 0x7ffff3d9b782, op: 315
|
| 233 |
+
new bb detected: 38
|
| 234 |
+
Scarab gitrev: 7185dea
|
| 235 |
+
Warning: Scarab expects the trace file type to include OFFLINE_FILE_TYPE_ARCH_REGDEPS (0x20000), but got type: 0xe40
|
| 236 |
+
Scarab started at Fri Jul 17 23:07:24 2026
|
| 237 |
+
|
| 238 |
+
read from initialization: 0x7ffff3d9b7c1
|
| 239 |
+
advanceReader: ROI end reached (ordinal 30000002 > roi_end 30000000)
|
| 240 |
+
Reached end of trace (last_inst) pc=0x7ffff3d9b7cc
|
| 241 |
+
[1]: ad: 0x7ffff3d9b7c1, op: 427
|
| 242 |
+
[1]: ad: 0x7ffff3d9b7c8, op: 427
|
| 243 |
+
DUP bb detected at trace end
|
| 244 |
+
to be appened segment num 1
|
| 245 |
+
10000000
|
| 246 |
+
10000000
|
| 247 |
+
====================================
|
| 248 |
+
TRACE_INST_TAKEN_NOT_CF:0
|
| 249 |
+
TRACE_INST_TAKEN_CF_BR:8226
|
| 250 |
+
TRACE_INST_TAKEN_CF_CBR:1137086
|
| 251 |
+
TRACE_INST_TAKEN_CF_REP:0
|
| 252 |
+
TRACE_INST_TAKEN_CF_CALL:14
|
| 253 |
+
TRACE_INST_TAKEN_CF_IBR:14
|
| 254 |
+
TRACE_INST_TAKEN_CF_ICALL:0
|
| 255 |
+
TRACE_INST_TAKEN_CF_ICO:0
|
| 256 |
+
TRACE_INST_TAKEN_CF_RET:14
|
| 257 |
+
TRACE_INST_TAKEN_CF_SYS:14
|
| 258 |
+
====================================
|
| 259 |
+
identity within this segment
|
| 260 |
+
2 bbs with same first pc
|
| 261 |
+
[1]: size 4, freq 959762
|
| 262 |
+
7ffff3d9b7c1: 427, 0
|
| 263 |
+
7ffff3d9b7c8: 427, 0
|
| 264 |
+
7ffff3d9b7cc: 847, 0
|
| 265 |
+
7ffff3d9b7cf: 330, 0
|
| 266 |
+
[1]: size 2, freq 1
|
| 267 |
+
7ffff3d9b7c1: 427, 0
|
| 268 |
+
7ffff3d9b7c8: 427, 0
|
| 269 |
+
1 / 38
|
| 270 |
+
========================================================
|
| 271 |
+
Number of blocks built : 38
|
| 272 |
+
Average size : 5.13 instructions
|
| 273 |
+
Number of blocks executed : 2451466
|
| 274 |
+
Average weighted size : 4.08 instructions
|
| 275 |
+
Number of total instructions : 10000000
|
| 276 |
+
Number of fetched instruction : 10000000
|
| 277 |
+
========================================================
|
| 278 |
+
Scarab finished at Fri Jul 17 23:07:28 2026
|
| 279 |
+
|
sssp_facebook/fingerprint/run_3/PARAMS.in
ADDED
|
@@ -0,0 +1,268 @@
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|
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|
|
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|
|
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|
|
|
|
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|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
|
|
|
|
|
|
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|
|
|
|
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|
|
|
|
|
|
|
|
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|
|
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|
|
|
|
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|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# File : PARAMS.golden_cove
|
| 2 |
+
# Date : 02/27/25
|
| 3 |
+
# Description : Golden Cove Configuration
|
| 4 |
+
# Author : Surim Oh <[email protected]>
|
| 5 |
+
#
|
| 6 |
+
# Based on documentation found here:
|
| 7 |
+
# https://en.wikipedia.org/wiki/Golden_Cove
|
| 8 |
+
# https://en.wikichip.org/wiki/intel/microarchitectures/golden_cove
|
| 9 |
+
# https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/3
|
| 10 |
+
|
| 11 |
+
## Simulation Parameters
|
| 12 |
+
--mode full
|
| 13 |
+
--model cmp
|
| 14 |
+
--sim_limit none
|
| 15 |
+
|
| 16 |
+
## Core Parameters
|
| 17 |
+
|
| 18 |
+
# Femptoseconds, 3.2GHz, used for energy estimates.
|
| 19 |
+
--chip_cycle_time 312500
|
| 20 |
+
|
| 21 |
+
|
| 22 |
+
### Fetch Stage
|
| 23 |
+
--fetch_off_path_ops 1
|
| 24 |
+
|
| 25 |
+
#### ICache
|
| 26 |
+
--icache_size 32768
|
| 27 |
+
--icache_assoc 8
|
| 28 |
+
--icache_line_size 64
|
| 29 |
+
|
| 30 |
+
### Uop Cache
|
| 31 |
+
# inclusive w/ L1i
|
| 32 |
+
--uop_cache_enable 1
|
| 33 |
+
--uop_cache_width 8
|
| 34 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 35 |
+
--uop_cache_assoc 8
|
| 36 |
+
--iprf_on_uop_cache_hit 1
|
| 37 |
+
|
| 38 |
+
### Branch Predictor
|
| 39 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 40 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 41 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 42 |
+
--bp_mech tage64k
|
| 43 |
+
|
| 44 |
+
|
| 45 |
+
#### BTB
|
| 46 |
+
|
| 47 |
+
# TODO
|
| 48 |
+
# multi-level BTB
|
| 49 |
+
# 128 entry L0 BTB
|
| 50 |
+
# 6144 entry L1 BTB
|
| 51 |
+
# 12888 entry L2 BTB
|
| 52 |
+
# ~2 entry Return Stack
|
| 53 |
+
# roughly 2x8192 for now
|
| 54 |
+
# BTB model to use.
|
| 55 |
+
--btb_mech generic
|
| 56 |
+
--btb_entries 12288
|
| 57 |
+
--btb_assoc 4
|
| 58 |
+
--btb_main_latency 3
|
| 59 |
+
--btb_l0_present 1
|
| 60 |
+
--btb_l0_entries 128
|
| 61 |
+
--btb_l0_assoc 4
|
| 62 |
+
--btb_l0_latency 1
|
| 63 |
+
--btb_l1_present 1
|
| 64 |
+
--btb_l1_entries 6144
|
| 65 |
+
--btb_l1_assoc 4
|
| 66 |
+
--btb_l1_latency 2
|
| 67 |
+
|
| 68 |
+
# Allow the BTB to be updated by off path ops.
|
| 69 |
+
--btb_off_path_writes 1
|
| 70 |
+
|
| 71 |
+
# NT branches are not inserted in BTB, but do not trigger resteer
|
| 72 |
+
# since we continue without a control flow change
|
| 73 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 74 |
+
|
| 75 |
+
#### CRS
|
| 76 |
+
|
| 77 |
+
# Enable return stack
|
| 78 |
+
--enable_crs 1
|
| 79 |
+
--crs_entries 128
|
| 80 |
+
--crs_realistic 1
|
| 81 |
+
|
| 82 |
+
### iBP
|
| 83 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 84 |
+
--ibtb_mech tc_tagged
|
| 85 |
+
# iBTB Model. tc_tagless, tc_tagged, tc_hybrid.
|
| 86 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 87 |
+
--tc_entries 4096
|
| 88 |
+
--tc_assoc 4
|
| 89 |
+
|
| 90 |
+
### Decode Stage
|
| 91 |
+
--decode_width 6
|
| 92 |
+
--decode_cycles 5
|
| 93 |
+
|
| 94 |
+
### Instruction Decode Queue
|
| 95 |
+
--idq_size 144
|
| 96 |
+
|
| 97 |
+
### Map Stage
|
| 98 |
+
--map_cycles 5
|
| 99 |
+
|
| 100 |
+
# register renaming table
|
| 101 |
+
--reg_renaming_scheme 1
|
| 102 |
+
--reg_table_integer_physical_size 280
|
| 103 |
+
--reg_table_vector_physical_size 332
|
| 104 |
+
|
| 105 |
+
### Issue Stage
|
| 106 |
+
|
| 107 |
+
# Max number of instructions to be renamed, and issued per cycle.
|
| 108 |
+
--issue_width 6
|
| 109 |
+
|
| 110 |
+
--rs_fill_width 0
|
| 111 |
+
# rs_sizes ~205 in total, and they are split into three different reservation stations (RS1, RS2, RS3) where each has 97, 70, 38 entries respectively
|
| 112 |
+
# original architecture
|
| 113 |
+
# RS1 connected to port 0,1,5,6,10
|
| 114 |
+
# RS2 connected to port 2,3,11
|
| 115 |
+
# RS3 connected to port 7,8,4,9
|
| 116 |
+
# scarab does not split ST AGU port and ST port, merge them
|
| 117 |
+
# adjusted architecture to scarab ST AGU (port 4 and 9 removed. rs_size reduced to 186 from 205)
|
| 118 |
+
# RS1 connected to port 0,1,4,5,8
|
| 119 |
+
# RS2 connected to port 2,3,9
|
| 120 |
+
# RS3 connected to port 6,7 (port 4,9 removed, entries reduced to 19 from 38)
|
| 121 |
+
--rs_sizes 97 70 19
|
| 122 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 123 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 124 |
+
|
| 125 |
+
### Exec Stage
|
| 126 |
+
|
| 127 |
+
### DCache
|
| 128 |
+
--dcache_size 49152
|
| 129 |
+
--dcache_read_ports 1
|
| 130 |
+
--dcache_write_ports 1
|
| 131 |
+
--dcache_banks 8
|
| 132 |
+
--dcache_assoc 12
|
| 133 |
+
--dcache_line_size 64
|
| 134 |
+
--dcache_cycles 5
|
| 135 |
+
|
| 136 |
+
### Reorder/Retire Stage
|
| 137 |
+
|
| 138 |
+
# Max number of instructions to be retired per cycle.
|
| 139 |
+
--node_ret_width 8
|
| 140 |
+
--node_table_size 512
|
| 141 |
+
|
| 142 |
+
# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does
|
| 143 |
+
--stores_do_not_block_window 1
|
| 144 |
+
|
| 145 |
+
# TODO: confirm what this knob does
|
| 146 |
+
--prefs_do_not_block_window 1
|
| 147 |
+
|
| 148 |
+
|
| 149 |
+
## Uncore
|
| 150 |
+
|
| 151 |
+
### Mid-level cache
|
| 152 |
+
|
| 153 |
+
# Enable use of a midlevel cache between i/d and L1
|
| 154 |
+
# client 1.25 MiB (1310720 bytes) per core, 8-way, 15 cycles
|
| 155 |
+
# server 2 MiB (2097000 bytes) per core, 8-way, 16 cycles
|
| 156 |
+
--mlc_present 1
|
| 157 |
+
--mlc_size 2097000
|
| 158 |
+
--mlc_assoc 8
|
| 159 |
+
--mlc_cycles 16
|
| 160 |
+
|
| 161 |
+
|
| 162 |
+
### LLC
|
| 163 |
+
# 3 MiB per core, 16-way
|
| 164 |
+
--l1_size 3145728
|
| 165 |
+
--l1_banks 8
|
| 166 |
+
--l1_cycles 36 // just a guess
|
| 167 |
+
--l1_assoc 16
|
| 168 |
+
--l1_line_size 64
|
| 169 |
+
--l1_interleave_factor 64
|
| 170 |
+
|
| 171 |
+
|
| 172 |
+
### prefetcher
|
| 173 |
+
# Kept same as Kaby Lake
|
| 174 |
+
--pref_framework_on 1
|
| 175 |
+
--pref_stream_on 1
|
| 176 |
+
--pref_train_on_pref_misses 0
|
| 177 |
+
--pref_oracle_train 0
|
| 178 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 179 |
+
|
| 180 |
+
--stream_length 64
|
| 181 |
+
--stream_prefetch_n 4
|
| 182 |
+
--stream_start_dis 1
|
| 183 |
+
--stream_train_num 4
|
| 184 |
+
--stream_create_on_dc_miss 0
|
| 185 |
+
--stream_create_on_l1_miss 1
|
| 186 |
+
|
| 187 |
+
--pref_throttlefb_on=1
|
| 188 |
+
--pref_acc_thresh_1=0.75
|
| 189 |
+
--pref_acc_thresh_2=0.4
|
| 190 |
+
--pref_acc_thresh_3=0.4
|
| 191 |
+
--pref_timely_thresh=0.01
|
| 192 |
+
--pref_polpf_thresh=0.005
|
| 193 |
+
--pref_update_interval=8192
|
| 194 |
+
|
| 195 |
+
--mem_req_buffer_pref_watermark 4
|
| 196 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 197 |
+
|
| 198 |
+
### Memory
|
| 199 |
+
# Kept same as Kaby Lake
|
| 200 |
+
--addr_translation random
|
| 201 |
+
|
| 202 |
+
--mem_priority_ifetch 0
|
| 203 |
+
--mem_priority_dfetch 1
|
| 204 |
+
--mem_priority_dstore 2
|
| 205 |
+
--mem_priority_iprf 3
|
| 206 |
+
--mem_priority_dprf 4
|
| 207 |
+
--mem_priority_wb 5
|
| 208 |
+
--mem_priority_wb_nodirty 5
|
| 209 |
+
|
| 210 |
+
--mem_req_buffer_entries 32
|
| 211 |
+
--bus_width_in_bytes 8
|
| 212 |
+
|
| 213 |
+
--ramulator_standard DDR4
|
| 214 |
+
--ramulator_speed DDR4_2400R
|
| 215 |
+
--ramulator_org DDR4_8Gb_x8
|
| 216 |
+
--ramulator_channels 1
|
| 217 |
+
--ramulator_ranks 1
|
| 218 |
+
--ramulator_bankgroups 4
|
| 219 |
+
--ramulator_banks 4
|
| 220 |
+
--ramulator_chip_width 8
|
| 221 |
+
--ramulator_rows 65536
|
| 222 |
+
--ramulator_cols 1024
|
| 223 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 224 |
+
--ramulator_readq_entries 32
|
| 225 |
+
--ramulator_writeq_entries 32
|
| 226 |
+
--ramulator_record_cmd_trace FALSE
|
| 227 |
+
--ramulator_print_cmd_trace FALSE
|
| 228 |
+
--ramulator_tCK 833333
|
| 229 |
+
--ramulator_tCL 16
|
| 230 |
+
--ramulator_tCCD 6
|
| 231 |
+
--ramulator_tCCDS 4
|
| 232 |
+
--ramulator_tCCDL 6
|
| 233 |
+
--ramulator_tCWL 12
|
| 234 |
+
--ramulator_tBL 4
|
| 235 |
+
--ramulator_tWTR 9
|
| 236 |
+
--ramulator_tWTRS 3
|
| 237 |
+
--ramulator_tWTRL 9
|
| 238 |
+
--ramulator_tRP 16
|
| 239 |
+
--ramulator_tRPpb 16
|
| 240 |
+
--ramulator_tRPab 16
|
| 241 |
+
--ramulator_tRCD 16
|
| 242 |
+
--ramulator_tRCDR 16
|
| 243 |
+
--ramulator_tRCDW 16
|
| 244 |
+
--ramulator_tRAS 39
|
| 245 |
+
--dram_tech_in_nm 32
|
| 246 |
+
|
| 247 |
+
## Other
|
| 248 |
+
|
| 249 |
+
|
| 250 |
+
### Debug
|
| 251 |
+
--debug_inst_start 0
|
| 252 |
+
--debug_inst_stop -1
|
| 253 |
+
--debug_cycle_start 0
|
| 254 |
+
--debug_cycle_stop -1
|
| 255 |
+
|
| 256 |
+
|
| 257 |
+
## Stats and Params
|
| 258 |
+
--dump_params 1
|
| 259 |
+
--dump_stats 1
|
| 260 |
+
--dump_trace 0
|
| 261 |
+
|
| 262 |
+
####################################
|
| 263 |
+
--set_off_path_confirmed 1
|
| 264 |
+
|
| 265 |
+
--order_beyond_bus 1
|
| 266 |
+
|
| 267 |
+
--mem_ooo_stores 1
|
| 268 |
+
--mem_obey_store_dep 1
|
sssp_facebook/fingerprint/run_3/PARAMS.out
ADDED
|
@@ -0,0 +1,1102 @@
|
|
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|
| 1 |
+
--mode trace_bbv_distributed
|
| 2 |
+
--model cmp
|
| 3 |
+
--frontend memtrace
|
| 4 |
+
--sim_limit none
|
| 5 |
+
--memtrace_roi_begin 30000001
|
| 6 |
+
--memtrace_roi_end 40000000
|
| 7 |
+
--use_fetched_count 1
|
| 8 |
+
--dump_params 1
|
| 9 |
+
--dump_stats 1
|
| 10 |
+
--dump_trace 0
|
| 11 |
+
--trace_bbv_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.3
|
| 12 |
+
--trace_footprint_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.3
|
| 13 |
+
--segment_instr_count 10000000
|
| 14 |
+
--mlc_present 1
|
| 15 |
+
--mlc_size 2097000
|
| 16 |
+
--mlc_assoc 8
|
| 17 |
+
--mlc_cycles 16
|
| 18 |
+
--l1_size 3145728
|
| 19 |
+
--l1_assoc 16
|
| 20 |
+
--l1_line_size 64
|
| 21 |
+
--l1_cycles 36 // just a guess
|
| 22 |
+
--l1_banks 8
|
| 23 |
+
--l1_interleave_factor 64
|
| 24 |
+
--addr_translation random
|
| 25 |
+
--icache_size 32768
|
| 26 |
+
--icache_assoc 8
|
| 27 |
+
--icache_line_size 64
|
| 28 |
+
--uop_cache_enable 1
|
| 29 |
+
--uop_cache_width 8
|
| 30 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 31 |
+
--uop_cache_assoc 8
|
| 32 |
+
--iprf_on_uop_cache_hit 1
|
| 33 |
+
--dcache_size 49152
|
| 34 |
+
--dcache_assoc 12
|
| 35 |
+
--dcache_line_size 64
|
| 36 |
+
--dcache_cycles 5
|
| 37 |
+
--dcache_read_ports 1
|
| 38 |
+
--dcache_write_ports 1
|
| 39 |
+
--dcache_banks 8
|
| 40 |
+
--mem_ooo_stores 1
|
| 41 |
+
--mem_obey_store_dep 1
|
| 42 |
+
--mem_req_buffer_entries 32
|
| 43 |
+
--mem_priority_ifetch 0
|
| 44 |
+
--mem_priority_dfetch 1
|
| 45 |
+
--mem_priority_dstore 2
|
| 46 |
+
--mem_priority_iprf 3
|
| 47 |
+
--mem_priority_dprf 4
|
| 48 |
+
--mem_priority_wb 5
|
| 49 |
+
--mem_priority_wb_nodirty 5
|
| 50 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 51 |
+
--mem_req_buffer_pref_watermark 4
|
| 52 |
+
--order_beyond_bus 1
|
| 53 |
+
--set_off_path_confirmed 1
|
| 54 |
+
--ramulator_standard DDR4
|
| 55 |
+
--ramulator_speed DDR4_2400R
|
| 56 |
+
--ramulator_org DDR4_8Gb_x8
|
| 57 |
+
--ramulator_channels 1
|
| 58 |
+
--ramulator_ranks 1
|
| 59 |
+
--ramulator_bankgroups 4
|
| 60 |
+
--ramulator_banks 4
|
| 61 |
+
--ramulator_chip_width 8
|
| 62 |
+
--bus_width_in_bytes 8
|
| 63 |
+
--ramulator_rows 65536
|
| 64 |
+
--ramulator_cols 1024
|
| 65 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 66 |
+
--ramulator_readq_entries 32
|
| 67 |
+
--ramulator_writeq_entries 32
|
| 68 |
+
--ramulator_record_cmd_trace FALSE
|
| 69 |
+
--ramulator_print_cmd_trace FALSE
|
| 70 |
+
--ramulator_tCK 833333
|
| 71 |
+
--ramulator_tCL 16
|
| 72 |
+
--ramulator_tCCD 6
|
| 73 |
+
--ramulator_tCCDS 4
|
| 74 |
+
--ramulator_tCCDL 6
|
| 75 |
+
--ramulator_tCWL 12
|
| 76 |
+
--ramulator_tBL 4
|
| 77 |
+
--ramulator_tWTR 9
|
| 78 |
+
--ramulator_tWTRS 3
|
| 79 |
+
--ramulator_tWTRL 9
|
| 80 |
+
--ramulator_tRP 16
|
| 81 |
+
--ramulator_tRPpb 16
|
| 82 |
+
--ramulator_tRPab 16
|
| 83 |
+
--ramulator_tRCD 16
|
| 84 |
+
--ramulator_tRCDR 16
|
| 85 |
+
--ramulator_tRCDW 16
|
| 86 |
+
--ramulator_tRAS 39
|
| 87 |
+
--dram_tech_in_nm 32
|
| 88 |
+
--chip_cycle_time 312500
|
| 89 |
+
--issue_width 6
|
| 90 |
+
--rs_fill_width 0
|
| 91 |
+
--node_table_size 512
|
| 92 |
+
--node_ret_width 8
|
| 93 |
+
--decode_width 6
|
| 94 |
+
--idq_size 144
|
| 95 |
+
--reg_renaming_scheme 1
|
| 96 |
+
--reg_table_integer_physical_size 280
|
| 97 |
+
--reg_table_vector_physical_size 332
|
| 98 |
+
--rs_sizes 97 70 19
|
| 99 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 100 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 101 |
+
--decode_cycles 5
|
| 102 |
+
--map_cycles 5
|
| 103 |
+
--fetch_off_path_ops 1
|
| 104 |
+
--stores_do_not_block_window 1
|
| 105 |
+
--prefs_do_not_block_window 1
|
| 106 |
+
--cbp_trace_r0 /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 107 |
+
--debug_cycle_start 0
|
| 108 |
+
--debug_cycle_stop -1
|
| 109 |
+
--debug_inst_start 0
|
| 110 |
+
--debug_inst_stop -1
|
| 111 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 112 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 113 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 114 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 115 |
+
--bp_mech tage64k
|
| 116 |
+
--btb_mech generic
|
| 117 |
+
--btb_entries 12288
|
| 118 |
+
--btb_assoc 4
|
| 119 |
+
--btb_off_path_writes 1
|
| 120 |
+
--btb_main_latency 3
|
| 121 |
+
--btb_l0_present 1
|
| 122 |
+
--btb_l0_entries 128
|
| 123 |
+
--btb_l0_assoc 4
|
| 124 |
+
--btb_l0_latency 1
|
| 125 |
+
--btb_l1_present 1
|
| 126 |
+
--btb_l1_entries 6144
|
| 127 |
+
--btb_l1_assoc 4
|
| 128 |
+
--btb_l1_latency 2
|
| 129 |
+
--enable_crs 1
|
| 130 |
+
--crs_entries 128
|
| 131 |
+
--crs_realistic 1
|
| 132 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 133 |
+
--ibtb_mech tc_tagged
|
| 134 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 135 |
+
--tc_entries 4096
|
| 136 |
+
--tc_assoc 4
|
| 137 |
+
--pref_stream_on 1
|
| 138 |
+
--stream_prefetch_n 4
|
| 139 |
+
--stream_start_dis 1
|
| 140 |
+
--stream_length 64
|
| 141 |
+
--stream_train_num 4
|
| 142 |
+
--stream_create_on_dc_miss 0
|
| 143 |
+
--stream_create_on_l1_miss 1
|
| 144 |
+
--pref_framework_on 1
|
| 145 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 146 |
+
--pref_train_on_pref_misses 0
|
| 147 |
+
--pref_oracle_train_on 0
|
| 148 |
+
--pref_throttlefb_on 1
|
| 149 |
+
--pref_acc_thresh_1 0.75
|
| 150 |
+
--pref_acc_thresh_2 0.4
|
| 151 |
+
--pref_acc_thresh_3 0.4
|
| 152 |
+
--pref_update_interval 8192
|
| 153 |
+
--pref_timely_thresh 0.01
|
| 154 |
+
--pref_polpf_thresh 0.005
|
| 155 |
+
1 1 1 1 1 1 1
|
| 156 |
+
|
| 157 |
+
--- Cut out everything below to use this file as PARAMS.in ---
|
| 158 |
+
|
| 159 |
+
Parameter status at compile time and values supplied on the command line:
|
| 160 |
+
|
| 161 |
+
SIM_MODE 0 trace_bbv_distributed
|
| 162 |
+
SIM_MODEL 0 cmp
|
| 163 |
+
FRONTEND FE_PIN_EXEC_DRIVEN memtrace
|
| 164 |
+
INST_LIMIT NULL
|
| 165 |
+
SIM_LIMIT "none" none
|
| 166 |
+
FORWARD_PROGRESS_LIMIT 100000000
|
| 167 |
+
FORWARD_PROGRESS_INTERVAL 10000
|
| 168 |
+
FAST_FORWARD 0
|
| 169 |
+
FAST_FORWARD_TRACE_INS 0
|
| 170 |
+
FAST_FORWARD_UNTIL_ADDR 0
|
| 171 |
+
MEMTRACE_ROI_BEGIN 0 30000001
|
| 172 |
+
MEMTRACE_ROI_END 0 40000000
|
| 173 |
+
FULL_WARMUP 0
|
| 174 |
+
WARMUP 0
|
| 175 |
+
HEARTBEAT_INTERVAL 1000000
|
| 176 |
+
NUM_HEARTBEATS 0
|
| 177 |
+
USE_FETCHED_COUNT FALSE 1
|
| 178 |
+
PERIODIC_DUMP FALSE
|
| 179 |
+
FILE_TAG ""
|
| 180 |
+
OUTPUT_DIR "."
|
| 181 |
+
STATUS_FILE NULL
|
| 182 |
+
BINDIR NULL
|
| 183 |
+
DUMP_PARAMS TRUE 1
|
| 184 |
+
DUMP_STATS TRUE 1
|
| 185 |
+
DUMP_TRACE FALSE 0
|
| 186 |
+
CLEAR_STATS "never"
|
| 187 |
+
STATS_TO_TRACE NULL
|
| 188 |
+
STAT_TRACE_FILE "stats.trace"
|
| 189 |
+
STAT_TRACE_INTERVAL "i:100000"
|
| 190 |
+
PIPEVIEW FALSE
|
| 191 |
+
PIPEVIEW_FILE "pipeview"
|
| 192 |
+
MEMVIEW FALSE
|
| 193 |
+
MEMVIEW_FILE "memview.out"
|
| 194 |
+
MEMVIEW_START "never"
|
| 195 |
+
INST_HASH_TABLE_SIZE 524288 const
|
| 196 |
+
STDOUT_FILE NULL
|
| 197 |
+
STDERR_FILE NULL
|
| 198 |
+
PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp"
|
| 199 |
+
PRINT_PID FALSE
|
| 200 |
+
USE_UNSURE_FREE_LISTS FALSE
|
| 201 |
+
OPTIMIZER2_MAX_NUM_SLAVES 64
|
| 202 |
+
OPTIMIZER2_PERFECT_MEMORYLESS FALSE
|
| 203 |
+
EXIT_COND 0
|
| 204 |
+
NUM_NOPS 0
|
| 205 |
+
NOPS_BB_START 0x5000000
|
| 206 |
+
IGNORE_BAR_FETCH FALSE
|
| 207 |
+
TRACE_BBV_OUTPUT NULL /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.3
|
| 208 |
+
TRACE_FOOTPRINT_OUTPUT "" /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.3
|
| 209 |
+
SEGMENT_INSTR_COUNT 0 10000000
|
| 210 |
+
ENABLE_SWPRF FALSE
|
| 211 |
+
MLC_PRESENT FALSE 1
|
| 212 |
+
MLC_SIZE (512 * 1024) 2097000
|
| 213 |
+
MLC_ASSOC 4 8
|
| 214 |
+
MLC_LINE_SIZE 64
|
| 215 |
+
MLC_CYCLES 12 16
|
| 216 |
+
PERFECT_MLC FALSE
|
| 217 |
+
MLC_READ_PORTS 1
|
| 218 |
+
MLC_WRITE_PORTS 1
|
| 219 |
+
MLC_BANKS 8
|
| 220 |
+
MLC_INTERLEAVE_FACTOR 64
|
| 221 |
+
MLC_CACHE_REPL_POLICY 0
|
| 222 |
+
MLC_WRITE_THROUGH FALSE
|
| 223 |
+
PREFETCH_UPDATE_LRU_MLC TRUE
|
| 224 |
+
FORCE_L1_MISS FALSE
|
| 225 |
+
L1_SIZE (4 * 1024 * 1024) 3145728
|
| 226 |
+
L1_ASSOC 8 16
|
| 227 |
+
L1_LINE_SIZE 64 64
|
| 228 |
+
L1_CYCLES 24 36 // just a guess
|
| 229 |
+
PERFECT_L1 FALSE
|
| 230 |
+
PRIVATE_L1 FALSE
|
| 231 |
+
L1_READ_PORTS 1
|
| 232 |
+
L1_WRITE_PORTS 1
|
| 233 |
+
L1_BANKS 8 8
|
| 234 |
+
L1_INTERLEAVE_FACTOR 64 64
|
| 235 |
+
L1_CACHE_REPL_POLICY 0
|
| 236 |
+
L1_WRITE_THROUGH FALSE
|
| 237 |
+
L1_IGNORE_WB FALSE
|
| 238 |
+
L1_USE_CORE_FREQ FALSE
|
| 239 |
+
MARK_L1_MISSES TRUE
|
| 240 |
+
PREFETCH_UPDATE_LRU_L1 TRUE
|
| 241 |
+
MEMORY_RANDOM_ADDR FALSE
|
| 242 |
+
VA_PAGE_SIZE_BYTES 4096
|
| 243 |
+
NUM_ADDR_NON_SIGN_EXTEND_BITS 48
|
| 244 |
+
ADDR_TRANSLATION 0 random
|
| 245 |
+
CONSTANT_MEMORY_LATENCY FALSE
|
| 246 |
+
MEMORY_CYCLES 100
|
| 247 |
+
STALL_MEM_REQS_ONLY FALSE
|
| 248 |
+
ICACHE_SIZE (64 * 1024) 32768
|
| 249 |
+
ICACHE_ASSOC 4 8
|
| 250 |
+
ICACHE_LINE_SIZE 64 64
|
| 251 |
+
PERFECT_ICACHE FALSE
|
| 252 |
+
ICACHE_READ_PORTS 1
|
| 253 |
+
ICACHE_WRITE_PORTS 1
|
| 254 |
+
ICACHE_BANKS 8
|
| 255 |
+
ICACHE_REPL 0
|
| 256 |
+
UOP_CACHE_ENABLE 1 1
|
| 257 |
+
UOP_CACHE_WIDTH 6 8
|
| 258 |
+
ALWAYS_LOOKUP_ICACHE 0
|
| 259 |
+
UOP_CACHE_INSERT_ONLY_ONPATH FALSE
|
| 260 |
+
UOP_CACHE_READ_PORTS 1
|
| 261 |
+
UOP_CACHE_LINES 384 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 262 |
+
UOP_CACHE_ASSOC 8 8
|
| 263 |
+
UOP_CACHE_MAX_IMM_DISP_LINE 4
|
| 264 |
+
IPRF_ON_UOP_CACHE_HIT FALSE 1
|
| 265 |
+
UOP_CACHE_REPL 0
|
| 266 |
+
PRIORITY_LINE_STICKINESS_PERCENT 50
|
| 267 |
+
PW_PRIORITY_LIST_FILEPATH "pw_priority_list.csv"
|
| 268 |
+
NUM_PRIORITY_PWS 10
|
| 269 |
+
PRIORITIZE_PWS_AFTER_FIRST_STICKY_UNTIL_BACKEND_STALL FALSE
|
| 270 |
+
NO_REPL_AFTER_QUEUE_SIZE 0
|
| 271 |
+
FDIP_UC_SIZE 0
|
| 272 |
+
FDIP_UC_ASSOC 4
|
| 273 |
+
FDIP_UC_INSERT_REPLPOL 0
|
| 274 |
+
MAP_STAGE_CONSUME_FROM_ICACHE_AND_UOC_SAME_CYCLE TRUE
|
| 275 |
+
UOP_QUEUE_LENGTH 7
|
| 276 |
+
DCACHE_SIZE (64 * 1024) 49152
|
| 277 |
+
DCACHE_ASSOC 1 12
|
| 278 |
+
DCACHE_LINE_SIZE 64 64
|
| 279 |
+
DCACHE_CYCLES 2 5
|
| 280 |
+
PERFECT_DCACHE FALSE
|
| 281 |
+
DCACHE_READ_PORTS 8 1
|
| 282 |
+
DCACHE_WRITE_PORTS 1 1
|
| 283 |
+
DCACHE_BANKS 1 8
|
| 284 |
+
DCACHE_INTERLEAVE_FACTOR 4
|
| 285 |
+
DCACHE_REPL 0
|
| 286 |
+
DCACHE_REPL_PREF_THRESH 1
|
| 287 |
+
MEM_OOO_STORES TRUE 1
|
| 288 |
+
MEM_OBEY_STORE_DEP TRUE 1
|
| 289 |
+
PREF_INSERT_LRU FALSE
|
| 290 |
+
PREF_INSERT_MIDDLE FALSE
|
| 291 |
+
PREF_INSERT_LOWQTR FALSE
|
| 292 |
+
PREF_INSERT_DYNACC FALSE
|
| 293 |
+
MEM_REQ_BUFFER_ENTRIES 32 32
|
| 294 |
+
PRIVATE_MSHR_ON TRUE
|
| 295 |
+
MEM_PRIORITY_IFETCH 0 0
|
| 296 |
+
MEM_PRIORITY_DFETCH 0 1
|
| 297 |
+
MEM_PRIORITY_DSTORE 0 2
|
| 298 |
+
MEM_PRIORITY_IPRF 9 3
|
| 299 |
+
MEM_PRIORITY_UOCPRF 9
|
| 300 |
+
MEM_PRIORITY_FDIPPRFON 8
|
| 301 |
+
MEM_PRIORITY_FDIPPRFOFF 9
|
| 302 |
+
MEM_PRIORITY_DPRF 10 4
|
| 303 |
+
MEM_PRIORITY_WB 0 5
|
| 304 |
+
MEM_PRIORITY_WB_NODIRTY 0 5
|
| 305 |
+
PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1
|
| 306 |
+
MEM_REQ_BUFFER_PREF_WATERMARK 0 4
|
| 307 |
+
MEM_REQ_BUFFER_WB_VALVE 2
|
| 308 |
+
MEM_L1_FILL_QUEUE_ENTRIES 32
|
| 309 |
+
MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE
|
| 310 |
+
MEM_MEM_QUEUE_PARTITION_ENABLE FALSE
|
| 311 |
+
MEM_BUS_OUT_QUEUE_AS_FIFO TRUE
|
| 312 |
+
OLDEST_FIRST_TO_MEM_QUEUE TRUE
|
| 313 |
+
ROUND_ROBIN_TO_MEM_QUEUE FALSE
|
| 314 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE FALSE
|
| 315 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0
|
| 316 |
+
L1_CYCLE_TIME 312500
|
| 317 |
+
MLCQ_TO_L1Q_TRANSFER_LATENCY 1
|
| 318 |
+
L1Q_TO_FSB_TRANSFER_LATENCY 1
|
| 319 |
+
PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE
|
| 320 |
+
KICKOUT_PREFETCHES FALSE
|
| 321 |
+
KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE
|
| 322 |
+
KICKOUT_OLDEST_PREFETCH FALSE
|
| 323 |
+
KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE
|
| 324 |
+
ORDER_BEYOND_BUS FALSE 1
|
| 325 |
+
ALL_FIFO_QUEUES FALSE
|
| 326 |
+
QUEUE_MLC_SIZE 0
|
| 327 |
+
QUEUE_L1_SIZE 0
|
| 328 |
+
QUEUE_BUS_OUT_SIZE 0
|
| 329 |
+
QUEUE_CORE_FILL_SIZE 0
|
| 330 |
+
ALLOW_TYPE_MATCHES FALSE
|
| 331 |
+
STREAM_PREFETCH_ON FALSE
|
| 332 |
+
DC_PREF_CACHE_ENABLE FALSE
|
| 333 |
+
DC_PREF_CACHE_CYCLE 0
|
| 334 |
+
PREF_INSERT_DCACHE_IMM TRUE
|
| 335 |
+
DC_PREF_CACHE_SIZE (64 * 1024)
|
| 336 |
+
DC_PREF_CACHE_ASSOC 4
|
| 337 |
+
DC_PREF_ONLY_L1HIT FALSE
|
| 338 |
+
PREF_CACHE_USE_RDY_CYCLE FALSE
|
| 339 |
+
IC_PREF_CACHE_ENABLE FALSE
|
| 340 |
+
IC_PREF_CACHE_SIZE (64 * 1024)
|
| 341 |
+
IC_PREF_CACHE_ASSOC 4
|
| 342 |
+
L1_PREF_CACHE_ENABLE FALSE
|
| 343 |
+
L1_PREF_CACHE_SIZE (1024 * 1024)
|
| 344 |
+
L1_PREF_CACHE_ASSOC 8
|
| 345 |
+
SET_OFF_PATH_CONFIRMED FALSE 1
|
| 346 |
+
USE_CONFIRMED_OFF FALSE
|
| 347 |
+
PREFCACHE_MOVE_OFFPATH FALSE
|
| 348 |
+
CACHE_STAT_ENABLE FALSE
|
| 349 |
+
PREF_DCACHE_HIT_FILL_L1 TRUE
|
| 350 |
+
PREF_ICACHE_HIT_FILL_L1 TRUE
|
| 351 |
+
CRITICAL_ACCESS_PLOT_ENABLE FALSE
|
| 352 |
+
CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat"
|
| 353 |
+
ROUND_ROBIN_TO_L1 FALSE
|
| 354 |
+
PREF_I_TOGETHER FALSE
|
| 355 |
+
ONE_MORE_CACHE_LINE_ENABLE FALSE
|
| 356 |
+
L1_STATIC_PARTITION_ENABLE 0
|
| 357 |
+
L1_STATIC_PARTITION NULL
|
| 358 |
+
L1_DYNAMIC_PARTITION_ENABLE FALSE
|
| 359 |
+
L1_DYNAMIC_PARTITION_POLICY 0
|
| 360 |
+
PARTITION_UMON_DSS_PREF_ENABLE FALSE
|
| 361 |
+
L1_CACHE_HIT_POSITION_COLLECT FALSE
|
| 362 |
+
L1_PART_ON FALSE
|
| 363 |
+
L1_PART_TRIGGER "c:1000000"
|
| 364 |
+
L1_PART_START "t:0"
|
| 365 |
+
L1_PART_WARMUP FALSE
|
| 366 |
+
L1_PART_SHADOW_WARMUP FALSE
|
| 367 |
+
L1_PART_METRIC 0
|
| 368 |
+
L1_PART_SEARCH 0
|
| 369 |
+
L1_PART_USE_STALLING TRUE
|
| 370 |
+
L1_PART_FILL_DELAY 0
|
| 371 |
+
L1_SHADOW_TAGS_MODULO 1
|
| 372 |
+
HIER_MSHR_ON FALSE
|
| 373 |
+
PERF_PRED_ENABLE FALSE
|
| 374 |
+
PERF_PRED_MECH PERF_PRED_CP
|
| 375 |
+
PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY
|
| 376 |
+
PERF_PRED_COUNT_ALL FALSE
|
| 377 |
+
PERF_PRED_COUNT_INST_MISSES TRUE
|
| 378 |
+
PERF_PRED_COUNT_PREFETCHES FALSE
|
| 379 |
+
PERF_PRED_COUNT_OFFPATH_REQS FALSE
|
| 380 |
+
PERF_PRED_COUNT_BW_REQS TRUE
|
| 381 |
+
PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE
|
| 382 |
+
PERF_PRED_SLACK_PERIOD_SIZE 32
|
| 383 |
+
PERF_PRED_REQS_FINISH_AT_FILL FALSE
|
| 384 |
+
PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE
|
| 385 |
+
PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE
|
| 386 |
+
DUMB_MODEL_AVG_REQ_DISTANCE 100
|
| 387 |
+
DUMB_MODEL_RANDOMIZE_DISTANCE FALSE
|
| 388 |
+
DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL
|
| 389 |
+
DUMB_MODEL_AVG_ROW_HITS 1
|
| 390 |
+
DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL
|
| 391 |
+
DUMB_MODEL_MLP 1
|
| 392 |
+
DUMB_MODEL_MLP_PER_CORE NULL
|
| 393 |
+
RAMULATOR_STANDARD "DDR4" DDR4
|
| 394 |
+
RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R
|
| 395 |
+
RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8
|
| 396 |
+
RAMULATOR_CHANNELS 1 1
|
| 397 |
+
RAMULATOR_RANKS 1 1
|
| 398 |
+
RAMULATOR_BANKGROUPS 4 4
|
| 399 |
+
RAMULATOR_BANKS 4 4
|
| 400 |
+
RAMULATOR_CHIP_WIDTH 8 8
|
| 401 |
+
BUS_WIDTH_IN_BYTES 8 8
|
| 402 |
+
RAMULATOR_ROWS 65536 65536
|
| 403 |
+
RAMULATOR_COLS 1024 1024
|
| 404 |
+
RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap
|
| 405 |
+
RAMULATOR_READQ_ENTRIES 32 32
|
| 406 |
+
RAMULATOR_WRITEQ_ENTRIES 32 32
|
| 407 |
+
RAMULATOR_REC_CMD_TRACE "off" FALSE
|
| 408 |
+
RAMULATOR_PRINT_CMD_TRACE "off" FALSE
|
| 409 |
+
RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on"
|
| 410 |
+
RAMULATOR_TCK 833333 833333
|
| 411 |
+
RAMULATOR_TCL 16 16
|
| 412 |
+
RAMULATOR_TCCD 6 6
|
| 413 |
+
RAMULATOR_TCCDS 4 4
|
| 414 |
+
RAMULATOR_TCCDL 6 6
|
| 415 |
+
RAMULATOR_TCWL 12 12
|
| 416 |
+
RAMULATOR_TBL 4 4
|
| 417 |
+
RAMULATOR_TWTR 9 9
|
| 418 |
+
RAMULATOR_TWTRS 3 3
|
| 419 |
+
RAMULATOR_TWTRL 9 9
|
| 420 |
+
RAMULATOR_TRP 16 16
|
| 421 |
+
RAMULATOR_TRPpb 16 16
|
| 422 |
+
RAMULATOR_TRPab 16 16
|
| 423 |
+
RAMULATOR_TRCD 16 16
|
| 424 |
+
RAMULATOR_TRCDR 16 16
|
| 425 |
+
RAMULATOR_TRCDW 16 16
|
| 426 |
+
RAMULATOR_TRAS 39 39
|
| 427 |
+
DRAM_TECH_IN_NM 32 32
|
| 428 |
+
DVFS_ON FALSE
|
| 429 |
+
DVFS_METRIC DVFS_METRIC_NUM_ELEMS
|
| 430 |
+
DVFS_CONFIGS NULL
|
| 431 |
+
DVFS_CONFIG_FILE NULL
|
| 432 |
+
DVFS_START "t:0"
|
| 433 |
+
DVFS_PERIOD "t:312500000000"
|
| 434 |
+
DVFS_LOG TRUE
|
| 435 |
+
DVFS_INDIVIDUAL_CORES FALSE
|
| 436 |
+
DVFS_CHIP_LEVEL FALSE
|
| 437 |
+
DVFS_STATIC NULL
|
| 438 |
+
DVFS_FORCE_CONFIG NULL
|
| 439 |
+
DVFS_REPLAY_CONFIG_TRACE NULL
|
| 440 |
+
DVFS_USE_ORACLE FALSE
|
| 441 |
+
DVFS_USE_BW_SHARING FALSE
|
| 442 |
+
DVFS_USE_DRAM_SHARING FALSE
|
| 443 |
+
DVFS_USE_STALL_TIME FALSE
|
| 444 |
+
DVFS_DRAM_SHARING_SOLVER_BIN NULL
|
| 445 |
+
DVFS_DRAM_SHARING_SOLVER_STRICT TRUE
|
| 446 |
+
DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95
|
| 447 |
+
DVFS_BW_SHARING_MAX_REQS 28.0
|
| 448 |
+
DVFS_BW_SHARING_MAX_RW_COST 0.25
|
| 449 |
+
DVFS_BW_SHARING_NO_PREF_STALL TRUE
|
| 450 |
+
DVFS_BW_SHARING_CRIT_STATS TRUE
|
| 451 |
+
DVFS_COUNT_L1_ACCESS_STALL FALSE
|
| 452 |
+
NUM_CORES 1
|
| 453 |
+
CHIP_CYCLE_TIME 312500 312500
|
| 454 |
+
CORE_0_CYCLE_TIME 312500
|
| 455 |
+
CORE_1_CYCLE_TIME 312500
|
| 456 |
+
CORE_2_CYCLE_TIME 312500
|
| 457 |
+
CORE_3_CYCLE_TIME 312500
|
| 458 |
+
CORE_4_CYCLE_TIME 312500
|
| 459 |
+
CORE_5_CYCLE_TIME 312500
|
| 460 |
+
CORE_6_CYCLE_TIME 312500
|
| 461 |
+
CORE_7_CYCLE_TIME 312500
|
| 462 |
+
CORE_8_CYCLE_TIME 312500
|
| 463 |
+
CORE_9_CYCLE_TIME 312500
|
| 464 |
+
CORE_10_CYCLE_TIME 312500
|
| 465 |
+
CORE_11_CYCLE_TIME 312500
|
| 466 |
+
CORE_12_CYCLE_TIME 312500
|
| 467 |
+
CORE_13_CYCLE_TIME 312500
|
| 468 |
+
CORE_14_CYCLE_TIME 312500
|
| 469 |
+
CORE_15_CYCLE_TIME 312500
|
| 470 |
+
CORE_16_CYCLE_TIME 312500
|
| 471 |
+
CORE_17_CYCLE_TIME 312500
|
| 472 |
+
CORE_18_CYCLE_TIME 312500
|
| 473 |
+
CORE_19_CYCLE_TIME 312500
|
| 474 |
+
CORE_20_CYCLE_TIME 312500
|
| 475 |
+
CORE_21_CYCLE_TIME 312500
|
| 476 |
+
CORE_22_CYCLE_TIME 312500
|
| 477 |
+
CORE_23_CYCLE_TIME 312500
|
| 478 |
+
CORE_24_CYCLE_TIME 312500
|
| 479 |
+
CORE_25_CYCLE_TIME 312500
|
| 480 |
+
CORE_26_CYCLE_TIME 312500
|
| 481 |
+
CORE_27_CYCLE_TIME 312500
|
| 482 |
+
CORE_28_CYCLE_TIME 312500
|
| 483 |
+
CORE_29_CYCLE_TIME 312500
|
| 484 |
+
CORE_30_CYCLE_TIME 312500
|
| 485 |
+
CORE_31_CYCLE_TIME 312500
|
| 486 |
+
CORE_32_CYCLE_TIME 312500
|
| 487 |
+
CORE_33_CYCLE_TIME 312500
|
| 488 |
+
CORE_34_CYCLE_TIME 312500
|
| 489 |
+
CORE_35_CYCLE_TIME 312500
|
| 490 |
+
CORE_36_CYCLE_TIME 312500
|
| 491 |
+
CORE_37_CYCLE_TIME 312500
|
| 492 |
+
CORE_38_CYCLE_TIME 312500
|
| 493 |
+
CORE_39_CYCLE_TIME 312500
|
| 494 |
+
CORE_40_CYCLE_TIME 312500
|
| 495 |
+
CORE_41_CYCLE_TIME 312500
|
| 496 |
+
CORE_42_CYCLE_TIME 312500
|
| 497 |
+
CORE_43_CYCLE_TIME 312500
|
| 498 |
+
CORE_44_CYCLE_TIME 312500
|
| 499 |
+
CORE_45_CYCLE_TIME 312500
|
| 500 |
+
CORE_46_CYCLE_TIME 312500
|
| 501 |
+
CORE_47_CYCLE_TIME 312500
|
| 502 |
+
CORE_48_CYCLE_TIME 312500
|
| 503 |
+
CORE_49_CYCLE_TIME 312500
|
| 504 |
+
CORE_50_CYCLE_TIME 312500
|
| 505 |
+
CORE_51_CYCLE_TIME 312500
|
| 506 |
+
CORE_52_CYCLE_TIME 312500
|
| 507 |
+
CORE_53_CYCLE_TIME 312500
|
| 508 |
+
CORE_54_CYCLE_TIME 312500
|
| 509 |
+
CORE_55_CYCLE_TIME 312500
|
| 510 |
+
CORE_56_CYCLE_TIME 312500
|
| 511 |
+
CORE_57_CYCLE_TIME 312500
|
| 512 |
+
CORE_58_CYCLE_TIME 312500
|
| 513 |
+
CORE_59_CYCLE_TIME 312500
|
| 514 |
+
CORE_60_CYCLE_TIME 312500
|
| 515 |
+
CORE_61_CYCLE_TIME 312500
|
| 516 |
+
CORE_62_CYCLE_TIME 312500
|
| 517 |
+
CORE_63_CYCLE_TIME 312500
|
| 518 |
+
TOPDOWN_FU_EXEC_FEW 0
|
| 519 |
+
ISSUE_WIDTH 4 6
|
| 520 |
+
RS_FILL_WIDTH 8 0
|
| 521 |
+
NODE_TABLE_SIZE 256 512
|
| 522 |
+
NODE_RET_WIDTH 4 8
|
| 523 |
+
NODE_RETIRE_RATE 10
|
| 524 |
+
DECODE_WIDTH 4 6
|
| 525 |
+
IDQ_SIZE 140 144
|
| 526 |
+
REG_RENAMING_SCHEME 0 1
|
| 527 |
+
REG_TABLE_INTEGER_PHYSICAL_SIZE 256 280
|
| 528 |
+
REG_TABLE_VECTOR_PHYSICAL_SIZE 256 332
|
| 529 |
+
REG_TABLE_INTEGER_VIRTUAL_SIZE 256
|
| 530 |
+
REG_TABLE_VECTOR_VIRTUAL_SIZE 256
|
| 531 |
+
REG_RENAMING_MOVE_ELIMINATE FALSE
|
| 532 |
+
NODE_ISSUE_QUEUE_DISPATCH_SCHEME 0
|
| 533 |
+
NODE_ISSUE_QUEUE_SCHEDULE_SCHEME 0
|
| 534 |
+
ISSUE_QUEUE_PARALLEL_PICK FALSE
|
| 535 |
+
RS_SIZES "256" 97 70 19
|
| 536 |
+
RS_CONNECTIONS "xF" b0100110011 b1000001100 b0011000000
|
| 537 |
+
FU_TYPES "0, 0, 0, 0" b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 538 |
+
LSQ_ENABLE TRUE
|
| 539 |
+
LOAD_QUEUE_ENTRY_NUM 128
|
| 540 |
+
STORE_QUEUE_ENTRY_NUM 72
|
| 541 |
+
DECODE_CYCLES 1 5
|
| 542 |
+
MAP_CYCLES 1 5
|
| 543 |
+
ICACHE_LATENCY 3
|
| 544 |
+
EXTRA_REDIRECT_CYCLES 0
|
| 545 |
+
EXTRA_RECOVERY_CYCLES 0
|
| 546 |
+
EXTRA_CALLSYS_CYCLES 20 const
|
| 547 |
+
DIE_ON_CALLSYS FALSE
|
| 548 |
+
DIE_ON_RET_STALL_THRESH 0
|
| 549 |
+
DIE_ON_RET_STALL_CORE 0
|
| 550 |
+
DIE_ON_MEM_BLOCK_THRESH 0
|
| 551 |
+
DIE_ON_MEM_BLOCK_CORE 0
|
| 552 |
+
ICACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 553 |
+
UOP_CACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 554 |
+
FETCH_OFF_PATH_OPS TRUE 1
|
| 555 |
+
WP_COLLECT_STATS TRUE
|
| 556 |
+
OP_INV_DELAY 1
|
| 557 |
+
OP_NOP_DELAY 1
|
| 558 |
+
OP_CF_DELAY 1
|
| 559 |
+
OP_MOV_DELAY 1
|
| 560 |
+
OP_CMOV_DELAY 1
|
| 561 |
+
OP_LDA_DELAY 1
|
| 562 |
+
OP_ILD_DELAY 1
|
| 563 |
+
OP_IST_DELAY 1
|
| 564 |
+
OP_IADD_DELAY 1
|
| 565 |
+
OP_IMUL_DELAY 3
|
| 566 |
+
OP_IDIV_DELAY -20
|
| 567 |
+
OP_ICMP_DELAY 1
|
| 568 |
+
OP_LOGIC_DELAY 1
|
| 569 |
+
OP_SHIFT_DELAY 1
|
| 570 |
+
OP_FLD_DELAY 1
|
| 571 |
+
OP_FST_DELAY 1
|
| 572 |
+
OP_FCVT_DELAY 3
|
| 573 |
+
OP_FADD_DELAY 3
|
| 574 |
+
OP_FMUL_DELAY 5
|
| 575 |
+
OP_FMA_DELAY 5
|
| 576 |
+
OP_FDIV_DELAY -20
|
| 577 |
+
OP_FCMP_DELAY 3
|
| 578 |
+
OP_FCMOV_DELAY 1
|
| 579 |
+
OP_GATHER_DELAY 12
|
| 580 |
+
OP_SCATTER_DELAY 18
|
| 581 |
+
OP_PIPELINED_FAST_DELAY 2
|
| 582 |
+
OP_PIPELINED_MEDIUM_DELAY 5
|
| 583 |
+
OP_PIPELINED_SLOW_DELAY 10
|
| 584 |
+
OP_NOTPIPELINED_MEDIUM_DELAY -5
|
| 585 |
+
OP_NOTPIPELINED_SLOW_DELAY -20
|
| 586 |
+
OP_NOTPIPELINED_VERY_SLOW_DELAY -100
|
| 587 |
+
UNIFORM_OP_DELAY 0
|
| 588 |
+
STALL_ON_WAIT_MEM TRUE
|
| 589 |
+
STORES_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 590 |
+
PREFS_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 591 |
+
OBEY_REG_DEP TRUE
|
| 592 |
+
TRACK_L1_MISS_DEPS FALSE
|
| 593 |
+
CBP_TRACE_R0 NULL /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 594 |
+
CBP_TRACE_R1 NULL
|
| 595 |
+
CBP_TRACE_R2 NULL
|
| 596 |
+
CBP_TRACE_R3 NULL
|
| 597 |
+
CBP_TRACE_R4 NULL
|
| 598 |
+
CBP_TRACE_R5 NULL
|
| 599 |
+
CBP_TRACE_R6 NULL
|
| 600 |
+
CBP_TRACE_R7 NULL
|
| 601 |
+
CBP_TRACE_R8 NULL
|
| 602 |
+
CBP_TRACE_R9 NULL
|
| 603 |
+
CBP_TRACE_R10 NULL
|
| 604 |
+
CBP_TRACE_R11 NULL
|
| 605 |
+
CBP_TRACE_R12 NULL
|
| 606 |
+
CBP_TRACE_R13 NULL
|
| 607 |
+
CBP_TRACE_R14 NULL
|
| 608 |
+
CBP_TRACE_R15 NULL
|
| 609 |
+
CBP_TRACE_R16 NULL
|
| 610 |
+
CBP_TRACE_R17 NULL
|
| 611 |
+
CBP_TRACE_R18 NULL
|
| 612 |
+
CBP_TRACE_R19 NULL
|
| 613 |
+
CBP_TRACE_R20 NULL
|
| 614 |
+
CBP_TRACE_R21 NULL
|
| 615 |
+
CBP_TRACE_R22 NULL
|
| 616 |
+
CBP_TRACE_R23 NULL
|
| 617 |
+
CBP_TRACE_R24 NULL
|
| 618 |
+
CBP_TRACE_R25 NULL
|
| 619 |
+
CBP_TRACE_R26 NULL
|
| 620 |
+
CBP_TRACE_R27 NULL
|
| 621 |
+
CBP_TRACE_R28 NULL
|
| 622 |
+
CBP_TRACE_R29 NULL
|
| 623 |
+
CBP_TRACE_R30 NULL
|
| 624 |
+
CBP_TRACE_R31 NULL
|
| 625 |
+
CBP_TRACE_R32 NULL
|
| 626 |
+
CBP_TRACE_R33 NULL
|
| 627 |
+
CBP_TRACE_R34 NULL
|
| 628 |
+
CBP_TRACE_R35 NULL
|
| 629 |
+
CBP_TRACE_R36 NULL
|
| 630 |
+
CBP_TRACE_R37 NULL
|
| 631 |
+
CBP_TRACE_R38 NULL
|
| 632 |
+
CBP_TRACE_R39 NULL
|
| 633 |
+
CBP_TRACE_R40 NULL
|
| 634 |
+
CBP_TRACE_R41 NULL
|
| 635 |
+
CBP_TRACE_R42 NULL
|
| 636 |
+
CBP_TRACE_R43 NULL
|
| 637 |
+
CBP_TRACE_R44 NULL
|
| 638 |
+
CBP_TRACE_R45 NULL
|
| 639 |
+
CBP_TRACE_R46 NULL
|
| 640 |
+
CBP_TRACE_R47 NULL
|
| 641 |
+
CBP_TRACE_R48 NULL
|
| 642 |
+
CBP_TRACE_R49 NULL
|
| 643 |
+
CBP_TRACE_R50 NULL
|
| 644 |
+
CBP_TRACE_R51 NULL
|
| 645 |
+
CBP_TRACE_R52 NULL
|
| 646 |
+
CBP_TRACE_R53 NULL
|
| 647 |
+
CBP_TRACE_R54 NULL
|
| 648 |
+
CBP_TRACE_R55 NULL
|
| 649 |
+
CBP_TRACE_R56 NULL
|
| 650 |
+
CBP_TRACE_R57 NULL
|
| 651 |
+
CBP_TRACE_R58 NULL
|
| 652 |
+
CBP_TRACE_R59 NULL
|
| 653 |
+
CBP_TRACE_R60 NULL
|
| 654 |
+
CBP_TRACE_R61 NULL
|
| 655 |
+
CBP_TRACE_R62 NULL
|
| 656 |
+
CBP_TRACE_R63 NULL
|
| 657 |
+
FE_FTQ_BLOCK_NUM 32
|
| 658 |
+
FE_FTQ_TAKEN_CFS_PER_CYCLE 2
|
| 659 |
+
FE_FTQ_FT_PER_CYCLE 1
|
| 660 |
+
DUMB_CORE_ON FALSE
|
| 661 |
+
DUMB_CORE 1
|
| 662 |
+
DCACHE_MISS_RATE 10
|
| 663 |
+
L1_MISS_RATE 10
|
| 664 |
+
TRACE_BUF_SIZE 0
|
| 665 |
+
PERFECT_CONFIDENCE FALSE
|
| 666 |
+
CONFIDENCE_ENABLE FALSE
|
| 667 |
+
CONFIDENCE_MECH 0
|
| 668 |
+
CONF_OFF_PATH_THRESHOLD 15
|
| 669 |
+
CONF_OFF_PATH_INC 5
|
| 670 |
+
CONF_BTB_MISS_BP_TAKEN FALSE
|
| 671 |
+
CONF_IPC_RATE_CONF FALSE
|
| 672 |
+
CONF_BTB_MISS_BP_TAKEN_THRESHOLD 0
|
| 673 |
+
CONF_BTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 674 |
+
CONF_IBTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 675 |
+
CONF_MISFETCH_RATE_CYCLES_THRESHOLD 1.0
|
| 676 |
+
CONF_MISPRED_RATE_CYCLES_THRESHOLD 1.0
|
| 677 |
+
CONF_BTB_MISS_SAMPLE_RATE 100000
|
| 678 |
+
CONF_IBTB_MISS_SAMPLE_RATE 100000
|
| 679 |
+
CONF_MISFETCH_SAMPLE_RATE 100000
|
| 680 |
+
CONF_MISPRED_SAMPLE_RATE 100000
|
| 681 |
+
CONF_IPC_SAMPLE_RATE 100000
|
| 682 |
+
CONF_BTB_MISS_RATE_WEIGHT 200
|
| 683 |
+
CONF_BTB_MISS_BP_TAKEN_CONF TRUE
|
| 684 |
+
CONF_IBTB_MISS_BP_TAKEN_CONF TRUE
|
| 685 |
+
CONF_BTB_MISS_RATE_CONF TRUE
|
| 686 |
+
CONF_IBTB_MISS_RATE_CONF TRUE
|
| 687 |
+
CONF_MISFETCH_RATE_CONF TRUE
|
| 688 |
+
CONF_MISPRED_RATE_CONF TRUE
|
| 689 |
+
CONF_INV_BP_CONF TRUE
|
| 690 |
+
CONF_PERFECT_BTB_MISS_CONF FALSE
|
| 691 |
+
CONF_PERFECT_IBTB_MISS_CONF FALSE
|
| 692 |
+
CONF_PERFECT_MISFETCH_CONF FALSE
|
| 693 |
+
CONF_PERFECT_MISPRED_CONF FALSE
|
| 694 |
+
CONF_LOG_DFE_TO_REC FALSE
|
| 695 |
+
CONF_LOG_PHASE_CYCLES FALSE
|
| 696 |
+
NUM_BPS 1
|
| 697 |
+
DFE0_TRIGGER_POLICY 0
|
| 698 |
+
DFE1_TRIGGER_POLICY 1
|
| 699 |
+
DFE2_TRIGGER_POLICY 1
|
| 700 |
+
DFE3_TRIGGER_POLICY 1
|
| 701 |
+
DFE4_TRIGGER_POLICY 1
|
| 702 |
+
DFE0_STOP_POLICY 0
|
| 703 |
+
DFE1_STOP_POLICY 1
|
| 704 |
+
DFE2_STOP_POLICY 1
|
| 705 |
+
DFE3_STOP_POLICY 1
|
| 706 |
+
DFE4_STOP_POLICY 1
|
| 707 |
+
LOOKAHEAD_BUF_SIZE 0
|
| 708 |
+
DEBUG_CYCLE_START 0 0
|
| 709 |
+
DEBUG_CYCLE_STOP 0 -1
|
| 710 |
+
DEBUG_TIME_START 0
|
| 711 |
+
DEBUG_TIME_STOP 0
|
| 712 |
+
DEBUG_INST_START 0 0
|
| 713 |
+
DEBUG_INST_STOP 0 -1
|
| 714 |
+
DEBUG_OP_START 0
|
| 715 |
+
DEBUG_OP_STOP 0
|
| 716 |
+
DEBUG_CACHE_LIB FALSE
|
| 717 |
+
DEBUG_HASH_LIB FALSE
|
| 718 |
+
DEBUG_LIST_LIB FALSE
|
| 719 |
+
DEBUG_PORT_LIB FALSE
|
| 720 |
+
DEBUG_BUS_LIB FALSE
|
| 721 |
+
DEBUG_OP_POOL FALSE
|
| 722 |
+
DEBUG_ORACLE FALSE
|
| 723 |
+
DEBUG_FRONTEND FALSE
|
| 724 |
+
DEBUG_ADDR_TRANS FALSE
|
| 725 |
+
DEBUG_BP FALSE
|
| 726 |
+
DEBUG_BP_DIR FALSE
|
| 727 |
+
DEBUG_BTB FALSE
|
| 728 |
+
DEBUG_CRS FALSE
|
| 729 |
+
DEBUG_MAP FALSE
|
| 730 |
+
DEBUG_MEMORY FALSE
|
| 731 |
+
DEBUG_REPLAY FALSE
|
| 732 |
+
DEBUG_FREQ FALSE
|
| 733 |
+
DEBUG_MODEL FALSE
|
| 734 |
+
DEBUG_THREAD FALSE
|
| 735 |
+
DEBUG_DECOUPLED_FE FALSE
|
| 736 |
+
DEBUG_CONF FALSE
|
| 737 |
+
DEBUG_ICACHE_STAGE FALSE
|
| 738 |
+
DEBUG_DECODE_STAGE FALSE
|
| 739 |
+
DEBUG_CPP_CACHE FALSE
|
| 740 |
+
DEBUG_UOP_CACHE FALSE
|
| 741 |
+
DEBUG_UOP_QUEUE_STAGE FALSE
|
| 742 |
+
DEBUG_IDQ_STAGE FALSE
|
| 743 |
+
DEBUG_MAP_STAGE FALSE
|
| 744 |
+
DEBUG_NODE_STAGE FALSE
|
| 745 |
+
DEBUG_EXEC_STAGE FALSE
|
| 746 |
+
DEBUG_DCACHE_STAGE FALSE
|
| 747 |
+
DEBUG_RETIRED_UOPS FALSE
|
| 748 |
+
DEBUG_EXC_INSERTS FALSE
|
| 749 |
+
DEBUG_BP_CONF FALSE
|
| 750 |
+
DEBUG_ONPATH_CONF FALSE
|
| 751 |
+
DEBUG_STREAM FALSE
|
| 752 |
+
DEBUG_STREAM_MEM FALSE
|
| 753 |
+
DEBUG_WAY FALSE
|
| 754 |
+
DEBUG_L2MARKV FALSE
|
| 755 |
+
DEBUG_L2L1PREF FALSE
|
| 756 |
+
DEBUG_PERF_PRED FALSE
|
| 757 |
+
DEBUG_POWER_UTILS FALSE
|
| 758 |
+
DEBUG_DVFS FALSE
|
| 759 |
+
DEBUG_TRACE_READ FALSE
|
| 760 |
+
DEBUG_INST_FIELDS FALSE
|
| 761 |
+
DEBUG_OP_FIELDS FALSE
|
| 762 |
+
DEBUG_PIN_EXEC_DRIVEN FALSE
|
| 763 |
+
DEBUG_CACHE_PART FALSE
|
| 764 |
+
DEBUG_OPTIMIZER2 FALSE
|
| 765 |
+
DEBUG_PREF FALSE
|
| 766 |
+
DEBUG_FDIP FALSE
|
| 767 |
+
DEBUG_EIP FALSE
|
| 768 |
+
DEBUG_DJOLT FALSE
|
| 769 |
+
DEBUG_FNLMMA FALSE
|
| 770 |
+
PERFECT_BP FALSE
|
| 771 |
+
PERFECT_BTB FALSE
|
| 772 |
+
PERFECT_IBP FALSE
|
| 773 |
+
PERFECT_CRS FALSE
|
| 774 |
+
PERFECT_CBR_BTB FALSE
|
| 775 |
+
PERFECT_NT_BTB FALSE 0 # deprecated, effectively always true.
|
| 776 |
+
CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle
|
| 777 |
+
UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 778 |
+
BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec.
|
| 779 |
+
BP_MECH TAGE64K_BP tage64k
|
| 780 |
+
BP_MECH_L0 BIMODAL_BP
|
| 781 |
+
BP_L0_LATENCY 1
|
| 782 |
+
BP_MAIN_LATENCY 3
|
| 783 |
+
BIMODAL_ENTRIES (4 * 1024)
|
| 784 |
+
HIST_LENGTH 16
|
| 785 |
+
PHT_CTR_BITS 2 const
|
| 786 |
+
BHT_ENTRIES (4 * 1024)
|
| 787 |
+
BHT_ASSOC 4
|
| 788 |
+
HYBRIDS_INDEX_LENGTH 16
|
| 789 |
+
HYBRIDG_HIST_LENGTH 16
|
| 790 |
+
HYBRIDP_HIST_LENGTH 16
|
| 791 |
+
FILTER_INDEX_LENGTH 16
|
| 792 |
+
USE_FILTER FALSE
|
| 793 |
+
INF_HYBRIDGP FALSE
|
| 794 |
+
BP_HASH_TOS FALSE
|
| 795 |
+
IBTB_HASH_TOS FALSE
|
| 796 |
+
BTB_MECH GENERIC_BTB generic
|
| 797 |
+
BTB_ENTRIES 12288 12288
|
| 798 |
+
BTB_ASSOC 4 4
|
| 799 |
+
BTB_NUM_BRSLOT 1
|
| 800 |
+
BTB_BLOCK_SIZE 64
|
| 801 |
+
BTB_OFF_PATH_WRITES TRUE 1
|
| 802 |
+
BTB_MAIN_LATENCY 3 3
|
| 803 |
+
BTB_L0_PRESENT FALSE 1
|
| 804 |
+
BTB_L0_ENTRIES 128 128
|
| 805 |
+
BTB_L0_ASSOC 4 4
|
| 806 |
+
BTB_L0_LATENCY 1 1
|
| 807 |
+
BTB_L1_PRESENT FALSE 1
|
| 808 |
+
BTB_L1_ENTRIES 6144 6144
|
| 809 |
+
BTB_L1_ASSOC 4 4
|
| 810 |
+
BTB_L1_LATENCY 2 2
|
| 811 |
+
ENABLE_CRS TRUE 1
|
| 812 |
+
CRS_ENTRIES 32 128
|
| 813 |
+
CRS_REALISTIC 0 1
|
| 814 |
+
ENABLE_IBP TRUE 1 # Enable the indirect branch predictor
|
| 815 |
+
USE_PAT_HIST TRUE
|
| 816 |
+
IBTB_MECH 1 tc_tagged
|
| 817 |
+
IBTB_HIST_LENGTH 16
|
| 818 |
+
IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb.
|
| 819 |
+
TARGETS_IN_HIST 4
|
| 820 |
+
TC_ENTRIES (4 * 1024) 4096
|
| 821 |
+
TC_ASSOC 4 4
|
| 822 |
+
NUM_CORR_BRANCHES 3
|
| 823 |
+
SEL_HIST_BP_ENTRIES 8192
|
| 824 |
+
SEL_HIST_LENGTH 16
|
| 825 |
+
SEL_HIST_DYN_CNT_TH 16
|
| 826 |
+
SEL_HIST_MISPRED_TH 4
|
| 827 |
+
ENABLE_BP_CONF FALSE
|
| 828 |
+
CONF_MECH 0
|
| 829 |
+
PERF_BP_CONF_PRED FALSE
|
| 830 |
+
BPC_BITS 16
|
| 831 |
+
BPC_MECH 1
|
| 832 |
+
BPC_CTR_RESET TRUE
|
| 833 |
+
BPC_CIT_BITS 8
|
| 834 |
+
BPC_CIT_TH 50
|
| 835 |
+
BPC_CTR_BITS 3
|
| 836 |
+
OPC_COUNT_ZEROS FALSE
|
| 837 |
+
OPC_COUNT_THRESH 10
|
| 838 |
+
INF_LOOP FALSE
|
| 839 |
+
INF_LOOP_BUCKETS 811
|
| 840 |
+
LOOP_ENTRIES (4 * 1024)
|
| 841 |
+
LOOP_ASSOC 4
|
| 842 |
+
LOOP_COUNT_MAX 127
|
| 843 |
+
LOOP_REPEAT_MAX 15
|
| 844 |
+
KNOB_PRINT_BRINFO FALSE
|
| 845 |
+
BR_MISPRED_FILE NULL
|
| 846 |
+
SPEC_LEVEL 3
|
| 847 |
+
RANDOM_DETERMINISTIC TRUE
|
| 848 |
+
TAGESCL64KB_SC TRUE
|
| 849 |
+
TAGESCL64KB_LOOP TRUE
|
| 850 |
+
TAGESCL64KB_ALT TRUE
|
| 851 |
+
CONF_PERCEPTRON_TH 0
|
| 852 |
+
CONF_PERCEPTRON_CTR_BITS 8
|
| 853 |
+
CONF_PERCEPTRON_ENTRIES 127
|
| 854 |
+
CONF_PERCEPTRON_THRESH_OVRD 0
|
| 855 |
+
CONF_HIST_LENGTH 32
|
| 856 |
+
PERCEPTRON_CONF_USE_CONF FALSE
|
| 857 |
+
PERCEPTRON_CONF_TRAIN_HIS FALSE
|
| 858 |
+
PERCEPTRON_CONF_TRAIN_CONF FALSE
|
| 859 |
+
PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE
|
| 860 |
+
PERCEPTRON_TRAIN_MISP_FACTOR 1
|
| 861 |
+
PERCEPTRON_TRAIN_CORR_FACTOR 1
|
| 862 |
+
PERCEPTRON_CONF_HIS_BOTH FALSE
|
| 863 |
+
PERCEPTRON_CONF_HIS_BOTH_LENGTH 4
|
| 864 |
+
MTAGE_REALISTIC_SC_40K FALSE
|
| 865 |
+
MTAGE_REALISTIC_SC_100K FALSE
|
| 866 |
+
H2P_TABLE_BUCKETS 16384
|
| 867 |
+
H2P_MIN_EXEC 5000
|
| 868 |
+
H2P_MIN_MISPRED 333
|
| 869 |
+
H2P_MISPRED_RATIO_PERMIL 10
|
| 870 |
+
H2P_TRACK_CBR TRUE
|
| 871 |
+
H2P_TRACK_REP TRUE
|
| 872 |
+
H2P_TRACK_CALL FALSE
|
| 873 |
+
H2P_TRACK_IBR FALSE
|
| 874 |
+
H2P_TRACK_ICALL FALSE
|
| 875 |
+
H2P_TRACK_RET FALSE
|
| 876 |
+
POWER_INTF_ON FALSE
|
| 877 |
+
POWER_INTF_ENABLE_SCALING FALSE
|
| 878 |
+
POWER_INTF_EXEC "power/power_intf.py"
|
| 879 |
+
POWER_INTF_REF_CHIP_TECH_NM 22
|
| 880 |
+
POWER_INTF_REF_CHIP_FREQ (3.2e9)
|
| 881 |
+
POWER_INTF_REF_MEMORY_FREQ (0.8e9)
|
| 882 |
+
POWER_OTHER (0.0)
|
| 883 |
+
PREF_STREAM_ON FALSE 1
|
| 884 |
+
PREF_STREAM_PER_CORE_ENABLE FALSE
|
| 885 |
+
STREAM_BUFFER_N 16
|
| 886 |
+
STREAM_PREFETCH_N 2 4
|
| 887 |
+
STREAM_START_DIS 5 1
|
| 888 |
+
STREAM_LENGTH 16 64
|
| 889 |
+
STREAM_FULL_N 1
|
| 890 |
+
STREAM_TRAIN_LENGTH 16
|
| 891 |
+
STREAM_TRAIN_NUM 1 4
|
| 892 |
+
PREF_ACC_USE_CACHE FALSE
|
| 893 |
+
STREAM_STALL_ON_QUEUE_FULL FALSE
|
| 894 |
+
PREF_SCHEDULE_NUM 4
|
| 895 |
+
TRAIN_FILTER_SIZE 32
|
| 896 |
+
PREF_REQ_Q_SIZE 64
|
| 897 |
+
STREAM_CREATE_ON_DC_MISS FALSE 0
|
| 898 |
+
STREAM_CREATE_ON_L1_MISS TRUE 1
|
| 899 |
+
STREAM_TRAIN_ON_WRONGPATH TRUE
|
| 900 |
+
STREAM_CREATE_ON_WRONGPATH TRUE
|
| 901 |
+
STREAM_PREF_INTO_DCACHE FALSE
|
| 902 |
+
REMOVE_REDUNDANT_STREAM FALSE
|
| 903 |
+
L2HIT_STREAM_SCHEDULE_NUM 4
|
| 904 |
+
PREF_REQ_QUEUE_FILTER_ON FALSE
|
| 905 |
+
HW_PREF_HIT_TRAIN_STREAM FALSE
|
| 906 |
+
L2HIT_STREAM_BUFFER_N 32
|
| 907 |
+
L2HIT_STREAM_PREFETCH_N 2
|
| 908 |
+
L2HIT_STREAM_START_DIS 2
|
| 909 |
+
L2HIT_STREAM_LENGTH 8
|
| 910 |
+
L2HIT_PREF_REQ_Q_SIZE 128
|
| 911 |
+
L2HIT_L2ACCESS_REQ_Q_SIZE 64
|
| 912 |
+
PREF_STREAM_ACCPERSTREAM FALSE
|
| 913 |
+
PREF_ACC_DISTANCE_10 128
|
| 914 |
+
PREF_FRAMEWORK_ON FALSE 1
|
| 915 |
+
PREF_TRACE_ON FALSE
|
| 916 |
+
PREF_UMLC_ON FALSE
|
| 917 |
+
PREF_UL1_ON TRUE
|
| 918 |
+
PREF_DL0REQ_QUEUE_SIZE 32
|
| 919 |
+
PREF_UMLC_REQ_QUEUE_SIZE 64
|
| 920 |
+
PREF_UL1REQ_QUEUE_SIZE 128
|
| 921 |
+
PREF_SHARED_QUEUES TRUE
|
| 922 |
+
PREF_DL0_MISS_ON TRUE
|
| 923 |
+
PREF_DL0_HIT_ON TRUE
|
| 924 |
+
PREF_DL0REQ_QUEUE_FILTER_ON TRUE
|
| 925 |
+
PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE
|
| 926 |
+
PREF_UL1REQ_QUEUE_FILTER_ON TRUE
|
| 927 |
+
PREF_DL0REQ_ADD_FILTER_ON TRUE
|
| 928 |
+
PREF_UMLC_REQ_ADD_FILTER_ON TRUE
|
| 929 |
+
PREF_UL1REQ_ADD_FILTER_ON TRUE
|
| 930 |
+
PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 931 |
+
PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 932 |
+
PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1
|
| 933 |
+
PREF_DL0SCHEDULE_NUM 4
|
| 934 |
+
PREF_UMLC_SCHEDULE_NUM 4
|
| 935 |
+
PREF_UL1SCHEDULE_NUM 4
|
| 936 |
+
PREF_L1Q_DEMAND_RESERVE 0
|
| 937 |
+
PREF_REPORT_PREF_MATCH_AS_MISS FALSE
|
| 938 |
+
PREF_REPORT_PREF_MATCH_AS_HIT TRUE
|
| 939 |
+
PREF_UPDATE_ON_WRONGPATH TRUE
|
| 940 |
+
PREF_TRAIN_ON_PREF_MISSES FALSE 0
|
| 941 |
+
PREF_ORACLE_TRAIN_ON FALSE 0
|
| 942 |
+
PREF_REQ_DROP FALSE
|
| 943 |
+
PREF_THROTTLE_ON FALSE
|
| 944 |
+
PREF_THROTTLEFB_ON FALSE 1
|
| 945 |
+
PREF_ACC_THRESH_1 0.90 0.75
|
| 946 |
+
PREF_ACC_THRESH_2 0.70 0.4
|
| 947 |
+
PREF_ACC_THRESH_3 0.60 0.4
|
| 948 |
+
PREF_ACC_THRESH_4 0.40
|
| 949 |
+
PREF_UPDATE_INTERVAL 0 8192
|
| 950 |
+
PREF_ANALYZE_LOAD FALSE
|
| 951 |
+
PREF_POL_THRESH_1 0.25
|
| 952 |
+
PREF_POL_THRESH_2 0.10
|
| 953 |
+
PREF_POLBV_ON FALSE
|
| 954 |
+
PREF_POLBV_SIZE 1024
|
| 955 |
+
PREF_TIMELY_THRESH 0.05 0.01
|
| 956 |
+
PREF_POLPF_THRESH 0.01 0.005
|
| 957 |
+
PREF_DEGFB_USEONLYACC FALSE
|
| 958 |
+
PREF_DEGFB_USEONLYPOL FALSE
|
| 959 |
+
PREF_DEGFB_USEONLYLATE FALSE
|
| 960 |
+
PREF_TIMELY_THRESH_2 0.005
|
| 961 |
+
PREF_DEGFB_STATPHASEFILE FALSE
|
| 962 |
+
PREF_MAX_DEGFB 4
|
| 963 |
+
PREF_DHAL FALSE
|
| 964 |
+
PREF_DHAL_SENTTHRESH 16
|
| 965 |
+
PREF_DHAL_USETHRESH_MAX 12
|
| 966 |
+
PREF_DHAL_USETHRESH_MIN2 8
|
| 967 |
+
PREF_DHAL_USETHRESH_MIN1 4
|
| 968 |
+
PREF_DHAL_MAXDEG 64
|
| 969 |
+
PREF_HFILTER_ON FALSE
|
| 970 |
+
PREF_HFILTER_INDEX_BITS 12
|
| 971 |
+
PREF_HFILTER_USE_PC FALSE
|
| 972 |
+
PREF_HFILTER_PRED_USELESS_THRES 2
|
| 973 |
+
PREF_HFILTER_RESET_ENABLE FALSE
|
| 974 |
+
PREF_HFILTER_RESET_INTERVAL 100000
|
| 975 |
+
EIP_ENABLE 0
|
| 976 |
+
L1I_ENTANGLED_TABLE_INDEX_BITS 9
|
| 977 |
+
L1I_ENTANGLED_TABLE_WAYS 16
|
| 978 |
+
DJOLT_ENABLE 0
|
| 979 |
+
FNLMMA_ENABLE 0
|
| 980 |
+
FDIP_ENABLE 1
|
| 981 |
+
FDIP_ALWAYS_PREFETCH FALSE
|
| 982 |
+
PERFECT_FDIP FALSE
|
| 983 |
+
IPRF_MAX_FTQ_ENTRY_CYC 2
|
| 984 |
+
FDIP_BLOOM_FILTER FALSE
|
| 985 |
+
FDIP_BLOOM_ENTRIES 4000
|
| 986 |
+
FDIP_BLOOM2_ENTRIES 1000
|
| 987 |
+
FDIP_BLOOM4_ENTRIES 1000
|
| 988 |
+
FDIP_BLOOM_SIZE 16384
|
| 989 |
+
FDIP_BLOOM_HASHES 6
|
| 990 |
+
FDIP_BLOOM_CLEAR_UNUSEFUL_RATIO 0.95
|
| 991 |
+
FDIP_BLOOM_CLEAR_CYC_PERIOD 10000
|
| 992 |
+
FDIP_UTILITY_HASH_ENABLE 0
|
| 993 |
+
FDIP_UTILITY_PREF_POLICY 0
|
| 994 |
+
FDIP_ADJUSTABLE_FTQ 0
|
| 995 |
+
FDIP_ADJUSTABLE_FTQ_CYC 100000
|
| 996 |
+
UTILITY_RATIO_THRESHOLD 0.58
|
| 997 |
+
TIMELINESS_RATIO_THRESHOLD 0.82
|
| 998 |
+
FDIP_PREF_NO_LATENCY FALSE
|
| 999 |
+
UDP_USEFUL_THRESHOLD 0
|
| 1000 |
+
UDP_WEIGHT_USEFUL 4
|
| 1001 |
+
UDP_WEIGHT_UNUSEFUL 1
|
| 1002 |
+
UDP_WEIGHT_POSITIVE_SATURATION 2147483647
|
| 1003 |
+
FDIP_GHIST_HASHING FALSE
|
| 1004 |
+
FDIP_UTILITY_ONLY_TRAIN_OFF_PATH FALSE
|
| 1005 |
+
FDIP_GHIST_BITS 8
|
| 1006 |
+
UFTQ_MIN_FTQ_BLOCK_NUM 4
|
| 1007 |
+
UFTQ_MAX_FTQ_BLOCK_NUM 64
|
| 1008 |
+
FDIP_SENIORITY_FTQ_HOLD_CYC 30000
|
| 1009 |
+
FDIP_PERFECT_PREFETCH FALSE
|
| 1010 |
+
FDIP_FREEZE_AT_MEM_BUF_LIMIT TRUE
|
| 1011 |
+
FDIP_DUAL_PATH_PREF_IC_ENABLE FALSE
|
| 1012 |
+
FDIP_DUAL_PATH_PREF_UOC_ENABLE FALSE
|
| 1013 |
+
TOP_MISPRED_BR_FILEPATH "br_resteer_coverage.csv"
|
| 1014 |
+
TOP_MISPRED_BR_RESTEER_COVERAGE 0
|
| 1015 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_ENABLE FALSE
|
| 1016 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_MISPRED_THRESHOLD 1
|
| 1017 |
+
FDIP_PRINT_CL_INFO FALSE
|
| 1018 |
+
BRANCH_MISPREDICTION_TABLE_SIZE 0
|
| 1019 |
+
UOC_PREF FALSE
|
| 1020 |
+
UOC_ORACLE_PREF FALSE
|
| 1021 |
+
UOC_ZERO_LATENCY_PREF FALSE
|
| 1022 |
+
L2L1PREF_ON FALSE
|
| 1023 |
+
L2WAY_PREF FALSE
|
| 1024 |
+
L2MARKV_PREF_ON FALSE
|
| 1025 |
+
L2NEXT_PREF_ON FALSE
|
| 1026 |
+
L2HIT_STREAM_PREF_ON FALSE
|
| 1027 |
+
L2L1_DC_HIT_TRAIN FALSE
|
| 1028 |
+
L1_HIT_DUMP_FILE_ON FALSE
|
| 1029 |
+
L1_HIT_DUMP_WO_TXT FALSE
|
| 1030 |
+
L1_HIT_DUMPFILE "l1hit_dump.out"
|
| 1031 |
+
IDEAL_L2_L1_PREFETCHER FALSE
|
| 1032 |
+
IDEAL_L2_ICACHE_PREFETCHER FALSE
|
| 1033 |
+
L1WAY_PREF_SEND_QUEUE 4
|
| 1034 |
+
L1PREF_REQ_QUEUE_SIZE 1024
|
| 1035 |
+
L1PREF_IMMEDIATE FALSE
|
| 1036 |
+
L1WAY_PREF_TIMER_DIS 1000
|
| 1037 |
+
L1MARKV_PREF_SEND_QUEUE 4
|
| 1038 |
+
L1PREF_MARKV_REQ_QUEUE_SIZE 1024
|
| 1039 |
+
MARKV_L2ACCESS_REQ_Q_SIZE 64
|
| 1040 |
+
L1MARKV_PREF_IMMEDIATE FALSE
|
| 1041 |
+
L1MARKV_PREF_TIMER_DIS 1
|
| 1042 |
+
L2L1_HIT_TRAIN TRUE
|
| 1043 |
+
L1MARKV_REQ_TH 1
|
| 1044 |
+
L2L1_IMMEDIATE_PREF_CACHE FALSE
|
| 1045 |
+
L2L1_FILL_PREF_CACHE FALSE
|
| 1046 |
+
L2L1_L2_HIT_STAT FALSE
|
| 1047 |
+
PREF_GHB_ON FALSE
|
| 1048 |
+
DEBUG_PREF_GHB FALSE
|
| 1049 |
+
PREF_GHB_BUFFER_N 1024
|
| 1050 |
+
PREF_GHB_INDEX_N 128
|
| 1051 |
+
PREF_GHB_CZONE_BITS 12
|
| 1052 |
+
PREF_GHB_DEGREE 16
|
| 1053 |
+
PREF_GHB_MAX_DEGREE 32
|
| 1054 |
+
PREF_STRIDE_ON FALSE
|
| 1055 |
+
DEBUG_PREF_STRIDE FALSE
|
| 1056 |
+
PREF_STRIDE_TABLE_N 1024
|
| 1057 |
+
PREF_STRIDE_REGION_BITS 16
|
| 1058 |
+
PREF_STRIDE_DEGREE 4
|
| 1059 |
+
PREF_STRIDE_DISTANCE 16
|
| 1060 |
+
PREF_STRIDE_STARTDISTANCE 1
|
| 1061 |
+
PREF_STRIDE_SINGLE_THRESH 6
|
| 1062 |
+
PREF_STRIDE_MULTI_THRESH 6
|
| 1063 |
+
PREF_STRIDE_SINGLE_STRIDE_MODE FALSE
|
| 1064 |
+
PREF_STRIDEPC_ON FALSE
|
| 1065 |
+
DEBUG_PREF_STRIDEPC FALSE
|
| 1066 |
+
PREF_STRIDEPC_TABLE_N 1024
|
| 1067 |
+
PREF_STRIDEPC_DEGREE 4
|
| 1068 |
+
PREF_STRIDEPC_DISTANCE 16
|
| 1069 |
+
PREF_STRIDEPC_USELOADADDR FALSE
|
| 1070 |
+
PREF_STRIDEPC_TRAINNUM 2
|
| 1071 |
+
PREF_STRIDEPC_STARTDIS 4
|
| 1072 |
+
PREF_PHASE_ON FALSE
|
| 1073 |
+
PREF_PHASE_STUDY FALSE
|
| 1074 |
+
DEBUG_PREF_PHASE FALSE
|
| 1075 |
+
PREF_PHASE_PRIME_HASH 16381
|
| 1076 |
+
PREF_PHASE_INFOSIZE 16384
|
| 1077 |
+
PREF_PHASE_LOG2REGIONSIZE 12
|
| 1078 |
+
PREF_PHASE_REGIONENTRIES 64
|
| 1079 |
+
PREF_PHASE_TRACKEDREGIONS 32
|
| 1080 |
+
PREF_PHASE_INTERVAL 100000
|
| 1081 |
+
PREF_PHASE_TABLE_SIZE 64
|
| 1082 |
+
PREF_PHASE_MAXDIFF_THRESH 64
|
| 1083 |
+
PREF_PHASE_MIN_MISSES 64
|
| 1084 |
+
PREF_PHASE_MISSPER 0.4
|
| 1085 |
+
PREF_2DC_ON FALSE
|
| 1086 |
+
DEBUG_PREF_2DC FALSE
|
| 1087 |
+
PREF_2DC_CACHE_SIZE (1 * 1024)
|
| 1088 |
+
PREF_2DC_CACHE_ASSOC 4
|
| 1089 |
+
PREF_2DC_CACHE_LINE_SIZE 1
|
| 1090 |
+
PREF_2DC_DEGREE 16
|
| 1091 |
+
PREF_2DC_ZONE_SHIFT 10
|
| 1092 |
+
PREF_2DC_TAG_SIZE 16
|
| 1093 |
+
PREF_2DC_NUM_REGIONS 64
|
| 1094 |
+
PREF_2DC_REGION_HASH 61
|
| 1095 |
+
PREF_MARKOV_ON FALSE
|
| 1096 |
+
DEBUG_PREF_MARKOV FALSE
|
| 1097 |
+
PREF_MARKOV_NUM_ENTRIES 65536
|
| 1098 |
+
PREF_MARKOV_NUM_NEXT_STATES 8
|
| 1099 |
+
PREF_MARKOV_SEND_ON_PREF_HIT TRUE
|
| 1100 |
+
PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE
|
| 1101 |
+
PREF_MARKOV_TABLE_UPDATE_POLICY 0
|
| 1102 |
+
PREF_MARKOV_SEND_THRESHOLD 0
|
sssp_facebook/fingerprint/run_3/sim.log
ADDED
|
@@ -0,0 +1,59 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
[0]: ad: 0x7ffff3d9b7cc, op: 847
|
| 2 |
+
[0]: ad: 0x7ffff3d9b7cf, op: 330
|
| 3 |
+
new bb detected: 1
|
| 4 |
+
[1]: ad: 0x7ffff3d9b7b0, op: 388
|
| 5 |
+
[1]: ad: 0x7ffff3d9b7b3, op: 8
|
| 6 |
+
[1]: ad: 0x7ffff3d9b7b7, op: 109
|
| 7 |
+
[1]: ad: 0x7ffff3d9b7bb, op: 315
|
| 8 |
+
new bb detected: 2
|
| 9 |
+
[2]: ad: 0x7ffff3d9b7c1, op: 427
|
| 10 |
+
[2]: ad: 0x7ffff3d9b7c8, op: 427
|
| 11 |
+
[2]: ad: 0x7ffff3d9b7cc, op: 847
|
| 12 |
+
[2]: ad: 0x7ffff3d9b7cf, op: 330
|
| 13 |
+
new bb detected: 3
|
| 14 |
+
Scarab gitrev: 7185dea
|
| 15 |
+
Warning: Scarab expects the trace file type to include OFFLINE_FILE_TYPE_ARCH_REGDEPS (0x20000), but got type: 0xe40
|
| 16 |
+
Scarab started at Fri Jul 17 23:07:24 2026
|
| 17 |
+
|
| 18 |
+
read from initialization: 0x7ffff3d9b7cc
|
| 19 |
+
advanceReader: ROI end reached (ordinal 40000002 > roi_end 40000000)
|
| 20 |
+
Reached end of trace (last_inst) pc=0x7ffff3d9b7cc
|
| 21 |
+
[3]: ad: 0x7ffff3d9b7c1, op: 427
|
| 22 |
+
[3]: ad: 0x7ffff3d9b7c8, op: 427
|
| 23 |
+
DUP bb detected at trace end
|
| 24 |
+
to be appened segment num 1
|
| 25 |
+
10000000
|
| 26 |
+
10000000
|
| 27 |
+
====================================
|
| 28 |
+
TRACE_INST_TAKEN_NOT_CF:0
|
| 29 |
+
TRACE_INST_TAKEN_CF_BR:0
|
| 30 |
+
TRACE_INST_TAKEN_CF_CBR:1250000
|
| 31 |
+
TRACE_INST_TAKEN_CF_REP:0
|
| 32 |
+
TRACE_INST_TAKEN_CF_CALL:0
|
| 33 |
+
TRACE_INST_TAKEN_CF_IBR:0
|
| 34 |
+
TRACE_INST_TAKEN_CF_ICALL:0
|
| 35 |
+
TRACE_INST_TAKEN_CF_ICO:0
|
| 36 |
+
TRACE_INST_TAKEN_CF_RET:0
|
| 37 |
+
TRACE_INST_TAKEN_CF_SYS:0
|
| 38 |
+
====================================
|
| 39 |
+
identity within this segment
|
| 40 |
+
2 bbs with same first pc
|
| 41 |
+
[3]: size 4, freq 1249999
|
| 42 |
+
7ffff3d9b7c1: 427, 0
|
| 43 |
+
7ffff3d9b7c8: 427, 0
|
| 44 |
+
7ffff3d9b7cc: 847, 0
|
| 45 |
+
7ffff3d9b7cf: 330, 0
|
| 46 |
+
[3]: size 2, freq 1
|
| 47 |
+
7ffff3d9b7c1: 427, 0
|
| 48 |
+
7ffff3d9b7c8: 427, 0
|
| 49 |
+
1 / 3
|
| 50 |
+
========================================================
|
| 51 |
+
Number of blocks built : 3
|
| 52 |
+
Average size : 3.33 instructions
|
| 53 |
+
Number of blocks executed : 2500001
|
| 54 |
+
Average weighted size : 4.00 instructions
|
| 55 |
+
Number of total instructions : 10000000
|
| 56 |
+
Number of fetched instruction : 10000000
|
| 57 |
+
========================================================
|
| 58 |
+
Scarab finished at Fri Jul 17 23:07:28 2026
|
| 59 |
+
|
sssp_facebook/fingerprint/run_4/PARAMS.in
ADDED
|
@@ -0,0 +1,268 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# File : PARAMS.golden_cove
|
| 2 |
+
# Date : 02/27/25
|
| 3 |
+
# Description : Golden Cove Configuration
|
| 4 |
+
# Author : Surim Oh <[email protected]>
|
| 5 |
+
#
|
| 6 |
+
# Based on documentation found here:
|
| 7 |
+
# https://en.wikipedia.org/wiki/Golden_Cove
|
| 8 |
+
# https://en.wikichip.org/wiki/intel/microarchitectures/golden_cove
|
| 9 |
+
# https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/3
|
| 10 |
+
|
| 11 |
+
## Simulation Parameters
|
| 12 |
+
--mode full
|
| 13 |
+
--model cmp
|
| 14 |
+
--sim_limit none
|
| 15 |
+
|
| 16 |
+
## Core Parameters
|
| 17 |
+
|
| 18 |
+
# Femptoseconds, 3.2GHz, used for energy estimates.
|
| 19 |
+
--chip_cycle_time 312500
|
| 20 |
+
|
| 21 |
+
|
| 22 |
+
### Fetch Stage
|
| 23 |
+
--fetch_off_path_ops 1
|
| 24 |
+
|
| 25 |
+
#### ICache
|
| 26 |
+
--icache_size 32768
|
| 27 |
+
--icache_assoc 8
|
| 28 |
+
--icache_line_size 64
|
| 29 |
+
|
| 30 |
+
### Uop Cache
|
| 31 |
+
# inclusive w/ L1i
|
| 32 |
+
--uop_cache_enable 1
|
| 33 |
+
--uop_cache_width 8
|
| 34 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 35 |
+
--uop_cache_assoc 8
|
| 36 |
+
--iprf_on_uop_cache_hit 1
|
| 37 |
+
|
| 38 |
+
### Branch Predictor
|
| 39 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 40 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 41 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 42 |
+
--bp_mech tage64k
|
| 43 |
+
|
| 44 |
+
|
| 45 |
+
#### BTB
|
| 46 |
+
|
| 47 |
+
# TODO
|
| 48 |
+
# multi-level BTB
|
| 49 |
+
# 128 entry L0 BTB
|
| 50 |
+
# 6144 entry L1 BTB
|
| 51 |
+
# 12888 entry L2 BTB
|
| 52 |
+
# ~2 entry Return Stack
|
| 53 |
+
# roughly 2x8192 for now
|
| 54 |
+
# BTB model to use.
|
| 55 |
+
--btb_mech generic
|
| 56 |
+
--btb_entries 12288
|
| 57 |
+
--btb_assoc 4
|
| 58 |
+
--btb_main_latency 3
|
| 59 |
+
--btb_l0_present 1
|
| 60 |
+
--btb_l0_entries 128
|
| 61 |
+
--btb_l0_assoc 4
|
| 62 |
+
--btb_l0_latency 1
|
| 63 |
+
--btb_l1_present 1
|
| 64 |
+
--btb_l1_entries 6144
|
| 65 |
+
--btb_l1_assoc 4
|
| 66 |
+
--btb_l1_latency 2
|
| 67 |
+
|
| 68 |
+
# Allow the BTB to be updated by off path ops.
|
| 69 |
+
--btb_off_path_writes 1
|
| 70 |
+
|
| 71 |
+
# NT branches are not inserted in BTB, but do not trigger resteer
|
| 72 |
+
# since we continue without a control flow change
|
| 73 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 74 |
+
|
| 75 |
+
#### CRS
|
| 76 |
+
|
| 77 |
+
# Enable return stack
|
| 78 |
+
--enable_crs 1
|
| 79 |
+
--crs_entries 128
|
| 80 |
+
--crs_realistic 1
|
| 81 |
+
|
| 82 |
+
### iBP
|
| 83 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 84 |
+
--ibtb_mech tc_tagged
|
| 85 |
+
# iBTB Model. tc_tagless, tc_tagged, tc_hybrid.
|
| 86 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 87 |
+
--tc_entries 4096
|
| 88 |
+
--tc_assoc 4
|
| 89 |
+
|
| 90 |
+
### Decode Stage
|
| 91 |
+
--decode_width 6
|
| 92 |
+
--decode_cycles 5
|
| 93 |
+
|
| 94 |
+
### Instruction Decode Queue
|
| 95 |
+
--idq_size 144
|
| 96 |
+
|
| 97 |
+
### Map Stage
|
| 98 |
+
--map_cycles 5
|
| 99 |
+
|
| 100 |
+
# register renaming table
|
| 101 |
+
--reg_renaming_scheme 1
|
| 102 |
+
--reg_table_integer_physical_size 280
|
| 103 |
+
--reg_table_vector_physical_size 332
|
| 104 |
+
|
| 105 |
+
### Issue Stage
|
| 106 |
+
|
| 107 |
+
# Max number of instructions to be renamed, and issued per cycle.
|
| 108 |
+
--issue_width 6
|
| 109 |
+
|
| 110 |
+
--rs_fill_width 0
|
| 111 |
+
# rs_sizes ~205 in total, and they are split into three different reservation stations (RS1, RS2, RS3) where each has 97, 70, 38 entries respectively
|
| 112 |
+
# original architecture
|
| 113 |
+
# RS1 connected to port 0,1,5,6,10
|
| 114 |
+
# RS2 connected to port 2,3,11
|
| 115 |
+
# RS3 connected to port 7,8,4,9
|
| 116 |
+
# scarab does not split ST AGU port and ST port, merge them
|
| 117 |
+
# adjusted architecture to scarab ST AGU (port 4 and 9 removed. rs_size reduced to 186 from 205)
|
| 118 |
+
# RS1 connected to port 0,1,4,5,8
|
| 119 |
+
# RS2 connected to port 2,3,9
|
| 120 |
+
# RS3 connected to port 6,7 (port 4,9 removed, entries reduced to 19 from 38)
|
| 121 |
+
--rs_sizes 97 70 19
|
| 122 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 123 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 124 |
+
|
| 125 |
+
### Exec Stage
|
| 126 |
+
|
| 127 |
+
### DCache
|
| 128 |
+
--dcache_size 49152
|
| 129 |
+
--dcache_read_ports 1
|
| 130 |
+
--dcache_write_ports 1
|
| 131 |
+
--dcache_banks 8
|
| 132 |
+
--dcache_assoc 12
|
| 133 |
+
--dcache_line_size 64
|
| 134 |
+
--dcache_cycles 5
|
| 135 |
+
|
| 136 |
+
### Reorder/Retire Stage
|
| 137 |
+
|
| 138 |
+
# Max number of instructions to be retired per cycle.
|
| 139 |
+
--node_ret_width 8
|
| 140 |
+
--node_table_size 512
|
| 141 |
+
|
| 142 |
+
# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does
|
| 143 |
+
--stores_do_not_block_window 1
|
| 144 |
+
|
| 145 |
+
# TODO: confirm what this knob does
|
| 146 |
+
--prefs_do_not_block_window 1
|
| 147 |
+
|
| 148 |
+
|
| 149 |
+
## Uncore
|
| 150 |
+
|
| 151 |
+
### Mid-level cache
|
| 152 |
+
|
| 153 |
+
# Enable use of a midlevel cache between i/d and L1
|
| 154 |
+
# client 1.25 MiB (1310720 bytes) per core, 8-way, 15 cycles
|
| 155 |
+
# server 2 MiB (2097000 bytes) per core, 8-way, 16 cycles
|
| 156 |
+
--mlc_present 1
|
| 157 |
+
--mlc_size 2097000
|
| 158 |
+
--mlc_assoc 8
|
| 159 |
+
--mlc_cycles 16
|
| 160 |
+
|
| 161 |
+
|
| 162 |
+
### LLC
|
| 163 |
+
# 3 MiB per core, 16-way
|
| 164 |
+
--l1_size 3145728
|
| 165 |
+
--l1_banks 8
|
| 166 |
+
--l1_cycles 36 // just a guess
|
| 167 |
+
--l1_assoc 16
|
| 168 |
+
--l1_line_size 64
|
| 169 |
+
--l1_interleave_factor 64
|
| 170 |
+
|
| 171 |
+
|
| 172 |
+
### prefetcher
|
| 173 |
+
# Kept same as Kaby Lake
|
| 174 |
+
--pref_framework_on 1
|
| 175 |
+
--pref_stream_on 1
|
| 176 |
+
--pref_train_on_pref_misses 0
|
| 177 |
+
--pref_oracle_train 0
|
| 178 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 179 |
+
|
| 180 |
+
--stream_length 64
|
| 181 |
+
--stream_prefetch_n 4
|
| 182 |
+
--stream_start_dis 1
|
| 183 |
+
--stream_train_num 4
|
| 184 |
+
--stream_create_on_dc_miss 0
|
| 185 |
+
--stream_create_on_l1_miss 1
|
| 186 |
+
|
| 187 |
+
--pref_throttlefb_on=1
|
| 188 |
+
--pref_acc_thresh_1=0.75
|
| 189 |
+
--pref_acc_thresh_2=0.4
|
| 190 |
+
--pref_acc_thresh_3=0.4
|
| 191 |
+
--pref_timely_thresh=0.01
|
| 192 |
+
--pref_polpf_thresh=0.005
|
| 193 |
+
--pref_update_interval=8192
|
| 194 |
+
|
| 195 |
+
--mem_req_buffer_pref_watermark 4
|
| 196 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 197 |
+
|
| 198 |
+
### Memory
|
| 199 |
+
# Kept same as Kaby Lake
|
| 200 |
+
--addr_translation random
|
| 201 |
+
|
| 202 |
+
--mem_priority_ifetch 0
|
| 203 |
+
--mem_priority_dfetch 1
|
| 204 |
+
--mem_priority_dstore 2
|
| 205 |
+
--mem_priority_iprf 3
|
| 206 |
+
--mem_priority_dprf 4
|
| 207 |
+
--mem_priority_wb 5
|
| 208 |
+
--mem_priority_wb_nodirty 5
|
| 209 |
+
|
| 210 |
+
--mem_req_buffer_entries 32
|
| 211 |
+
--bus_width_in_bytes 8
|
| 212 |
+
|
| 213 |
+
--ramulator_standard DDR4
|
| 214 |
+
--ramulator_speed DDR4_2400R
|
| 215 |
+
--ramulator_org DDR4_8Gb_x8
|
| 216 |
+
--ramulator_channels 1
|
| 217 |
+
--ramulator_ranks 1
|
| 218 |
+
--ramulator_bankgroups 4
|
| 219 |
+
--ramulator_banks 4
|
| 220 |
+
--ramulator_chip_width 8
|
| 221 |
+
--ramulator_rows 65536
|
| 222 |
+
--ramulator_cols 1024
|
| 223 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 224 |
+
--ramulator_readq_entries 32
|
| 225 |
+
--ramulator_writeq_entries 32
|
| 226 |
+
--ramulator_record_cmd_trace FALSE
|
| 227 |
+
--ramulator_print_cmd_trace FALSE
|
| 228 |
+
--ramulator_tCK 833333
|
| 229 |
+
--ramulator_tCL 16
|
| 230 |
+
--ramulator_tCCD 6
|
| 231 |
+
--ramulator_tCCDS 4
|
| 232 |
+
--ramulator_tCCDL 6
|
| 233 |
+
--ramulator_tCWL 12
|
| 234 |
+
--ramulator_tBL 4
|
| 235 |
+
--ramulator_tWTR 9
|
| 236 |
+
--ramulator_tWTRS 3
|
| 237 |
+
--ramulator_tWTRL 9
|
| 238 |
+
--ramulator_tRP 16
|
| 239 |
+
--ramulator_tRPpb 16
|
| 240 |
+
--ramulator_tRPab 16
|
| 241 |
+
--ramulator_tRCD 16
|
| 242 |
+
--ramulator_tRCDR 16
|
| 243 |
+
--ramulator_tRCDW 16
|
| 244 |
+
--ramulator_tRAS 39
|
| 245 |
+
--dram_tech_in_nm 32
|
| 246 |
+
|
| 247 |
+
## Other
|
| 248 |
+
|
| 249 |
+
|
| 250 |
+
### Debug
|
| 251 |
+
--debug_inst_start 0
|
| 252 |
+
--debug_inst_stop -1
|
| 253 |
+
--debug_cycle_start 0
|
| 254 |
+
--debug_cycle_stop -1
|
| 255 |
+
|
| 256 |
+
|
| 257 |
+
## Stats and Params
|
| 258 |
+
--dump_params 1
|
| 259 |
+
--dump_stats 1
|
| 260 |
+
--dump_trace 0
|
| 261 |
+
|
| 262 |
+
####################################
|
| 263 |
+
--set_off_path_confirmed 1
|
| 264 |
+
|
| 265 |
+
--order_beyond_bus 1
|
| 266 |
+
|
| 267 |
+
--mem_ooo_stores 1
|
| 268 |
+
--mem_obey_store_dep 1
|
sssp_facebook/fingerprint/run_4/PARAMS.out
ADDED
|
@@ -0,0 +1,1102 @@
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|
|
| 1 |
+
--mode trace_bbv_distributed
|
| 2 |
+
--model cmp
|
| 3 |
+
--frontend memtrace
|
| 4 |
+
--sim_limit none
|
| 5 |
+
--memtrace_roi_begin 40000001
|
| 6 |
+
--memtrace_roi_end 50000000
|
| 7 |
+
--use_fetched_count 1
|
| 8 |
+
--dump_params 1
|
| 9 |
+
--dump_stats 1
|
| 10 |
+
--dump_trace 0
|
| 11 |
+
--trace_bbv_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.4
|
| 12 |
+
--trace_footprint_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.4
|
| 13 |
+
--segment_instr_count 10000000
|
| 14 |
+
--mlc_present 1
|
| 15 |
+
--mlc_size 2097000
|
| 16 |
+
--mlc_assoc 8
|
| 17 |
+
--mlc_cycles 16
|
| 18 |
+
--l1_size 3145728
|
| 19 |
+
--l1_assoc 16
|
| 20 |
+
--l1_line_size 64
|
| 21 |
+
--l1_cycles 36 // just a guess
|
| 22 |
+
--l1_banks 8
|
| 23 |
+
--l1_interleave_factor 64
|
| 24 |
+
--addr_translation random
|
| 25 |
+
--icache_size 32768
|
| 26 |
+
--icache_assoc 8
|
| 27 |
+
--icache_line_size 64
|
| 28 |
+
--uop_cache_enable 1
|
| 29 |
+
--uop_cache_width 8
|
| 30 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 31 |
+
--uop_cache_assoc 8
|
| 32 |
+
--iprf_on_uop_cache_hit 1
|
| 33 |
+
--dcache_size 49152
|
| 34 |
+
--dcache_assoc 12
|
| 35 |
+
--dcache_line_size 64
|
| 36 |
+
--dcache_cycles 5
|
| 37 |
+
--dcache_read_ports 1
|
| 38 |
+
--dcache_write_ports 1
|
| 39 |
+
--dcache_banks 8
|
| 40 |
+
--mem_ooo_stores 1
|
| 41 |
+
--mem_obey_store_dep 1
|
| 42 |
+
--mem_req_buffer_entries 32
|
| 43 |
+
--mem_priority_ifetch 0
|
| 44 |
+
--mem_priority_dfetch 1
|
| 45 |
+
--mem_priority_dstore 2
|
| 46 |
+
--mem_priority_iprf 3
|
| 47 |
+
--mem_priority_dprf 4
|
| 48 |
+
--mem_priority_wb 5
|
| 49 |
+
--mem_priority_wb_nodirty 5
|
| 50 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 51 |
+
--mem_req_buffer_pref_watermark 4
|
| 52 |
+
--order_beyond_bus 1
|
| 53 |
+
--set_off_path_confirmed 1
|
| 54 |
+
--ramulator_standard DDR4
|
| 55 |
+
--ramulator_speed DDR4_2400R
|
| 56 |
+
--ramulator_org DDR4_8Gb_x8
|
| 57 |
+
--ramulator_channels 1
|
| 58 |
+
--ramulator_ranks 1
|
| 59 |
+
--ramulator_bankgroups 4
|
| 60 |
+
--ramulator_banks 4
|
| 61 |
+
--ramulator_chip_width 8
|
| 62 |
+
--bus_width_in_bytes 8
|
| 63 |
+
--ramulator_rows 65536
|
| 64 |
+
--ramulator_cols 1024
|
| 65 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 66 |
+
--ramulator_readq_entries 32
|
| 67 |
+
--ramulator_writeq_entries 32
|
| 68 |
+
--ramulator_record_cmd_trace FALSE
|
| 69 |
+
--ramulator_print_cmd_trace FALSE
|
| 70 |
+
--ramulator_tCK 833333
|
| 71 |
+
--ramulator_tCL 16
|
| 72 |
+
--ramulator_tCCD 6
|
| 73 |
+
--ramulator_tCCDS 4
|
| 74 |
+
--ramulator_tCCDL 6
|
| 75 |
+
--ramulator_tCWL 12
|
| 76 |
+
--ramulator_tBL 4
|
| 77 |
+
--ramulator_tWTR 9
|
| 78 |
+
--ramulator_tWTRS 3
|
| 79 |
+
--ramulator_tWTRL 9
|
| 80 |
+
--ramulator_tRP 16
|
| 81 |
+
--ramulator_tRPpb 16
|
| 82 |
+
--ramulator_tRPab 16
|
| 83 |
+
--ramulator_tRCD 16
|
| 84 |
+
--ramulator_tRCDR 16
|
| 85 |
+
--ramulator_tRCDW 16
|
| 86 |
+
--ramulator_tRAS 39
|
| 87 |
+
--dram_tech_in_nm 32
|
| 88 |
+
--chip_cycle_time 312500
|
| 89 |
+
--issue_width 6
|
| 90 |
+
--rs_fill_width 0
|
| 91 |
+
--node_table_size 512
|
| 92 |
+
--node_ret_width 8
|
| 93 |
+
--decode_width 6
|
| 94 |
+
--idq_size 144
|
| 95 |
+
--reg_renaming_scheme 1
|
| 96 |
+
--reg_table_integer_physical_size 280
|
| 97 |
+
--reg_table_vector_physical_size 332
|
| 98 |
+
--rs_sizes 97 70 19
|
| 99 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 100 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 101 |
+
--decode_cycles 5
|
| 102 |
+
--map_cycles 5
|
| 103 |
+
--fetch_off_path_ops 1
|
| 104 |
+
--stores_do_not_block_window 1
|
| 105 |
+
--prefs_do_not_block_window 1
|
| 106 |
+
--cbp_trace_r0 /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 107 |
+
--debug_cycle_start 0
|
| 108 |
+
--debug_cycle_stop -1
|
| 109 |
+
--debug_inst_start 0
|
| 110 |
+
--debug_inst_stop -1
|
| 111 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 112 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 113 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 114 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 115 |
+
--bp_mech tage64k
|
| 116 |
+
--btb_mech generic
|
| 117 |
+
--btb_entries 12288
|
| 118 |
+
--btb_assoc 4
|
| 119 |
+
--btb_off_path_writes 1
|
| 120 |
+
--btb_main_latency 3
|
| 121 |
+
--btb_l0_present 1
|
| 122 |
+
--btb_l0_entries 128
|
| 123 |
+
--btb_l0_assoc 4
|
| 124 |
+
--btb_l0_latency 1
|
| 125 |
+
--btb_l1_present 1
|
| 126 |
+
--btb_l1_entries 6144
|
| 127 |
+
--btb_l1_assoc 4
|
| 128 |
+
--btb_l1_latency 2
|
| 129 |
+
--enable_crs 1
|
| 130 |
+
--crs_entries 128
|
| 131 |
+
--crs_realistic 1
|
| 132 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 133 |
+
--ibtb_mech tc_tagged
|
| 134 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 135 |
+
--tc_entries 4096
|
| 136 |
+
--tc_assoc 4
|
| 137 |
+
--pref_stream_on 1
|
| 138 |
+
--stream_prefetch_n 4
|
| 139 |
+
--stream_start_dis 1
|
| 140 |
+
--stream_length 64
|
| 141 |
+
--stream_train_num 4
|
| 142 |
+
--stream_create_on_dc_miss 0
|
| 143 |
+
--stream_create_on_l1_miss 1
|
| 144 |
+
--pref_framework_on 1
|
| 145 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 146 |
+
--pref_train_on_pref_misses 0
|
| 147 |
+
--pref_oracle_train_on 0
|
| 148 |
+
--pref_throttlefb_on 1
|
| 149 |
+
--pref_acc_thresh_1 0.75
|
| 150 |
+
--pref_acc_thresh_2 0.4
|
| 151 |
+
--pref_acc_thresh_3 0.4
|
| 152 |
+
--pref_update_interval 8192
|
| 153 |
+
--pref_timely_thresh 0.01
|
| 154 |
+
--pref_polpf_thresh 0.005
|
| 155 |
+
1 1 1 1 1 1 1
|
| 156 |
+
|
| 157 |
+
--- Cut out everything below to use this file as PARAMS.in ---
|
| 158 |
+
|
| 159 |
+
Parameter status at compile time and values supplied on the command line:
|
| 160 |
+
|
| 161 |
+
SIM_MODE 0 trace_bbv_distributed
|
| 162 |
+
SIM_MODEL 0 cmp
|
| 163 |
+
FRONTEND FE_PIN_EXEC_DRIVEN memtrace
|
| 164 |
+
INST_LIMIT NULL
|
| 165 |
+
SIM_LIMIT "none" none
|
| 166 |
+
FORWARD_PROGRESS_LIMIT 100000000
|
| 167 |
+
FORWARD_PROGRESS_INTERVAL 10000
|
| 168 |
+
FAST_FORWARD 0
|
| 169 |
+
FAST_FORWARD_TRACE_INS 0
|
| 170 |
+
FAST_FORWARD_UNTIL_ADDR 0
|
| 171 |
+
MEMTRACE_ROI_BEGIN 0 40000001
|
| 172 |
+
MEMTRACE_ROI_END 0 50000000
|
| 173 |
+
FULL_WARMUP 0
|
| 174 |
+
WARMUP 0
|
| 175 |
+
HEARTBEAT_INTERVAL 1000000
|
| 176 |
+
NUM_HEARTBEATS 0
|
| 177 |
+
USE_FETCHED_COUNT FALSE 1
|
| 178 |
+
PERIODIC_DUMP FALSE
|
| 179 |
+
FILE_TAG ""
|
| 180 |
+
OUTPUT_DIR "."
|
| 181 |
+
STATUS_FILE NULL
|
| 182 |
+
BINDIR NULL
|
| 183 |
+
DUMP_PARAMS TRUE 1
|
| 184 |
+
DUMP_STATS TRUE 1
|
| 185 |
+
DUMP_TRACE FALSE 0
|
| 186 |
+
CLEAR_STATS "never"
|
| 187 |
+
STATS_TO_TRACE NULL
|
| 188 |
+
STAT_TRACE_FILE "stats.trace"
|
| 189 |
+
STAT_TRACE_INTERVAL "i:100000"
|
| 190 |
+
PIPEVIEW FALSE
|
| 191 |
+
PIPEVIEW_FILE "pipeview"
|
| 192 |
+
MEMVIEW FALSE
|
| 193 |
+
MEMVIEW_FILE "memview.out"
|
| 194 |
+
MEMVIEW_START "never"
|
| 195 |
+
INST_HASH_TABLE_SIZE 524288 const
|
| 196 |
+
STDOUT_FILE NULL
|
| 197 |
+
STDERR_FILE NULL
|
| 198 |
+
PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp"
|
| 199 |
+
PRINT_PID FALSE
|
| 200 |
+
USE_UNSURE_FREE_LISTS FALSE
|
| 201 |
+
OPTIMIZER2_MAX_NUM_SLAVES 64
|
| 202 |
+
OPTIMIZER2_PERFECT_MEMORYLESS FALSE
|
| 203 |
+
EXIT_COND 0
|
| 204 |
+
NUM_NOPS 0
|
| 205 |
+
NOPS_BB_START 0x5000000
|
| 206 |
+
IGNORE_BAR_FETCH FALSE
|
| 207 |
+
TRACE_BBV_OUTPUT NULL /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.4
|
| 208 |
+
TRACE_FOOTPRINT_OUTPUT "" /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.4
|
| 209 |
+
SEGMENT_INSTR_COUNT 0 10000000
|
| 210 |
+
ENABLE_SWPRF FALSE
|
| 211 |
+
MLC_PRESENT FALSE 1
|
| 212 |
+
MLC_SIZE (512 * 1024) 2097000
|
| 213 |
+
MLC_ASSOC 4 8
|
| 214 |
+
MLC_LINE_SIZE 64
|
| 215 |
+
MLC_CYCLES 12 16
|
| 216 |
+
PERFECT_MLC FALSE
|
| 217 |
+
MLC_READ_PORTS 1
|
| 218 |
+
MLC_WRITE_PORTS 1
|
| 219 |
+
MLC_BANKS 8
|
| 220 |
+
MLC_INTERLEAVE_FACTOR 64
|
| 221 |
+
MLC_CACHE_REPL_POLICY 0
|
| 222 |
+
MLC_WRITE_THROUGH FALSE
|
| 223 |
+
PREFETCH_UPDATE_LRU_MLC TRUE
|
| 224 |
+
FORCE_L1_MISS FALSE
|
| 225 |
+
L1_SIZE (4 * 1024 * 1024) 3145728
|
| 226 |
+
L1_ASSOC 8 16
|
| 227 |
+
L1_LINE_SIZE 64 64
|
| 228 |
+
L1_CYCLES 24 36 // just a guess
|
| 229 |
+
PERFECT_L1 FALSE
|
| 230 |
+
PRIVATE_L1 FALSE
|
| 231 |
+
L1_READ_PORTS 1
|
| 232 |
+
L1_WRITE_PORTS 1
|
| 233 |
+
L1_BANKS 8 8
|
| 234 |
+
L1_INTERLEAVE_FACTOR 64 64
|
| 235 |
+
L1_CACHE_REPL_POLICY 0
|
| 236 |
+
L1_WRITE_THROUGH FALSE
|
| 237 |
+
L1_IGNORE_WB FALSE
|
| 238 |
+
L1_USE_CORE_FREQ FALSE
|
| 239 |
+
MARK_L1_MISSES TRUE
|
| 240 |
+
PREFETCH_UPDATE_LRU_L1 TRUE
|
| 241 |
+
MEMORY_RANDOM_ADDR FALSE
|
| 242 |
+
VA_PAGE_SIZE_BYTES 4096
|
| 243 |
+
NUM_ADDR_NON_SIGN_EXTEND_BITS 48
|
| 244 |
+
ADDR_TRANSLATION 0 random
|
| 245 |
+
CONSTANT_MEMORY_LATENCY FALSE
|
| 246 |
+
MEMORY_CYCLES 100
|
| 247 |
+
STALL_MEM_REQS_ONLY FALSE
|
| 248 |
+
ICACHE_SIZE (64 * 1024) 32768
|
| 249 |
+
ICACHE_ASSOC 4 8
|
| 250 |
+
ICACHE_LINE_SIZE 64 64
|
| 251 |
+
PERFECT_ICACHE FALSE
|
| 252 |
+
ICACHE_READ_PORTS 1
|
| 253 |
+
ICACHE_WRITE_PORTS 1
|
| 254 |
+
ICACHE_BANKS 8
|
| 255 |
+
ICACHE_REPL 0
|
| 256 |
+
UOP_CACHE_ENABLE 1 1
|
| 257 |
+
UOP_CACHE_WIDTH 6 8
|
| 258 |
+
ALWAYS_LOOKUP_ICACHE 0
|
| 259 |
+
UOP_CACHE_INSERT_ONLY_ONPATH FALSE
|
| 260 |
+
UOP_CACHE_READ_PORTS 1
|
| 261 |
+
UOP_CACHE_LINES 384 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 262 |
+
UOP_CACHE_ASSOC 8 8
|
| 263 |
+
UOP_CACHE_MAX_IMM_DISP_LINE 4
|
| 264 |
+
IPRF_ON_UOP_CACHE_HIT FALSE 1
|
| 265 |
+
UOP_CACHE_REPL 0
|
| 266 |
+
PRIORITY_LINE_STICKINESS_PERCENT 50
|
| 267 |
+
PW_PRIORITY_LIST_FILEPATH "pw_priority_list.csv"
|
| 268 |
+
NUM_PRIORITY_PWS 10
|
| 269 |
+
PRIORITIZE_PWS_AFTER_FIRST_STICKY_UNTIL_BACKEND_STALL FALSE
|
| 270 |
+
NO_REPL_AFTER_QUEUE_SIZE 0
|
| 271 |
+
FDIP_UC_SIZE 0
|
| 272 |
+
FDIP_UC_ASSOC 4
|
| 273 |
+
FDIP_UC_INSERT_REPLPOL 0
|
| 274 |
+
MAP_STAGE_CONSUME_FROM_ICACHE_AND_UOC_SAME_CYCLE TRUE
|
| 275 |
+
UOP_QUEUE_LENGTH 7
|
| 276 |
+
DCACHE_SIZE (64 * 1024) 49152
|
| 277 |
+
DCACHE_ASSOC 1 12
|
| 278 |
+
DCACHE_LINE_SIZE 64 64
|
| 279 |
+
DCACHE_CYCLES 2 5
|
| 280 |
+
PERFECT_DCACHE FALSE
|
| 281 |
+
DCACHE_READ_PORTS 8 1
|
| 282 |
+
DCACHE_WRITE_PORTS 1 1
|
| 283 |
+
DCACHE_BANKS 1 8
|
| 284 |
+
DCACHE_INTERLEAVE_FACTOR 4
|
| 285 |
+
DCACHE_REPL 0
|
| 286 |
+
DCACHE_REPL_PREF_THRESH 1
|
| 287 |
+
MEM_OOO_STORES TRUE 1
|
| 288 |
+
MEM_OBEY_STORE_DEP TRUE 1
|
| 289 |
+
PREF_INSERT_LRU FALSE
|
| 290 |
+
PREF_INSERT_MIDDLE FALSE
|
| 291 |
+
PREF_INSERT_LOWQTR FALSE
|
| 292 |
+
PREF_INSERT_DYNACC FALSE
|
| 293 |
+
MEM_REQ_BUFFER_ENTRIES 32 32
|
| 294 |
+
PRIVATE_MSHR_ON TRUE
|
| 295 |
+
MEM_PRIORITY_IFETCH 0 0
|
| 296 |
+
MEM_PRIORITY_DFETCH 0 1
|
| 297 |
+
MEM_PRIORITY_DSTORE 0 2
|
| 298 |
+
MEM_PRIORITY_IPRF 9 3
|
| 299 |
+
MEM_PRIORITY_UOCPRF 9
|
| 300 |
+
MEM_PRIORITY_FDIPPRFON 8
|
| 301 |
+
MEM_PRIORITY_FDIPPRFOFF 9
|
| 302 |
+
MEM_PRIORITY_DPRF 10 4
|
| 303 |
+
MEM_PRIORITY_WB 0 5
|
| 304 |
+
MEM_PRIORITY_WB_NODIRTY 0 5
|
| 305 |
+
PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1
|
| 306 |
+
MEM_REQ_BUFFER_PREF_WATERMARK 0 4
|
| 307 |
+
MEM_REQ_BUFFER_WB_VALVE 2
|
| 308 |
+
MEM_L1_FILL_QUEUE_ENTRIES 32
|
| 309 |
+
MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE
|
| 310 |
+
MEM_MEM_QUEUE_PARTITION_ENABLE FALSE
|
| 311 |
+
MEM_BUS_OUT_QUEUE_AS_FIFO TRUE
|
| 312 |
+
OLDEST_FIRST_TO_MEM_QUEUE TRUE
|
| 313 |
+
ROUND_ROBIN_TO_MEM_QUEUE FALSE
|
| 314 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE FALSE
|
| 315 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0
|
| 316 |
+
L1_CYCLE_TIME 312500
|
| 317 |
+
MLCQ_TO_L1Q_TRANSFER_LATENCY 1
|
| 318 |
+
L1Q_TO_FSB_TRANSFER_LATENCY 1
|
| 319 |
+
PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE
|
| 320 |
+
KICKOUT_PREFETCHES FALSE
|
| 321 |
+
KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE
|
| 322 |
+
KICKOUT_OLDEST_PREFETCH FALSE
|
| 323 |
+
KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE
|
| 324 |
+
ORDER_BEYOND_BUS FALSE 1
|
| 325 |
+
ALL_FIFO_QUEUES FALSE
|
| 326 |
+
QUEUE_MLC_SIZE 0
|
| 327 |
+
QUEUE_L1_SIZE 0
|
| 328 |
+
QUEUE_BUS_OUT_SIZE 0
|
| 329 |
+
QUEUE_CORE_FILL_SIZE 0
|
| 330 |
+
ALLOW_TYPE_MATCHES FALSE
|
| 331 |
+
STREAM_PREFETCH_ON FALSE
|
| 332 |
+
DC_PREF_CACHE_ENABLE FALSE
|
| 333 |
+
DC_PREF_CACHE_CYCLE 0
|
| 334 |
+
PREF_INSERT_DCACHE_IMM TRUE
|
| 335 |
+
DC_PREF_CACHE_SIZE (64 * 1024)
|
| 336 |
+
DC_PREF_CACHE_ASSOC 4
|
| 337 |
+
DC_PREF_ONLY_L1HIT FALSE
|
| 338 |
+
PREF_CACHE_USE_RDY_CYCLE FALSE
|
| 339 |
+
IC_PREF_CACHE_ENABLE FALSE
|
| 340 |
+
IC_PREF_CACHE_SIZE (64 * 1024)
|
| 341 |
+
IC_PREF_CACHE_ASSOC 4
|
| 342 |
+
L1_PREF_CACHE_ENABLE FALSE
|
| 343 |
+
L1_PREF_CACHE_SIZE (1024 * 1024)
|
| 344 |
+
L1_PREF_CACHE_ASSOC 8
|
| 345 |
+
SET_OFF_PATH_CONFIRMED FALSE 1
|
| 346 |
+
USE_CONFIRMED_OFF FALSE
|
| 347 |
+
PREFCACHE_MOVE_OFFPATH FALSE
|
| 348 |
+
CACHE_STAT_ENABLE FALSE
|
| 349 |
+
PREF_DCACHE_HIT_FILL_L1 TRUE
|
| 350 |
+
PREF_ICACHE_HIT_FILL_L1 TRUE
|
| 351 |
+
CRITICAL_ACCESS_PLOT_ENABLE FALSE
|
| 352 |
+
CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat"
|
| 353 |
+
ROUND_ROBIN_TO_L1 FALSE
|
| 354 |
+
PREF_I_TOGETHER FALSE
|
| 355 |
+
ONE_MORE_CACHE_LINE_ENABLE FALSE
|
| 356 |
+
L1_STATIC_PARTITION_ENABLE 0
|
| 357 |
+
L1_STATIC_PARTITION NULL
|
| 358 |
+
L1_DYNAMIC_PARTITION_ENABLE FALSE
|
| 359 |
+
L1_DYNAMIC_PARTITION_POLICY 0
|
| 360 |
+
PARTITION_UMON_DSS_PREF_ENABLE FALSE
|
| 361 |
+
L1_CACHE_HIT_POSITION_COLLECT FALSE
|
| 362 |
+
L1_PART_ON FALSE
|
| 363 |
+
L1_PART_TRIGGER "c:1000000"
|
| 364 |
+
L1_PART_START "t:0"
|
| 365 |
+
L1_PART_WARMUP FALSE
|
| 366 |
+
L1_PART_SHADOW_WARMUP FALSE
|
| 367 |
+
L1_PART_METRIC 0
|
| 368 |
+
L1_PART_SEARCH 0
|
| 369 |
+
L1_PART_USE_STALLING TRUE
|
| 370 |
+
L1_PART_FILL_DELAY 0
|
| 371 |
+
L1_SHADOW_TAGS_MODULO 1
|
| 372 |
+
HIER_MSHR_ON FALSE
|
| 373 |
+
PERF_PRED_ENABLE FALSE
|
| 374 |
+
PERF_PRED_MECH PERF_PRED_CP
|
| 375 |
+
PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY
|
| 376 |
+
PERF_PRED_COUNT_ALL FALSE
|
| 377 |
+
PERF_PRED_COUNT_INST_MISSES TRUE
|
| 378 |
+
PERF_PRED_COUNT_PREFETCHES FALSE
|
| 379 |
+
PERF_PRED_COUNT_OFFPATH_REQS FALSE
|
| 380 |
+
PERF_PRED_COUNT_BW_REQS TRUE
|
| 381 |
+
PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE
|
| 382 |
+
PERF_PRED_SLACK_PERIOD_SIZE 32
|
| 383 |
+
PERF_PRED_REQS_FINISH_AT_FILL FALSE
|
| 384 |
+
PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE
|
| 385 |
+
PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE
|
| 386 |
+
DUMB_MODEL_AVG_REQ_DISTANCE 100
|
| 387 |
+
DUMB_MODEL_RANDOMIZE_DISTANCE FALSE
|
| 388 |
+
DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL
|
| 389 |
+
DUMB_MODEL_AVG_ROW_HITS 1
|
| 390 |
+
DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL
|
| 391 |
+
DUMB_MODEL_MLP 1
|
| 392 |
+
DUMB_MODEL_MLP_PER_CORE NULL
|
| 393 |
+
RAMULATOR_STANDARD "DDR4" DDR4
|
| 394 |
+
RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R
|
| 395 |
+
RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8
|
| 396 |
+
RAMULATOR_CHANNELS 1 1
|
| 397 |
+
RAMULATOR_RANKS 1 1
|
| 398 |
+
RAMULATOR_BANKGROUPS 4 4
|
| 399 |
+
RAMULATOR_BANKS 4 4
|
| 400 |
+
RAMULATOR_CHIP_WIDTH 8 8
|
| 401 |
+
BUS_WIDTH_IN_BYTES 8 8
|
| 402 |
+
RAMULATOR_ROWS 65536 65536
|
| 403 |
+
RAMULATOR_COLS 1024 1024
|
| 404 |
+
RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap
|
| 405 |
+
RAMULATOR_READQ_ENTRIES 32 32
|
| 406 |
+
RAMULATOR_WRITEQ_ENTRIES 32 32
|
| 407 |
+
RAMULATOR_REC_CMD_TRACE "off" FALSE
|
| 408 |
+
RAMULATOR_PRINT_CMD_TRACE "off" FALSE
|
| 409 |
+
RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on"
|
| 410 |
+
RAMULATOR_TCK 833333 833333
|
| 411 |
+
RAMULATOR_TCL 16 16
|
| 412 |
+
RAMULATOR_TCCD 6 6
|
| 413 |
+
RAMULATOR_TCCDS 4 4
|
| 414 |
+
RAMULATOR_TCCDL 6 6
|
| 415 |
+
RAMULATOR_TCWL 12 12
|
| 416 |
+
RAMULATOR_TBL 4 4
|
| 417 |
+
RAMULATOR_TWTR 9 9
|
| 418 |
+
RAMULATOR_TWTRS 3 3
|
| 419 |
+
RAMULATOR_TWTRL 9 9
|
| 420 |
+
RAMULATOR_TRP 16 16
|
| 421 |
+
RAMULATOR_TRPpb 16 16
|
| 422 |
+
RAMULATOR_TRPab 16 16
|
| 423 |
+
RAMULATOR_TRCD 16 16
|
| 424 |
+
RAMULATOR_TRCDR 16 16
|
| 425 |
+
RAMULATOR_TRCDW 16 16
|
| 426 |
+
RAMULATOR_TRAS 39 39
|
| 427 |
+
DRAM_TECH_IN_NM 32 32
|
| 428 |
+
DVFS_ON FALSE
|
| 429 |
+
DVFS_METRIC DVFS_METRIC_NUM_ELEMS
|
| 430 |
+
DVFS_CONFIGS NULL
|
| 431 |
+
DVFS_CONFIG_FILE NULL
|
| 432 |
+
DVFS_START "t:0"
|
| 433 |
+
DVFS_PERIOD "t:312500000000"
|
| 434 |
+
DVFS_LOG TRUE
|
| 435 |
+
DVFS_INDIVIDUAL_CORES FALSE
|
| 436 |
+
DVFS_CHIP_LEVEL FALSE
|
| 437 |
+
DVFS_STATIC NULL
|
| 438 |
+
DVFS_FORCE_CONFIG NULL
|
| 439 |
+
DVFS_REPLAY_CONFIG_TRACE NULL
|
| 440 |
+
DVFS_USE_ORACLE FALSE
|
| 441 |
+
DVFS_USE_BW_SHARING FALSE
|
| 442 |
+
DVFS_USE_DRAM_SHARING FALSE
|
| 443 |
+
DVFS_USE_STALL_TIME FALSE
|
| 444 |
+
DVFS_DRAM_SHARING_SOLVER_BIN NULL
|
| 445 |
+
DVFS_DRAM_SHARING_SOLVER_STRICT TRUE
|
| 446 |
+
DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95
|
| 447 |
+
DVFS_BW_SHARING_MAX_REQS 28.0
|
| 448 |
+
DVFS_BW_SHARING_MAX_RW_COST 0.25
|
| 449 |
+
DVFS_BW_SHARING_NO_PREF_STALL TRUE
|
| 450 |
+
DVFS_BW_SHARING_CRIT_STATS TRUE
|
| 451 |
+
DVFS_COUNT_L1_ACCESS_STALL FALSE
|
| 452 |
+
NUM_CORES 1
|
| 453 |
+
CHIP_CYCLE_TIME 312500 312500
|
| 454 |
+
CORE_0_CYCLE_TIME 312500
|
| 455 |
+
CORE_1_CYCLE_TIME 312500
|
| 456 |
+
CORE_2_CYCLE_TIME 312500
|
| 457 |
+
CORE_3_CYCLE_TIME 312500
|
| 458 |
+
CORE_4_CYCLE_TIME 312500
|
| 459 |
+
CORE_5_CYCLE_TIME 312500
|
| 460 |
+
CORE_6_CYCLE_TIME 312500
|
| 461 |
+
CORE_7_CYCLE_TIME 312500
|
| 462 |
+
CORE_8_CYCLE_TIME 312500
|
| 463 |
+
CORE_9_CYCLE_TIME 312500
|
| 464 |
+
CORE_10_CYCLE_TIME 312500
|
| 465 |
+
CORE_11_CYCLE_TIME 312500
|
| 466 |
+
CORE_12_CYCLE_TIME 312500
|
| 467 |
+
CORE_13_CYCLE_TIME 312500
|
| 468 |
+
CORE_14_CYCLE_TIME 312500
|
| 469 |
+
CORE_15_CYCLE_TIME 312500
|
| 470 |
+
CORE_16_CYCLE_TIME 312500
|
| 471 |
+
CORE_17_CYCLE_TIME 312500
|
| 472 |
+
CORE_18_CYCLE_TIME 312500
|
| 473 |
+
CORE_19_CYCLE_TIME 312500
|
| 474 |
+
CORE_20_CYCLE_TIME 312500
|
| 475 |
+
CORE_21_CYCLE_TIME 312500
|
| 476 |
+
CORE_22_CYCLE_TIME 312500
|
| 477 |
+
CORE_23_CYCLE_TIME 312500
|
| 478 |
+
CORE_24_CYCLE_TIME 312500
|
| 479 |
+
CORE_25_CYCLE_TIME 312500
|
| 480 |
+
CORE_26_CYCLE_TIME 312500
|
| 481 |
+
CORE_27_CYCLE_TIME 312500
|
| 482 |
+
CORE_28_CYCLE_TIME 312500
|
| 483 |
+
CORE_29_CYCLE_TIME 312500
|
| 484 |
+
CORE_30_CYCLE_TIME 312500
|
| 485 |
+
CORE_31_CYCLE_TIME 312500
|
| 486 |
+
CORE_32_CYCLE_TIME 312500
|
| 487 |
+
CORE_33_CYCLE_TIME 312500
|
| 488 |
+
CORE_34_CYCLE_TIME 312500
|
| 489 |
+
CORE_35_CYCLE_TIME 312500
|
| 490 |
+
CORE_36_CYCLE_TIME 312500
|
| 491 |
+
CORE_37_CYCLE_TIME 312500
|
| 492 |
+
CORE_38_CYCLE_TIME 312500
|
| 493 |
+
CORE_39_CYCLE_TIME 312500
|
| 494 |
+
CORE_40_CYCLE_TIME 312500
|
| 495 |
+
CORE_41_CYCLE_TIME 312500
|
| 496 |
+
CORE_42_CYCLE_TIME 312500
|
| 497 |
+
CORE_43_CYCLE_TIME 312500
|
| 498 |
+
CORE_44_CYCLE_TIME 312500
|
| 499 |
+
CORE_45_CYCLE_TIME 312500
|
| 500 |
+
CORE_46_CYCLE_TIME 312500
|
| 501 |
+
CORE_47_CYCLE_TIME 312500
|
| 502 |
+
CORE_48_CYCLE_TIME 312500
|
| 503 |
+
CORE_49_CYCLE_TIME 312500
|
| 504 |
+
CORE_50_CYCLE_TIME 312500
|
| 505 |
+
CORE_51_CYCLE_TIME 312500
|
| 506 |
+
CORE_52_CYCLE_TIME 312500
|
| 507 |
+
CORE_53_CYCLE_TIME 312500
|
| 508 |
+
CORE_54_CYCLE_TIME 312500
|
| 509 |
+
CORE_55_CYCLE_TIME 312500
|
| 510 |
+
CORE_56_CYCLE_TIME 312500
|
| 511 |
+
CORE_57_CYCLE_TIME 312500
|
| 512 |
+
CORE_58_CYCLE_TIME 312500
|
| 513 |
+
CORE_59_CYCLE_TIME 312500
|
| 514 |
+
CORE_60_CYCLE_TIME 312500
|
| 515 |
+
CORE_61_CYCLE_TIME 312500
|
| 516 |
+
CORE_62_CYCLE_TIME 312500
|
| 517 |
+
CORE_63_CYCLE_TIME 312500
|
| 518 |
+
TOPDOWN_FU_EXEC_FEW 0
|
| 519 |
+
ISSUE_WIDTH 4 6
|
| 520 |
+
RS_FILL_WIDTH 8 0
|
| 521 |
+
NODE_TABLE_SIZE 256 512
|
| 522 |
+
NODE_RET_WIDTH 4 8
|
| 523 |
+
NODE_RETIRE_RATE 10
|
| 524 |
+
DECODE_WIDTH 4 6
|
| 525 |
+
IDQ_SIZE 140 144
|
| 526 |
+
REG_RENAMING_SCHEME 0 1
|
| 527 |
+
REG_TABLE_INTEGER_PHYSICAL_SIZE 256 280
|
| 528 |
+
REG_TABLE_VECTOR_PHYSICAL_SIZE 256 332
|
| 529 |
+
REG_TABLE_INTEGER_VIRTUAL_SIZE 256
|
| 530 |
+
REG_TABLE_VECTOR_VIRTUAL_SIZE 256
|
| 531 |
+
REG_RENAMING_MOVE_ELIMINATE FALSE
|
| 532 |
+
NODE_ISSUE_QUEUE_DISPATCH_SCHEME 0
|
| 533 |
+
NODE_ISSUE_QUEUE_SCHEDULE_SCHEME 0
|
| 534 |
+
ISSUE_QUEUE_PARALLEL_PICK FALSE
|
| 535 |
+
RS_SIZES "256" 97 70 19
|
| 536 |
+
RS_CONNECTIONS "xF" b0100110011 b1000001100 b0011000000
|
| 537 |
+
FU_TYPES "0, 0, 0, 0" b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 538 |
+
LSQ_ENABLE TRUE
|
| 539 |
+
LOAD_QUEUE_ENTRY_NUM 128
|
| 540 |
+
STORE_QUEUE_ENTRY_NUM 72
|
| 541 |
+
DECODE_CYCLES 1 5
|
| 542 |
+
MAP_CYCLES 1 5
|
| 543 |
+
ICACHE_LATENCY 3
|
| 544 |
+
EXTRA_REDIRECT_CYCLES 0
|
| 545 |
+
EXTRA_RECOVERY_CYCLES 0
|
| 546 |
+
EXTRA_CALLSYS_CYCLES 20 const
|
| 547 |
+
DIE_ON_CALLSYS FALSE
|
| 548 |
+
DIE_ON_RET_STALL_THRESH 0
|
| 549 |
+
DIE_ON_RET_STALL_CORE 0
|
| 550 |
+
DIE_ON_MEM_BLOCK_THRESH 0
|
| 551 |
+
DIE_ON_MEM_BLOCK_CORE 0
|
| 552 |
+
ICACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 553 |
+
UOP_CACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 554 |
+
FETCH_OFF_PATH_OPS TRUE 1
|
| 555 |
+
WP_COLLECT_STATS TRUE
|
| 556 |
+
OP_INV_DELAY 1
|
| 557 |
+
OP_NOP_DELAY 1
|
| 558 |
+
OP_CF_DELAY 1
|
| 559 |
+
OP_MOV_DELAY 1
|
| 560 |
+
OP_CMOV_DELAY 1
|
| 561 |
+
OP_LDA_DELAY 1
|
| 562 |
+
OP_ILD_DELAY 1
|
| 563 |
+
OP_IST_DELAY 1
|
| 564 |
+
OP_IADD_DELAY 1
|
| 565 |
+
OP_IMUL_DELAY 3
|
| 566 |
+
OP_IDIV_DELAY -20
|
| 567 |
+
OP_ICMP_DELAY 1
|
| 568 |
+
OP_LOGIC_DELAY 1
|
| 569 |
+
OP_SHIFT_DELAY 1
|
| 570 |
+
OP_FLD_DELAY 1
|
| 571 |
+
OP_FST_DELAY 1
|
| 572 |
+
OP_FCVT_DELAY 3
|
| 573 |
+
OP_FADD_DELAY 3
|
| 574 |
+
OP_FMUL_DELAY 5
|
| 575 |
+
OP_FMA_DELAY 5
|
| 576 |
+
OP_FDIV_DELAY -20
|
| 577 |
+
OP_FCMP_DELAY 3
|
| 578 |
+
OP_FCMOV_DELAY 1
|
| 579 |
+
OP_GATHER_DELAY 12
|
| 580 |
+
OP_SCATTER_DELAY 18
|
| 581 |
+
OP_PIPELINED_FAST_DELAY 2
|
| 582 |
+
OP_PIPELINED_MEDIUM_DELAY 5
|
| 583 |
+
OP_PIPELINED_SLOW_DELAY 10
|
| 584 |
+
OP_NOTPIPELINED_MEDIUM_DELAY -5
|
| 585 |
+
OP_NOTPIPELINED_SLOW_DELAY -20
|
| 586 |
+
OP_NOTPIPELINED_VERY_SLOW_DELAY -100
|
| 587 |
+
UNIFORM_OP_DELAY 0
|
| 588 |
+
STALL_ON_WAIT_MEM TRUE
|
| 589 |
+
STORES_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 590 |
+
PREFS_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 591 |
+
OBEY_REG_DEP TRUE
|
| 592 |
+
TRACK_L1_MISS_DEPS FALSE
|
| 593 |
+
CBP_TRACE_R0 NULL /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 594 |
+
CBP_TRACE_R1 NULL
|
| 595 |
+
CBP_TRACE_R2 NULL
|
| 596 |
+
CBP_TRACE_R3 NULL
|
| 597 |
+
CBP_TRACE_R4 NULL
|
| 598 |
+
CBP_TRACE_R5 NULL
|
| 599 |
+
CBP_TRACE_R6 NULL
|
| 600 |
+
CBP_TRACE_R7 NULL
|
| 601 |
+
CBP_TRACE_R8 NULL
|
| 602 |
+
CBP_TRACE_R9 NULL
|
| 603 |
+
CBP_TRACE_R10 NULL
|
| 604 |
+
CBP_TRACE_R11 NULL
|
| 605 |
+
CBP_TRACE_R12 NULL
|
| 606 |
+
CBP_TRACE_R13 NULL
|
| 607 |
+
CBP_TRACE_R14 NULL
|
| 608 |
+
CBP_TRACE_R15 NULL
|
| 609 |
+
CBP_TRACE_R16 NULL
|
| 610 |
+
CBP_TRACE_R17 NULL
|
| 611 |
+
CBP_TRACE_R18 NULL
|
| 612 |
+
CBP_TRACE_R19 NULL
|
| 613 |
+
CBP_TRACE_R20 NULL
|
| 614 |
+
CBP_TRACE_R21 NULL
|
| 615 |
+
CBP_TRACE_R22 NULL
|
| 616 |
+
CBP_TRACE_R23 NULL
|
| 617 |
+
CBP_TRACE_R24 NULL
|
| 618 |
+
CBP_TRACE_R25 NULL
|
| 619 |
+
CBP_TRACE_R26 NULL
|
| 620 |
+
CBP_TRACE_R27 NULL
|
| 621 |
+
CBP_TRACE_R28 NULL
|
| 622 |
+
CBP_TRACE_R29 NULL
|
| 623 |
+
CBP_TRACE_R30 NULL
|
| 624 |
+
CBP_TRACE_R31 NULL
|
| 625 |
+
CBP_TRACE_R32 NULL
|
| 626 |
+
CBP_TRACE_R33 NULL
|
| 627 |
+
CBP_TRACE_R34 NULL
|
| 628 |
+
CBP_TRACE_R35 NULL
|
| 629 |
+
CBP_TRACE_R36 NULL
|
| 630 |
+
CBP_TRACE_R37 NULL
|
| 631 |
+
CBP_TRACE_R38 NULL
|
| 632 |
+
CBP_TRACE_R39 NULL
|
| 633 |
+
CBP_TRACE_R40 NULL
|
| 634 |
+
CBP_TRACE_R41 NULL
|
| 635 |
+
CBP_TRACE_R42 NULL
|
| 636 |
+
CBP_TRACE_R43 NULL
|
| 637 |
+
CBP_TRACE_R44 NULL
|
| 638 |
+
CBP_TRACE_R45 NULL
|
| 639 |
+
CBP_TRACE_R46 NULL
|
| 640 |
+
CBP_TRACE_R47 NULL
|
| 641 |
+
CBP_TRACE_R48 NULL
|
| 642 |
+
CBP_TRACE_R49 NULL
|
| 643 |
+
CBP_TRACE_R50 NULL
|
| 644 |
+
CBP_TRACE_R51 NULL
|
| 645 |
+
CBP_TRACE_R52 NULL
|
| 646 |
+
CBP_TRACE_R53 NULL
|
| 647 |
+
CBP_TRACE_R54 NULL
|
| 648 |
+
CBP_TRACE_R55 NULL
|
| 649 |
+
CBP_TRACE_R56 NULL
|
| 650 |
+
CBP_TRACE_R57 NULL
|
| 651 |
+
CBP_TRACE_R58 NULL
|
| 652 |
+
CBP_TRACE_R59 NULL
|
| 653 |
+
CBP_TRACE_R60 NULL
|
| 654 |
+
CBP_TRACE_R61 NULL
|
| 655 |
+
CBP_TRACE_R62 NULL
|
| 656 |
+
CBP_TRACE_R63 NULL
|
| 657 |
+
FE_FTQ_BLOCK_NUM 32
|
| 658 |
+
FE_FTQ_TAKEN_CFS_PER_CYCLE 2
|
| 659 |
+
FE_FTQ_FT_PER_CYCLE 1
|
| 660 |
+
DUMB_CORE_ON FALSE
|
| 661 |
+
DUMB_CORE 1
|
| 662 |
+
DCACHE_MISS_RATE 10
|
| 663 |
+
L1_MISS_RATE 10
|
| 664 |
+
TRACE_BUF_SIZE 0
|
| 665 |
+
PERFECT_CONFIDENCE FALSE
|
| 666 |
+
CONFIDENCE_ENABLE FALSE
|
| 667 |
+
CONFIDENCE_MECH 0
|
| 668 |
+
CONF_OFF_PATH_THRESHOLD 15
|
| 669 |
+
CONF_OFF_PATH_INC 5
|
| 670 |
+
CONF_BTB_MISS_BP_TAKEN FALSE
|
| 671 |
+
CONF_IPC_RATE_CONF FALSE
|
| 672 |
+
CONF_BTB_MISS_BP_TAKEN_THRESHOLD 0
|
| 673 |
+
CONF_BTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 674 |
+
CONF_IBTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 675 |
+
CONF_MISFETCH_RATE_CYCLES_THRESHOLD 1.0
|
| 676 |
+
CONF_MISPRED_RATE_CYCLES_THRESHOLD 1.0
|
| 677 |
+
CONF_BTB_MISS_SAMPLE_RATE 100000
|
| 678 |
+
CONF_IBTB_MISS_SAMPLE_RATE 100000
|
| 679 |
+
CONF_MISFETCH_SAMPLE_RATE 100000
|
| 680 |
+
CONF_MISPRED_SAMPLE_RATE 100000
|
| 681 |
+
CONF_IPC_SAMPLE_RATE 100000
|
| 682 |
+
CONF_BTB_MISS_RATE_WEIGHT 200
|
| 683 |
+
CONF_BTB_MISS_BP_TAKEN_CONF TRUE
|
| 684 |
+
CONF_IBTB_MISS_BP_TAKEN_CONF TRUE
|
| 685 |
+
CONF_BTB_MISS_RATE_CONF TRUE
|
| 686 |
+
CONF_IBTB_MISS_RATE_CONF TRUE
|
| 687 |
+
CONF_MISFETCH_RATE_CONF TRUE
|
| 688 |
+
CONF_MISPRED_RATE_CONF TRUE
|
| 689 |
+
CONF_INV_BP_CONF TRUE
|
| 690 |
+
CONF_PERFECT_BTB_MISS_CONF FALSE
|
| 691 |
+
CONF_PERFECT_IBTB_MISS_CONF FALSE
|
| 692 |
+
CONF_PERFECT_MISFETCH_CONF FALSE
|
| 693 |
+
CONF_PERFECT_MISPRED_CONF FALSE
|
| 694 |
+
CONF_LOG_DFE_TO_REC FALSE
|
| 695 |
+
CONF_LOG_PHASE_CYCLES FALSE
|
| 696 |
+
NUM_BPS 1
|
| 697 |
+
DFE0_TRIGGER_POLICY 0
|
| 698 |
+
DFE1_TRIGGER_POLICY 1
|
| 699 |
+
DFE2_TRIGGER_POLICY 1
|
| 700 |
+
DFE3_TRIGGER_POLICY 1
|
| 701 |
+
DFE4_TRIGGER_POLICY 1
|
| 702 |
+
DFE0_STOP_POLICY 0
|
| 703 |
+
DFE1_STOP_POLICY 1
|
| 704 |
+
DFE2_STOP_POLICY 1
|
| 705 |
+
DFE3_STOP_POLICY 1
|
| 706 |
+
DFE4_STOP_POLICY 1
|
| 707 |
+
LOOKAHEAD_BUF_SIZE 0
|
| 708 |
+
DEBUG_CYCLE_START 0 0
|
| 709 |
+
DEBUG_CYCLE_STOP 0 -1
|
| 710 |
+
DEBUG_TIME_START 0
|
| 711 |
+
DEBUG_TIME_STOP 0
|
| 712 |
+
DEBUG_INST_START 0 0
|
| 713 |
+
DEBUG_INST_STOP 0 -1
|
| 714 |
+
DEBUG_OP_START 0
|
| 715 |
+
DEBUG_OP_STOP 0
|
| 716 |
+
DEBUG_CACHE_LIB FALSE
|
| 717 |
+
DEBUG_HASH_LIB FALSE
|
| 718 |
+
DEBUG_LIST_LIB FALSE
|
| 719 |
+
DEBUG_PORT_LIB FALSE
|
| 720 |
+
DEBUG_BUS_LIB FALSE
|
| 721 |
+
DEBUG_OP_POOL FALSE
|
| 722 |
+
DEBUG_ORACLE FALSE
|
| 723 |
+
DEBUG_FRONTEND FALSE
|
| 724 |
+
DEBUG_ADDR_TRANS FALSE
|
| 725 |
+
DEBUG_BP FALSE
|
| 726 |
+
DEBUG_BP_DIR FALSE
|
| 727 |
+
DEBUG_BTB FALSE
|
| 728 |
+
DEBUG_CRS FALSE
|
| 729 |
+
DEBUG_MAP FALSE
|
| 730 |
+
DEBUG_MEMORY FALSE
|
| 731 |
+
DEBUG_REPLAY FALSE
|
| 732 |
+
DEBUG_FREQ FALSE
|
| 733 |
+
DEBUG_MODEL FALSE
|
| 734 |
+
DEBUG_THREAD FALSE
|
| 735 |
+
DEBUG_DECOUPLED_FE FALSE
|
| 736 |
+
DEBUG_CONF FALSE
|
| 737 |
+
DEBUG_ICACHE_STAGE FALSE
|
| 738 |
+
DEBUG_DECODE_STAGE FALSE
|
| 739 |
+
DEBUG_CPP_CACHE FALSE
|
| 740 |
+
DEBUG_UOP_CACHE FALSE
|
| 741 |
+
DEBUG_UOP_QUEUE_STAGE FALSE
|
| 742 |
+
DEBUG_IDQ_STAGE FALSE
|
| 743 |
+
DEBUG_MAP_STAGE FALSE
|
| 744 |
+
DEBUG_NODE_STAGE FALSE
|
| 745 |
+
DEBUG_EXEC_STAGE FALSE
|
| 746 |
+
DEBUG_DCACHE_STAGE FALSE
|
| 747 |
+
DEBUG_RETIRED_UOPS FALSE
|
| 748 |
+
DEBUG_EXC_INSERTS FALSE
|
| 749 |
+
DEBUG_BP_CONF FALSE
|
| 750 |
+
DEBUG_ONPATH_CONF FALSE
|
| 751 |
+
DEBUG_STREAM FALSE
|
| 752 |
+
DEBUG_STREAM_MEM FALSE
|
| 753 |
+
DEBUG_WAY FALSE
|
| 754 |
+
DEBUG_L2MARKV FALSE
|
| 755 |
+
DEBUG_L2L1PREF FALSE
|
| 756 |
+
DEBUG_PERF_PRED FALSE
|
| 757 |
+
DEBUG_POWER_UTILS FALSE
|
| 758 |
+
DEBUG_DVFS FALSE
|
| 759 |
+
DEBUG_TRACE_READ FALSE
|
| 760 |
+
DEBUG_INST_FIELDS FALSE
|
| 761 |
+
DEBUG_OP_FIELDS FALSE
|
| 762 |
+
DEBUG_PIN_EXEC_DRIVEN FALSE
|
| 763 |
+
DEBUG_CACHE_PART FALSE
|
| 764 |
+
DEBUG_OPTIMIZER2 FALSE
|
| 765 |
+
DEBUG_PREF FALSE
|
| 766 |
+
DEBUG_FDIP FALSE
|
| 767 |
+
DEBUG_EIP FALSE
|
| 768 |
+
DEBUG_DJOLT FALSE
|
| 769 |
+
DEBUG_FNLMMA FALSE
|
| 770 |
+
PERFECT_BP FALSE
|
| 771 |
+
PERFECT_BTB FALSE
|
| 772 |
+
PERFECT_IBP FALSE
|
| 773 |
+
PERFECT_CRS FALSE
|
| 774 |
+
PERFECT_CBR_BTB FALSE
|
| 775 |
+
PERFECT_NT_BTB FALSE 0 # deprecated, effectively always true.
|
| 776 |
+
CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle
|
| 777 |
+
UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 778 |
+
BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec.
|
| 779 |
+
BP_MECH TAGE64K_BP tage64k
|
| 780 |
+
BP_MECH_L0 BIMODAL_BP
|
| 781 |
+
BP_L0_LATENCY 1
|
| 782 |
+
BP_MAIN_LATENCY 3
|
| 783 |
+
BIMODAL_ENTRIES (4 * 1024)
|
| 784 |
+
HIST_LENGTH 16
|
| 785 |
+
PHT_CTR_BITS 2 const
|
| 786 |
+
BHT_ENTRIES (4 * 1024)
|
| 787 |
+
BHT_ASSOC 4
|
| 788 |
+
HYBRIDS_INDEX_LENGTH 16
|
| 789 |
+
HYBRIDG_HIST_LENGTH 16
|
| 790 |
+
HYBRIDP_HIST_LENGTH 16
|
| 791 |
+
FILTER_INDEX_LENGTH 16
|
| 792 |
+
USE_FILTER FALSE
|
| 793 |
+
INF_HYBRIDGP FALSE
|
| 794 |
+
BP_HASH_TOS FALSE
|
| 795 |
+
IBTB_HASH_TOS FALSE
|
| 796 |
+
BTB_MECH GENERIC_BTB generic
|
| 797 |
+
BTB_ENTRIES 12288 12288
|
| 798 |
+
BTB_ASSOC 4 4
|
| 799 |
+
BTB_NUM_BRSLOT 1
|
| 800 |
+
BTB_BLOCK_SIZE 64
|
| 801 |
+
BTB_OFF_PATH_WRITES TRUE 1
|
| 802 |
+
BTB_MAIN_LATENCY 3 3
|
| 803 |
+
BTB_L0_PRESENT FALSE 1
|
| 804 |
+
BTB_L0_ENTRIES 128 128
|
| 805 |
+
BTB_L0_ASSOC 4 4
|
| 806 |
+
BTB_L0_LATENCY 1 1
|
| 807 |
+
BTB_L1_PRESENT FALSE 1
|
| 808 |
+
BTB_L1_ENTRIES 6144 6144
|
| 809 |
+
BTB_L1_ASSOC 4 4
|
| 810 |
+
BTB_L1_LATENCY 2 2
|
| 811 |
+
ENABLE_CRS TRUE 1
|
| 812 |
+
CRS_ENTRIES 32 128
|
| 813 |
+
CRS_REALISTIC 0 1
|
| 814 |
+
ENABLE_IBP TRUE 1 # Enable the indirect branch predictor
|
| 815 |
+
USE_PAT_HIST TRUE
|
| 816 |
+
IBTB_MECH 1 tc_tagged
|
| 817 |
+
IBTB_HIST_LENGTH 16
|
| 818 |
+
IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb.
|
| 819 |
+
TARGETS_IN_HIST 4
|
| 820 |
+
TC_ENTRIES (4 * 1024) 4096
|
| 821 |
+
TC_ASSOC 4 4
|
| 822 |
+
NUM_CORR_BRANCHES 3
|
| 823 |
+
SEL_HIST_BP_ENTRIES 8192
|
| 824 |
+
SEL_HIST_LENGTH 16
|
| 825 |
+
SEL_HIST_DYN_CNT_TH 16
|
| 826 |
+
SEL_HIST_MISPRED_TH 4
|
| 827 |
+
ENABLE_BP_CONF FALSE
|
| 828 |
+
CONF_MECH 0
|
| 829 |
+
PERF_BP_CONF_PRED FALSE
|
| 830 |
+
BPC_BITS 16
|
| 831 |
+
BPC_MECH 1
|
| 832 |
+
BPC_CTR_RESET TRUE
|
| 833 |
+
BPC_CIT_BITS 8
|
| 834 |
+
BPC_CIT_TH 50
|
| 835 |
+
BPC_CTR_BITS 3
|
| 836 |
+
OPC_COUNT_ZEROS FALSE
|
| 837 |
+
OPC_COUNT_THRESH 10
|
| 838 |
+
INF_LOOP FALSE
|
| 839 |
+
INF_LOOP_BUCKETS 811
|
| 840 |
+
LOOP_ENTRIES (4 * 1024)
|
| 841 |
+
LOOP_ASSOC 4
|
| 842 |
+
LOOP_COUNT_MAX 127
|
| 843 |
+
LOOP_REPEAT_MAX 15
|
| 844 |
+
KNOB_PRINT_BRINFO FALSE
|
| 845 |
+
BR_MISPRED_FILE NULL
|
| 846 |
+
SPEC_LEVEL 3
|
| 847 |
+
RANDOM_DETERMINISTIC TRUE
|
| 848 |
+
TAGESCL64KB_SC TRUE
|
| 849 |
+
TAGESCL64KB_LOOP TRUE
|
| 850 |
+
TAGESCL64KB_ALT TRUE
|
| 851 |
+
CONF_PERCEPTRON_TH 0
|
| 852 |
+
CONF_PERCEPTRON_CTR_BITS 8
|
| 853 |
+
CONF_PERCEPTRON_ENTRIES 127
|
| 854 |
+
CONF_PERCEPTRON_THRESH_OVRD 0
|
| 855 |
+
CONF_HIST_LENGTH 32
|
| 856 |
+
PERCEPTRON_CONF_USE_CONF FALSE
|
| 857 |
+
PERCEPTRON_CONF_TRAIN_HIS FALSE
|
| 858 |
+
PERCEPTRON_CONF_TRAIN_CONF FALSE
|
| 859 |
+
PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE
|
| 860 |
+
PERCEPTRON_TRAIN_MISP_FACTOR 1
|
| 861 |
+
PERCEPTRON_TRAIN_CORR_FACTOR 1
|
| 862 |
+
PERCEPTRON_CONF_HIS_BOTH FALSE
|
| 863 |
+
PERCEPTRON_CONF_HIS_BOTH_LENGTH 4
|
| 864 |
+
MTAGE_REALISTIC_SC_40K FALSE
|
| 865 |
+
MTAGE_REALISTIC_SC_100K FALSE
|
| 866 |
+
H2P_TABLE_BUCKETS 16384
|
| 867 |
+
H2P_MIN_EXEC 5000
|
| 868 |
+
H2P_MIN_MISPRED 333
|
| 869 |
+
H2P_MISPRED_RATIO_PERMIL 10
|
| 870 |
+
H2P_TRACK_CBR TRUE
|
| 871 |
+
H2P_TRACK_REP TRUE
|
| 872 |
+
H2P_TRACK_CALL FALSE
|
| 873 |
+
H2P_TRACK_IBR FALSE
|
| 874 |
+
H2P_TRACK_ICALL FALSE
|
| 875 |
+
H2P_TRACK_RET FALSE
|
| 876 |
+
POWER_INTF_ON FALSE
|
| 877 |
+
POWER_INTF_ENABLE_SCALING FALSE
|
| 878 |
+
POWER_INTF_EXEC "power/power_intf.py"
|
| 879 |
+
POWER_INTF_REF_CHIP_TECH_NM 22
|
| 880 |
+
POWER_INTF_REF_CHIP_FREQ (3.2e9)
|
| 881 |
+
POWER_INTF_REF_MEMORY_FREQ (0.8e9)
|
| 882 |
+
POWER_OTHER (0.0)
|
| 883 |
+
PREF_STREAM_ON FALSE 1
|
| 884 |
+
PREF_STREAM_PER_CORE_ENABLE FALSE
|
| 885 |
+
STREAM_BUFFER_N 16
|
| 886 |
+
STREAM_PREFETCH_N 2 4
|
| 887 |
+
STREAM_START_DIS 5 1
|
| 888 |
+
STREAM_LENGTH 16 64
|
| 889 |
+
STREAM_FULL_N 1
|
| 890 |
+
STREAM_TRAIN_LENGTH 16
|
| 891 |
+
STREAM_TRAIN_NUM 1 4
|
| 892 |
+
PREF_ACC_USE_CACHE FALSE
|
| 893 |
+
STREAM_STALL_ON_QUEUE_FULL FALSE
|
| 894 |
+
PREF_SCHEDULE_NUM 4
|
| 895 |
+
TRAIN_FILTER_SIZE 32
|
| 896 |
+
PREF_REQ_Q_SIZE 64
|
| 897 |
+
STREAM_CREATE_ON_DC_MISS FALSE 0
|
| 898 |
+
STREAM_CREATE_ON_L1_MISS TRUE 1
|
| 899 |
+
STREAM_TRAIN_ON_WRONGPATH TRUE
|
| 900 |
+
STREAM_CREATE_ON_WRONGPATH TRUE
|
| 901 |
+
STREAM_PREF_INTO_DCACHE FALSE
|
| 902 |
+
REMOVE_REDUNDANT_STREAM FALSE
|
| 903 |
+
L2HIT_STREAM_SCHEDULE_NUM 4
|
| 904 |
+
PREF_REQ_QUEUE_FILTER_ON FALSE
|
| 905 |
+
HW_PREF_HIT_TRAIN_STREAM FALSE
|
| 906 |
+
L2HIT_STREAM_BUFFER_N 32
|
| 907 |
+
L2HIT_STREAM_PREFETCH_N 2
|
| 908 |
+
L2HIT_STREAM_START_DIS 2
|
| 909 |
+
L2HIT_STREAM_LENGTH 8
|
| 910 |
+
L2HIT_PREF_REQ_Q_SIZE 128
|
| 911 |
+
L2HIT_L2ACCESS_REQ_Q_SIZE 64
|
| 912 |
+
PREF_STREAM_ACCPERSTREAM FALSE
|
| 913 |
+
PREF_ACC_DISTANCE_10 128
|
| 914 |
+
PREF_FRAMEWORK_ON FALSE 1
|
| 915 |
+
PREF_TRACE_ON FALSE
|
| 916 |
+
PREF_UMLC_ON FALSE
|
| 917 |
+
PREF_UL1_ON TRUE
|
| 918 |
+
PREF_DL0REQ_QUEUE_SIZE 32
|
| 919 |
+
PREF_UMLC_REQ_QUEUE_SIZE 64
|
| 920 |
+
PREF_UL1REQ_QUEUE_SIZE 128
|
| 921 |
+
PREF_SHARED_QUEUES TRUE
|
| 922 |
+
PREF_DL0_MISS_ON TRUE
|
| 923 |
+
PREF_DL0_HIT_ON TRUE
|
| 924 |
+
PREF_DL0REQ_QUEUE_FILTER_ON TRUE
|
| 925 |
+
PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE
|
| 926 |
+
PREF_UL1REQ_QUEUE_FILTER_ON TRUE
|
| 927 |
+
PREF_DL0REQ_ADD_FILTER_ON TRUE
|
| 928 |
+
PREF_UMLC_REQ_ADD_FILTER_ON TRUE
|
| 929 |
+
PREF_UL1REQ_ADD_FILTER_ON TRUE
|
| 930 |
+
PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 931 |
+
PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 932 |
+
PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1
|
| 933 |
+
PREF_DL0SCHEDULE_NUM 4
|
| 934 |
+
PREF_UMLC_SCHEDULE_NUM 4
|
| 935 |
+
PREF_UL1SCHEDULE_NUM 4
|
| 936 |
+
PREF_L1Q_DEMAND_RESERVE 0
|
| 937 |
+
PREF_REPORT_PREF_MATCH_AS_MISS FALSE
|
| 938 |
+
PREF_REPORT_PREF_MATCH_AS_HIT TRUE
|
| 939 |
+
PREF_UPDATE_ON_WRONGPATH TRUE
|
| 940 |
+
PREF_TRAIN_ON_PREF_MISSES FALSE 0
|
| 941 |
+
PREF_ORACLE_TRAIN_ON FALSE 0
|
| 942 |
+
PREF_REQ_DROP FALSE
|
| 943 |
+
PREF_THROTTLE_ON FALSE
|
| 944 |
+
PREF_THROTTLEFB_ON FALSE 1
|
| 945 |
+
PREF_ACC_THRESH_1 0.90 0.75
|
| 946 |
+
PREF_ACC_THRESH_2 0.70 0.4
|
| 947 |
+
PREF_ACC_THRESH_3 0.60 0.4
|
| 948 |
+
PREF_ACC_THRESH_4 0.40
|
| 949 |
+
PREF_UPDATE_INTERVAL 0 8192
|
| 950 |
+
PREF_ANALYZE_LOAD FALSE
|
| 951 |
+
PREF_POL_THRESH_1 0.25
|
| 952 |
+
PREF_POL_THRESH_2 0.10
|
| 953 |
+
PREF_POLBV_ON FALSE
|
| 954 |
+
PREF_POLBV_SIZE 1024
|
| 955 |
+
PREF_TIMELY_THRESH 0.05 0.01
|
| 956 |
+
PREF_POLPF_THRESH 0.01 0.005
|
| 957 |
+
PREF_DEGFB_USEONLYACC FALSE
|
| 958 |
+
PREF_DEGFB_USEONLYPOL FALSE
|
| 959 |
+
PREF_DEGFB_USEONLYLATE FALSE
|
| 960 |
+
PREF_TIMELY_THRESH_2 0.005
|
| 961 |
+
PREF_DEGFB_STATPHASEFILE FALSE
|
| 962 |
+
PREF_MAX_DEGFB 4
|
| 963 |
+
PREF_DHAL FALSE
|
| 964 |
+
PREF_DHAL_SENTTHRESH 16
|
| 965 |
+
PREF_DHAL_USETHRESH_MAX 12
|
| 966 |
+
PREF_DHAL_USETHRESH_MIN2 8
|
| 967 |
+
PREF_DHAL_USETHRESH_MIN1 4
|
| 968 |
+
PREF_DHAL_MAXDEG 64
|
| 969 |
+
PREF_HFILTER_ON FALSE
|
| 970 |
+
PREF_HFILTER_INDEX_BITS 12
|
| 971 |
+
PREF_HFILTER_USE_PC FALSE
|
| 972 |
+
PREF_HFILTER_PRED_USELESS_THRES 2
|
| 973 |
+
PREF_HFILTER_RESET_ENABLE FALSE
|
| 974 |
+
PREF_HFILTER_RESET_INTERVAL 100000
|
| 975 |
+
EIP_ENABLE 0
|
| 976 |
+
L1I_ENTANGLED_TABLE_INDEX_BITS 9
|
| 977 |
+
L1I_ENTANGLED_TABLE_WAYS 16
|
| 978 |
+
DJOLT_ENABLE 0
|
| 979 |
+
FNLMMA_ENABLE 0
|
| 980 |
+
FDIP_ENABLE 1
|
| 981 |
+
FDIP_ALWAYS_PREFETCH FALSE
|
| 982 |
+
PERFECT_FDIP FALSE
|
| 983 |
+
IPRF_MAX_FTQ_ENTRY_CYC 2
|
| 984 |
+
FDIP_BLOOM_FILTER FALSE
|
| 985 |
+
FDIP_BLOOM_ENTRIES 4000
|
| 986 |
+
FDIP_BLOOM2_ENTRIES 1000
|
| 987 |
+
FDIP_BLOOM4_ENTRIES 1000
|
| 988 |
+
FDIP_BLOOM_SIZE 16384
|
| 989 |
+
FDIP_BLOOM_HASHES 6
|
| 990 |
+
FDIP_BLOOM_CLEAR_UNUSEFUL_RATIO 0.95
|
| 991 |
+
FDIP_BLOOM_CLEAR_CYC_PERIOD 10000
|
| 992 |
+
FDIP_UTILITY_HASH_ENABLE 0
|
| 993 |
+
FDIP_UTILITY_PREF_POLICY 0
|
| 994 |
+
FDIP_ADJUSTABLE_FTQ 0
|
| 995 |
+
FDIP_ADJUSTABLE_FTQ_CYC 100000
|
| 996 |
+
UTILITY_RATIO_THRESHOLD 0.58
|
| 997 |
+
TIMELINESS_RATIO_THRESHOLD 0.82
|
| 998 |
+
FDIP_PREF_NO_LATENCY FALSE
|
| 999 |
+
UDP_USEFUL_THRESHOLD 0
|
| 1000 |
+
UDP_WEIGHT_USEFUL 4
|
| 1001 |
+
UDP_WEIGHT_UNUSEFUL 1
|
| 1002 |
+
UDP_WEIGHT_POSITIVE_SATURATION 2147483647
|
| 1003 |
+
FDIP_GHIST_HASHING FALSE
|
| 1004 |
+
FDIP_UTILITY_ONLY_TRAIN_OFF_PATH FALSE
|
| 1005 |
+
FDIP_GHIST_BITS 8
|
| 1006 |
+
UFTQ_MIN_FTQ_BLOCK_NUM 4
|
| 1007 |
+
UFTQ_MAX_FTQ_BLOCK_NUM 64
|
| 1008 |
+
FDIP_SENIORITY_FTQ_HOLD_CYC 30000
|
| 1009 |
+
FDIP_PERFECT_PREFETCH FALSE
|
| 1010 |
+
FDIP_FREEZE_AT_MEM_BUF_LIMIT TRUE
|
| 1011 |
+
FDIP_DUAL_PATH_PREF_IC_ENABLE FALSE
|
| 1012 |
+
FDIP_DUAL_PATH_PREF_UOC_ENABLE FALSE
|
| 1013 |
+
TOP_MISPRED_BR_FILEPATH "br_resteer_coverage.csv"
|
| 1014 |
+
TOP_MISPRED_BR_RESTEER_COVERAGE 0
|
| 1015 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_ENABLE FALSE
|
| 1016 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_MISPRED_THRESHOLD 1
|
| 1017 |
+
FDIP_PRINT_CL_INFO FALSE
|
| 1018 |
+
BRANCH_MISPREDICTION_TABLE_SIZE 0
|
| 1019 |
+
UOC_PREF FALSE
|
| 1020 |
+
UOC_ORACLE_PREF FALSE
|
| 1021 |
+
UOC_ZERO_LATENCY_PREF FALSE
|
| 1022 |
+
L2L1PREF_ON FALSE
|
| 1023 |
+
L2WAY_PREF FALSE
|
| 1024 |
+
L2MARKV_PREF_ON FALSE
|
| 1025 |
+
L2NEXT_PREF_ON FALSE
|
| 1026 |
+
L2HIT_STREAM_PREF_ON FALSE
|
| 1027 |
+
L2L1_DC_HIT_TRAIN FALSE
|
| 1028 |
+
L1_HIT_DUMP_FILE_ON FALSE
|
| 1029 |
+
L1_HIT_DUMP_WO_TXT FALSE
|
| 1030 |
+
L1_HIT_DUMPFILE "l1hit_dump.out"
|
| 1031 |
+
IDEAL_L2_L1_PREFETCHER FALSE
|
| 1032 |
+
IDEAL_L2_ICACHE_PREFETCHER FALSE
|
| 1033 |
+
L1WAY_PREF_SEND_QUEUE 4
|
| 1034 |
+
L1PREF_REQ_QUEUE_SIZE 1024
|
| 1035 |
+
L1PREF_IMMEDIATE FALSE
|
| 1036 |
+
L1WAY_PREF_TIMER_DIS 1000
|
| 1037 |
+
L1MARKV_PREF_SEND_QUEUE 4
|
| 1038 |
+
L1PREF_MARKV_REQ_QUEUE_SIZE 1024
|
| 1039 |
+
MARKV_L2ACCESS_REQ_Q_SIZE 64
|
| 1040 |
+
L1MARKV_PREF_IMMEDIATE FALSE
|
| 1041 |
+
L1MARKV_PREF_TIMER_DIS 1
|
| 1042 |
+
L2L1_HIT_TRAIN TRUE
|
| 1043 |
+
L1MARKV_REQ_TH 1
|
| 1044 |
+
L2L1_IMMEDIATE_PREF_CACHE FALSE
|
| 1045 |
+
L2L1_FILL_PREF_CACHE FALSE
|
| 1046 |
+
L2L1_L2_HIT_STAT FALSE
|
| 1047 |
+
PREF_GHB_ON FALSE
|
| 1048 |
+
DEBUG_PREF_GHB FALSE
|
| 1049 |
+
PREF_GHB_BUFFER_N 1024
|
| 1050 |
+
PREF_GHB_INDEX_N 128
|
| 1051 |
+
PREF_GHB_CZONE_BITS 12
|
| 1052 |
+
PREF_GHB_DEGREE 16
|
| 1053 |
+
PREF_GHB_MAX_DEGREE 32
|
| 1054 |
+
PREF_STRIDE_ON FALSE
|
| 1055 |
+
DEBUG_PREF_STRIDE FALSE
|
| 1056 |
+
PREF_STRIDE_TABLE_N 1024
|
| 1057 |
+
PREF_STRIDE_REGION_BITS 16
|
| 1058 |
+
PREF_STRIDE_DEGREE 4
|
| 1059 |
+
PREF_STRIDE_DISTANCE 16
|
| 1060 |
+
PREF_STRIDE_STARTDISTANCE 1
|
| 1061 |
+
PREF_STRIDE_SINGLE_THRESH 6
|
| 1062 |
+
PREF_STRIDE_MULTI_THRESH 6
|
| 1063 |
+
PREF_STRIDE_SINGLE_STRIDE_MODE FALSE
|
| 1064 |
+
PREF_STRIDEPC_ON FALSE
|
| 1065 |
+
DEBUG_PREF_STRIDEPC FALSE
|
| 1066 |
+
PREF_STRIDEPC_TABLE_N 1024
|
| 1067 |
+
PREF_STRIDEPC_DEGREE 4
|
| 1068 |
+
PREF_STRIDEPC_DISTANCE 16
|
| 1069 |
+
PREF_STRIDEPC_USELOADADDR FALSE
|
| 1070 |
+
PREF_STRIDEPC_TRAINNUM 2
|
| 1071 |
+
PREF_STRIDEPC_STARTDIS 4
|
| 1072 |
+
PREF_PHASE_ON FALSE
|
| 1073 |
+
PREF_PHASE_STUDY FALSE
|
| 1074 |
+
DEBUG_PREF_PHASE FALSE
|
| 1075 |
+
PREF_PHASE_PRIME_HASH 16381
|
| 1076 |
+
PREF_PHASE_INFOSIZE 16384
|
| 1077 |
+
PREF_PHASE_LOG2REGIONSIZE 12
|
| 1078 |
+
PREF_PHASE_REGIONENTRIES 64
|
| 1079 |
+
PREF_PHASE_TRACKEDREGIONS 32
|
| 1080 |
+
PREF_PHASE_INTERVAL 100000
|
| 1081 |
+
PREF_PHASE_TABLE_SIZE 64
|
| 1082 |
+
PREF_PHASE_MAXDIFF_THRESH 64
|
| 1083 |
+
PREF_PHASE_MIN_MISSES 64
|
| 1084 |
+
PREF_PHASE_MISSPER 0.4
|
| 1085 |
+
PREF_2DC_ON FALSE
|
| 1086 |
+
DEBUG_PREF_2DC FALSE
|
| 1087 |
+
PREF_2DC_CACHE_SIZE (1 * 1024)
|
| 1088 |
+
PREF_2DC_CACHE_ASSOC 4
|
| 1089 |
+
PREF_2DC_CACHE_LINE_SIZE 1
|
| 1090 |
+
PREF_2DC_DEGREE 16
|
| 1091 |
+
PREF_2DC_ZONE_SHIFT 10
|
| 1092 |
+
PREF_2DC_TAG_SIZE 16
|
| 1093 |
+
PREF_2DC_NUM_REGIONS 64
|
| 1094 |
+
PREF_2DC_REGION_HASH 61
|
| 1095 |
+
PREF_MARKOV_ON FALSE
|
| 1096 |
+
DEBUG_PREF_MARKOV FALSE
|
| 1097 |
+
PREF_MARKOV_NUM_ENTRIES 65536
|
| 1098 |
+
PREF_MARKOV_NUM_NEXT_STATES 8
|
| 1099 |
+
PREF_MARKOV_SEND_ON_PREF_HIT TRUE
|
| 1100 |
+
PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE
|
| 1101 |
+
PREF_MARKOV_TABLE_UPDATE_POLICY 0
|
| 1102 |
+
PREF_MARKOV_SEND_THRESHOLD 0
|
sssp_facebook/fingerprint/run_4/sim.log
ADDED
|
@@ -0,0 +1,242 @@
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
[0]: ad: 0x7ffff3d9b7cc, op: 847
|
| 2 |
+
[0]: ad: 0x7ffff3d9b7cf, op: 330
|
| 3 |
+
new bb detected: 1
|
| 4 |
+
[1]: ad: 0x7ffff3d9b7b0, op: 388
|
| 5 |
+
[1]: ad: 0x7ffff3d9b7b3, op: 8
|
| 6 |
+
[1]: ad: 0x7ffff3d9b7b7, op: 109
|
| 7 |
+
[1]: ad: 0x7ffff3d9b7bb, op: 315
|
| 8 |
+
new bb detected: 2
|
| 9 |
+
[2]: ad: 0x7ffff3d9b7c1, op: 427
|
| 10 |
+
[2]: ad: 0x7ffff3d9b7c8, op: 427
|
| 11 |
+
[2]: ad: 0x7ffff3d9b7cc, op: 847
|
| 12 |
+
[2]: ad: 0x7ffff3d9b7cf, op: 330
|
| 13 |
+
new bb detected: 3
|
| 14 |
+
[3]: ad: 0x7ffff3d9b88d, op: 427
|
| 15 |
+
[3]: ad: 0x7ffff3d9b890, op: 427
|
| 16 |
+
[3]: ad: 0x7ffff3d9b894, op: 427
|
| 17 |
+
[3]: ad: 0x7ffff3d9b897, op: 427
|
| 18 |
+
[3]: ad: 0x7ffff3d9b89a, op: 109
|
| 19 |
+
[3]: ad: 0x7ffff3d9b89e, op: 315
|
| 20 |
+
new bb detected: 4
|
| 21 |
+
[4]: ad: 0x7ffff3d9b9ba, op: 427
|
| 22 |
+
[4]: ad: 0x7ffff3d9b9bf, op: 427
|
| 23 |
+
[4]: ad: 0x7ffff3d9b9c3, op: 75
|
| 24 |
+
new bb detected: 5
|
| 25 |
+
[5]: ad: 0x7ffff3d9a250, op: 482
|
| 26 |
+
[5]: ad: 0x7ffff3d9a254, op: 316
|
| 27 |
+
new bb detected: 6
|
| 28 |
+
[6]: ad: 0x7ffff7345910, op: 482
|
| 29 |
+
[6]: ad: 0x7ffff7345914, op: 671
|
| 30 |
+
[6]: ad: 0x7ffff7345916, op: 427
|
| 31 |
+
[6]: ad: 0x7ffff7345919, op: 671
|
| 32 |
+
[6]: ad: 0x7ffff734591b, op: 427
|
| 33 |
+
[6]: ad: 0x7ffff7345921, op: 671
|
| 34 |
+
[6]: ad: 0x7ffff7345923, op: 427
|
| 35 |
+
[6]: ad: 0x7ffff7345929, op: 671
|
| 36 |
+
[6]: ad: 0x7ffff734592a, op: 427
|
| 37 |
+
[6]: ad: 0x7ffff734592f, op: 671
|
| 38 |
+
[6]: ad: 0x7ffff7345930, op: 427
|
| 39 |
+
[6]: ad: 0x7ffff7345936, op: 1717
|
| 40 |
+
[6]: ad: 0x7ffff734593b, op: 1723
|
| 41 |
+
[6]: ad: 0x7ffff734593d, op: 427
|
| 42 |
+
[6]: ad: 0x7ffff7345941, op: 427
|
| 43 |
+
[6]: ad: 0x7ffff7345944, op: 427
|
| 44 |
+
[6]: ad: 0x7ffff7345947, op: 8
|
| 45 |
+
[6]: ad: 0x7ffff734594b, op: 157
|
| 46 |
+
[6]: ad: 0x7ffff734594e, op: 826
|
| 47 |
+
[6]: ad: 0x7ffff7345950, op: 109
|
| 48 |
+
[6]: ad: 0x7ffff7345953, op: 319
|
| 49 |
+
new bb detected: 7
|
| 50 |
+
[7]: ad: 0x7ffff7345955, op: 316
|
| 51 |
+
new bb detected: 8
|
| 52 |
+
[8]: ad: 0x7ffff734599f, op: 427
|
| 53 |
+
[8]: ad: 0x7ffff73459a3, op: 388
|
| 54 |
+
[8]: ad: 0x7ffff73459a7, op: 388
|
| 55 |
+
[8]: ad: 0x7ffff73459ab, op: 109
|
| 56 |
+
[8]: ad: 0x7ffff73459ae, op: 319
|
| 57 |
+
new bb detected: 9
|
| 58 |
+
[9]: ad: 0x7ffff73459b4, op: 427
|
| 59 |
+
[9]: ad: 0x7ffff73459b7, op: 1723
|
| 60 |
+
[9]: ad: 0x7ffff73459b9, op: 427
|
| 61 |
+
[9]: ad: 0x7ffff73459bc, op: 157
|
| 62 |
+
[9]: ad: 0x7ffff73459bf, op: 427
|
| 63 |
+
[9]: ad: 0x7ffff73459c1, op: 826
|
| 64 |
+
[9]: ad: 0x7ffff73459c4, op: 123
|
| 65 |
+
[9]: ad: 0x7ffff73459c9, op: 427
|
| 66 |
+
[9]: ad: 0x7ffff73459cb, op: 325
|
| 67 |
+
new bb detected: 10
|
| 68 |
+
[10]: ad: 0x7ffff73459cd, op: 427
|
| 69 |
+
[10]: ad: 0x7ffff73459d1, op: 1723
|
| 70 |
+
[10]: ad: 0x7ffff73459d4, op: 427
|
| 71 |
+
[10]: ad: 0x7ffff73459d9, op: 427
|
| 72 |
+
[10]: ad: 0x7ffff73459de, op: 1723
|
| 73 |
+
[10]: ad: 0x7ffff73459e2, op: 833
|
| 74 |
+
new bb detected: 11
|
| 75 |
+
[11]: ad: 0x7ffff73459e4, op: 109
|
| 76 |
+
[11]: ad: 0x7ffff73459ea, op: 319
|
| 77 |
+
new bb detected: 12
|
| 78 |
+
[12]: ad: 0x7ffff73459ec, op: 109
|
| 79 |
+
[12]: ad: 0x7ffff73459ef, op: 311
|
| 80 |
+
new bb detected: 13
|
| 81 |
+
[13]: ad: 0x7ffff7345a40, op: 388
|
| 82 |
+
[13]: ad: 0x7ffff7345a44, op: 427
|
| 83 |
+
[13]: ad: 0x7ffff7345a49, op: 1717
|
| 84 |
+
[13]: ad: 0x7ffff7345a4d, op: 8
|
| 85 |
+
[13]: ad: 0x7ffff7345a50, op: 109
|
| 86 |
+
[13]: ad: 0x7ffff7345a52, op: 330
|
| 87 |
+
new bb detected: 14
|
| 88 |
+
[14]: ad: 0x7ffff7345a54, op: 1723
|
| 89 |
+
[14]: ad: 0x7ffff7345a56, op: 427
|
| 90 |
+
[14]: ad: 0x7ffff7345a59, op: 616
|
| 91 |
+
[14]: ad: 0x7ffff7345a5a, op: 616
|
| 92 |
+
[14]: ad: 0x7ffff7345a5b, op: 157
|
| 93 |
+
[14]: ad: 0x7ffff7345a5e, op: 616
|
| 94 |
+
[14]: ad: 0x7ffff7345a60, op: 616
|
| 95 |
+
[14]: ad: 0x7ffff7345a62, op: 616
|
| 96 |
+
[14]: ad: 0x7ffff7345a64, op: 109
|
| 97 |
+
[14]: ad: 0x7ffff7345a67, op: 759
|
| 98 |
+
[14]: ad: 0x7ffff7345a69, op: 740
|
| 99 |
+
new bb detected: 15
|
| 100 |
+
[15]: ad: 0x7ffff3d9b9c8, op: 427
|
| 101 |
+
[15]: ad: 0x7ffff3d9b9cc, op: 847
|
| 102 |
+
[15]: ad: 0x7ffff3d9b9ce, op: 325
|
| 103 |
+
new bb detected: 16
|
| 104 |
+
[16]: ad: 0x7ffff3d9b9d0, op: 427
|
| 105 |
+
[16]: ad: 0x7ffff3d9b9d4, op: 285
|
| 106 |
+
[16]: ad: 0x7ffff3d9b9db, op: 109
|
| 107 |
+
[16]: ad: 0x7ffff3d9b9dd, op: 100
|
| 108 |
+
[16]: ad: 0x7ffff3d9b9e0, op: 427
|
| 109 |
+
[16]: ad: 0x7ffff3d9b9e6, op: 427
|
| 110 |
+
[16]: ad: 0x7ffff3d9b9eb, op: 427
|
| 111 |
+
[16]: ad: 0x7ffff3d9b9ef, op: 75
|
| 112 |
+
new bb detected: 17
|
| 113 |
+
[17]: ad: 0x7ffff3d9b9f4, op: 458
|
| 114 |
+
[17]: ad: 0x7ffff3d9b9fa, op: 427
|
| 115 |
+
[17]: ad: 0x7ffff3d9ba00, op: 678
|
| 116 |
+
[17]: ad: 0x7ffff3d9ba04, op: 428
|
| 117 |
+
[17]: ad: 0x7ffff3d9ba08, op: 141
|
| 118 |
+
[17]: ad: 0x7ffff3d9ba0c, op: 160
|
| 119 |
+
[17]: ad: 0x7ffff3d9ba12, op: 475
|
| 120 |
+
[17]: ad: 0x7ffff3d9ba16, op: 149
|
| 121 |
+
[17]: ad: 0x7ffff3d9ba1a, op: 458
|
| 122 |
+
[17]: ad: 0x7ffff3d9ba22, op: 11
|
| 123 |
+
[17]: ad: 0x7ffff3d9ba26, op: 475
|
| 124 |
+
[17]: ad: 0x7ffff3d9ba2a, op: 149
|
| 125 |
+
[17]: ad: 0x7ffff3d9ba2e, op: 109
|
| 126 |
+
[17]: ad: 0x7ffff3d9ba30, op: 96
|
| 127 |
+
[17]: ad: 0x7ffff3d9ba33, op: 427
|
| 128 |
+
[17]: ad: 0x7ffff3d9ba35, op: 109
|
| 129 |
+
[17]: ad: 0x7ffff3d9ba37, op: 330
|
| 130 |
+
new bb detected: 18
|
| 131 |
+
[18]: ad: 0x7ffff3d9ba39, op: 109
|
| 132 |
+
[18]: ad: 0x7ffff3d9ba3d, op: 315
|
| 133 |
+
new bb detected: 19
|
| 134 |
+
[19]: ad: 0x7ffff3d9ba3f, op: 427
|
| 135 |
+
[19]: ad: 0x7ffff3d9ba43, op: 427
|
| 136 |
+
[19]: ad: 0x7ffff3d9ba48, op: 427
|
| 137 |
+
[19]: ad: 0x7ffff3d9ba4c, op: 75
|
| 138 |
+
new bb detected: 20
|
| 139 |
+
[20]: ad: 0x7ffff3d9ba51, op: 427
|
| 140 |
+
[20]: ad: 0x7ffff3d9ba57, op: 847
|
| 141 |
+
[20]: ad: 0x7ffff3d9ba59, op: 427
|
| 142 |
+
[20]: ad: 0x7ffff3d9ba5d, op: 325
|
| 143 |
+
new bb detected: 21
|
| 144 |
+
[21]: ad: 0x7ffff3d9ba5f, op: 427
|
| 145 |
+
[21]: ad: 0x7ffff3d9ba63, op: 109
|
| 146 |
+
[21]: ad: 0x7ffff3d9ba67, op: 314
|
| 147 |
+
new bb detected: 22
|
| 148 |
+
[22]: ad: 0x7ffff3d9b780, op: 109
|
| 149 |
+
[22]: ad: 0x7ffff3d9b782, op: 315
|
| 150 |
+
new bb detected: 23
|
| 151 |
+
[23]: ad: 0x7ffff3d9b788, op: 427
|
| 152 |
+
[23]: ad: 0x7ffff3d9b78c, op: 465
|
| 153 |
+
[23]: ad: 0x7ffff3d9b78f, op: 427
|
| 154 |
+
[23]: ad: 0x7ffff3d9b793, op: 109
|
| 155 |
+
[23]: ad: 0x7ffff3d9b795, op: 96
|
| 156 |
+
[23]: ad: 0x7ffff3d9b798, op: 427
|
| 157 |
+
[23]: ad: 0x7ffff3d9b79b, op: 427
|
| 158 |
+
[23]: ad: 0x7ffff3d9b79f, op: 427
|
| 159 |
+
[23]: ad: 0x7ffff3d9b7a2, op: 427
|
| 160 |
+
[23]: ad: 0x7ffff3d9b7a5, op: 427
|
| 161 |
+
[23]: ad: 0x7ffff3d9b7a8, op: 316
|
| 162 |
+
new bb detected: 24
|
| 163 |
+
[24]: ad: 0x7ffff3d9b7d1, op: 427
|
| 164 |
+
[24]: ad: 0x7ffff3d9b7d6, op: 847
|
| 165 |
+
[24]: ad: 0x7ffff3d9b7d9, op: 315
|
| 166 |
+
new bb detected: 25
|
| 167 |
+
[25]: ad: 0x7ffff3d9b7db, op: 427
|
| 168 |
+
[25]: ad: 0x7ffff3d9b7de, op: 1723
|
| 169 |
+
[25]: ad: 0x7ffff3d9b7e0, op: 427
|
| 170 |
+
[25]: ad: 0x7ffff3d9b7e3, op: 316
|
| 171 |
+
new bb detected: 26
|
| 172 |
+
[26]: ad: 0x7ffff3d9b7f2, op: 427
|
| 173 |
+
[26]: ad: 0x7ffff3d9b7f6, op: 427
|
| 174 |
+
[26]: ad: 0x7ffff3d9b7fa, op: 109
|
| 175 |
+
[26]: ad: 0x7ffff3d9b7ff, op: 315
|
| 176 |
+
new bb detected: 27
|
| 177 |
+
[27]: ad: 0x7ffff3d9b801, op: 427
|
| 178 |
+
[27]: ad: 0x7ffff3d9b805, op: 465
|
| 179 |
+
[27]: ad: 0x7ffff3d9b808, op: 427
|
| 180 |
+
[27]: ad: 0x7ffff3d9b80c, op: 8
|
| 181 |
+
[27]: ad: 0x7ffff3d9b80f, op: 109
|
| 182 |
+
[27]: ad: 0x7ffff3d9b813, op: 315
|
| 183 |
+
new bb detected: 28
|
| 184 |
+
[28]: ad: 0x7ffff3d9b7e8, op: 8
|
| 185 |
+
[28]: ad: 0x7ffff3d9b7ec, op: 109
|
| 186 |
+
[28]: ad: 0x7ffff3d9b7f0, op: 330
|
| 187 |
+
new bb detected: 29
|
| 188 |
+
[29]: ad: 0x7ffff3d9b870, op: 427
|
| 189 |
+
[29]: ad: 0x7ffff3d9b873, op: 388
|
| 190 |
+
[29]: ad: 0x7ffff3d9b876, op: 427
|
| 191 |
+
[29]: ad: 0x7ffff3d9b879, op: 8
|
| 192 |
+
[29]: ad: 0x7ffff3d9b87d, op: 427
|
| 193 |
+
[29]: ad: 0x7ffff3d9b880, op: 427
|
| 194 |
+
[29]: ad: 0x7ffff3d9b883, op: 109
|
| 195 |
+
[29]: ad: 0x7ffff3d9b887, op: 321
|
| 196 |
+
new bb detected: 30
|
| 197 |
+
Scarab gitrev: 7185dea
|
| 198 |
+
Warning: Scarab expects the trace file type to include OFFLINE_FILE_TYPE_ARCH_REGDEPS (0x20000), but got type: 0xe40
|
| 199 |
+
Scarab started at Fri Jul 17 23:07:24 2026
|
| 200 |
+
|
| 201 |
+
read from initialization: 0x7ffff3d9b7cc
|
| 202 |
+
advanceReader: ROI end reached (ordinal 50000002 > roi_end 50000000)
|
| 203 |
+
Reached end of trace (last_inst) pc=0x7ffff3d9b7b7
|
| 204 |
+
[2]: ad: 0x7ffff3d9b7b0, op: 388
|
| 205 |
+
[2]: ad: 0x7ffff3d9b7b3, op: 8
|
| 206 |
+
DUP bb detected at trace end
|
| 207 |
+
to be appened segment num 1
|
| 208 |
+
10000000
|
| 209 |
+
10000000
|
| 210 |
+
====================================
|
| 211 |
+
TRACE_INST_TAKEN_NOT_CF:0
|
| 212 |
+
TRACE_INST_TAKEN_CF_BR:4043
|
| 213 |
+
TRACE_INST_TAKEN_CF_CBR:1194236
|
| 214 |
+
TRACE_INST_TAKEN_CF_REP:0
|
| 215 |
+
TRACE_INST_TAKEN_CF_CALL:3
|
| 216 |
+
TRACE_INST_TAKEN_CF_IBR:3
|
| 217 |
+
TRACE_INST_TAKEN_CF_ICALL:0
|
| 218 |
+
TRACE_INST_TAKEN_CF_ICO:0
|
| 219 |
+
TRACE_INST_TAKEN_CF_RET:3
|
| 220 |
+
TRACE_INST_TAKEN_CF_SYS:3
|
| 221 |
+
====================================
|
| 222 |
+
identity within this segment
|
| 223 |
+
2 bbs with same first pc
|
| 224 |
+
[2]: size 4, freq 1102566
|
| 225 |
+
7ffff3d9b7b0: 388, 0
|
| 226 |
+
7ffff3d9b7b3: 8, 0
|
| 227 |
+
7ffff3d9b7b7: 109, 0
|
| 228 |
+
7ffff3d9b7bb: 315, 0
|
| 229 |
+
[2]: size 2, freq 1
|
| 230 |
+
7ffff3d9b7b0: 388, 0
|
| 231 |
+
7ffff3d9b7b3: 8, 0
|
| 232 |
+
1 / 30
|
| 233 |
+
========================================================
|
| 234 |
+
Number of blocks built : 30
|
| 235 |
+
Average size : 5.53 instructions
|
| 236 |
+
Number of blocks executed : 2476052
|
| 237 |
+
Average weighted size : 4.04 instructions
|
| 238 |
+
Number of total instructions : 10000000
|
| 239 |
+
Number of fetched instruction : 10000000
|
| 240 |
+
========================================================
|
| 241 |
+
Scarab finished at Fri Jul 17 23:07:28 2026
|
| 242 |
+
|
sssp_facebook/fingerprint/run_5/PARAMS.in
ADDED
|
@@ -0,0 +1,268 @@
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|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
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|
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|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
|
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|
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|
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|
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|
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|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
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|
|
|
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|
|
|
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|
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|
|
|
|
| 1 |
+
# File : PARAMS.golden_cove
|
| 2 |
+
# Date : 02/27/25
|
| 3 |
+
# Description : Golden Cove Configuration
|
| 4 |
+
# Author : Surim Oh <[email protected]>
|
| 5 |
+
#
|
| 6 |
+
# Based on documentation found here:
|
| 7 |
+
# https://en.wikipedia.org/wiki/Golden_Cove
|
| 8 |
+
# https://en.wikichip.org/wiki/intel/microarchitectures/golden_cove
|
| 9 |
+
# https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/3
|
| 10 |
+
|
| 11 |
+
## Simulation Parameters
|
| 12 |
+
--mode full
|
| 13 |
+
--model cmp
|
| 14 |
+
--sim_limit none
|
| 15 |
+
|
| 16 |
+
## Core Parameters
|
| 17 |
+
|
| 18 |
+
# Femptoseconds, 3.2GHz, used for energy estimates.
|
| 19 |
+
--chip_cycle_time 312500
|
| 20 |
+
|
| 21 |
+
|
| 22 |
+
### Fetch Stage
|
| 23 |
+
--fetch_off_path_ops 1
|
| 24 |
+
|
| 25 |
+
#### ICache
|
| 26 |
+
--icache_size 32768
|
| 27 |
+
--icache_assoc 8
|
| 28 |
+
--icache_line_size 64
|
| 29 |
+
|
| 30 |
+
### Uop Cache
|
| 31 |
+
# inclusive w/ L1i
|
| 32 |
+
--uop_cache_enable 1
|
| 33 |
+
--uop_cache_width 8
|
| 34 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 35 |
+
--uop_cache_assoc 8
|
| 36 |
+
--iprf_on_uop_cache_hit 1
|
| 37 |
+
|
| 38 |
+
### Branch Predictor
|
| 39 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 40 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 41 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 42 |
+
--bp_mech tage64k
|
| 43 |
+
|
| 44 |
+
|
| 45 |
+
#### BTB
|
| 46 |
+
|
| 47 |
+
# TODO
|
| 48 |
+
# multi-level BTB
|
| 49 |
+
# 128 entry L0 BTB
|
| 50 |
+
# 6144 entry L1 BTB
|
| 51 |
+
# 12888 entry L2 BTB
|
| 52 |
+
# ~2 entry Return Stack
|
| 53 |
+
# roughly 2x8192 for now
|
| 54 |
+
# BTB model to use.
|
| 55 |
+
--btb_mech generic
|
| 56 |
+
--btb_entries 12288
|
| 57 |
+
--btb_assoc 4
|
| 58 |
+
--btb_main_latency 3
|
| 59 |
+
--btb_l0_present 1
|
| 60 |
+
--btb_l0_entries 128
|
| 61 |
+
--btb_l0_assoc 4
|
| 62 |
+
--btb_l0_latency 1
|
| 63 |
+
--btb_l1_present 1
|
| 64 |
+
--btb_l1_entries 6144
|
| 65 |
+
--btb_l1_assoc 4
|
| 66 |
+
--btb_l1_latency 2
|
| 67 |
+
|
| 68 |
+
# Allow the BTB to be updated by off path ops.
|
| 69 |
+
--btb_off_path_writes 1
|
| 70 |
+
|
| 71 |
+
# NT branches are not inserted in BTB, but do not trigger resteer
|
| 72 |
+
# since we continue without a control flow change
|
| 73 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 74 |
+
|
| 75 |
+
#### CRS
|
| 76 |
+
|
| 77 |
+
# Enable return stack
|
| 78 |
+
--enable_crs 1
|
| 79 |
+
--crs_entries 128
|
| 80 |
+
--crs_realistic 1
|
| 81 |
+
|
| 82 |
+
### iBP
|
| 83 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 84 |
+
--ibtb_mech tc_tagged
|
| 85 |
+
# iBTB Model. tc_tagless, tc_tagged, tc_hybrid.
|
| 86 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 87 |
+
--tc_entries 4096
|
| 88 |
+
--tc_assoc 4
|
| 89 |
+
|
| 90 |
+
### Decode Stage
|
| 91 |
+
--decode_width 6
|
| 92 |
+
--decode_cycles 5
|
| 93 |
+
|
| 94 |
+
### Instruction Decode Queue
|
| 95 |
+
--idq_size 144
|
| 96 |
+
|
| 97 |
+
### Map Stage
|
| 98 |
+
--map_cycles 5
|
| 99 |
+
|
| 100 |
+
# register renaming table
|
| 101 |
+
--reg_renaming_scheme 1
|
| 102 |
+
--reg_table_integer_physical_size 280
|
| 103 |
+
--reg_table_vector_physical_size 332
|
| 104 |
+
|
| 105 |
+
### Issue Stage
|
| 106 |
+
|
| 107 |
+
# Max number of instructions to be renamed, and issued per cycle.
|
| 108 |
+
--issue_width 6
|
| 109 |
+
|
| 110 |
+
--rs_fill_width 0
|
| 111 |
+
# rs_sizes ~205 in total, and they are split into three different reservation stations (RS1, RS2, RS3) where each has 97, 70, 38 entries respectively
|
| 112 |
+
# original architecture
|
| 113 |
+
# RS1 connected to port 0,1,5,6,10
|
| 114 |
+
# RS2 connected to port 2,3,11
|
| 115 |
+
# RS3 connected to port 7,8,4,9
|
| 116 |
+
# scarab does not split ST AGU port and ST port, merge them
|
| 117 |
+
# adjusted architecture to scarab ST AGU (port 4 and 9 removed. rs_size reduced to 186 from 205)
|
| 118 |
+
# RS1 connected to port 0,1,4,5,8
|
| 119 |
+
# RS2 connected to port 2,3,9
|
| 120 |
+
# RS3 connected to port 6,7 (port 4,9 removed, entries reduced to 19 from 38)
|
| 121 |
+
--rs_sizes 97 70 19
|
| 122 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 123 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 124 |
+
|
| 125 |
+
### Exec Stage
|
| 126 |
+
|
| 127 |
+
### DCache
|
| 128 |
+
--dcache_size 49152
|
| 129 |
+
--dcache_read_ports 1
|
| 130 |
+
--dcache_write_ports 1
|
| 131 |
+
--dcache_banks 8
|
| 132 |
+
--dcache_assoc 12
|
| 133 |
+
--dcache_line_size 64
|
| 134 |
+
--dcache_cycles 5
|
| 135 |
+
|
| 136 |
+
### Reorder/Retire Stage
|
| 137 |
+
|
| 138 |
+
# Max number of instructions to be retired per cycle.
|
| 139 |
+
--node_ret_width 8
|
| 140 |
+
--node_table_size 512
|
| 141 |
+
|
| 142 |
+
# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does
|
| 143 |
+
--stores_do_not_block_window 1
|
| 144 |
+
|
| 145 |
+
# TODO: confirm what this knob does
|
| 146 |
+
--prefs_do_not_block_window 1
|
| 147 |
+
|
| 148 |
+
|
| 149 |
+
## Uncore
|
| 150 |
+
|
| 151 |
+
### Mid-level cache
|
| 152 |
+
|
| 153 |
+
# Enable use of a midlevel cache between i/d and L1
|
| 154 |
+
# client 1.25 MiB (1310720 bytes) per core, 8-way, 15 cycles
|
| 155 |
+
# server 2 MiB (2097000 bytes) per core, 8-way, 16 cycles
|
| 156 |
+
--mlc_present 1
|
| 157 |
+
--mlc_size 2097000
|
| 158 |
+
--mlc_assoc 8
|
| 159 |
+
--mlc_cycles 16
|
| 160 |
+
|
| 161 |
+
|
| 162 |
+
### LLC
|
| 163 |
+
# 3 MiB per core, 16-way
|
| 164 |
+
--l1_size 3145728
|
| 165 |
+
--l1_banks 8
|
| 166 |
+
--l1_cycles 36 // just a guess
|
| 167 |
+
--l1_assoc 16
|
| 168 |
+
--l1_line_size 64
|
| 169 |
+
--l1_interleave_factor 64
|
| 170 |
+
|
| 171 |
+
|
| 172 |
+
### prefetcher
|
| 173 |
+
# Kept same as Kaby Lake
|
| 174 |
+
--pref_framework_on 1
|
| 175 |
+
--pref_stream_on 1
|
| 176 |
+
--pref_train_on_pref_misses 0
|
| 177 |
+
--pref_oracle_train 0
|
| 178 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 179 |
+
|
| 180 |
+
--stream_length 64
|
| 181 |
+
--stream_prefetch_n 4
|
| 182 |
+
--stream_start_dis 1
|
| 183 |
+
--stream_train_num 4
|
| 184 |
+
--stream_create_on_dc_miss 0
|
| 185 |
+
--stream_create_on_l1_miss 1
|
| 186 |
+
|
| 187 |
+
--pref_throttlefb_on=1
|
| 188 |
+
--pref_acc_thresh_1=0.75
|
| 189 |
+
--pref_acc_thresh_2=0.4
|
| 190 |
+
--pref_acc_thresh_3=0.4
|
| 191 |
+
--pref_timely_thresh=0.01
|
| 192 |
+
--pref_polpf_thresh=0.005
|
| 193 |
+
--pref_update_interval=8192
|
| 194 |
+
|
| 195 |
+
--mem_req_buffer_pref_watermark 4
|
| 196 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 197 |
+
|
| 198 |
+
### Memory
|
| 199 |
+
# Kept same as Kaby Lake
|
| 200 |
+
--addr_translation random
|
| 201 |
+
|
| 202 |
+
--mem_priority_ifetch 0
|
| 203 |
+
--mem_priority_dfetch 1
|
| 204 |
+
--mem_priority_dstore 2
|
| 205 |
+
--mem_priority_iprf 3
|
| 206 |
+
--mem_priority_dprf 4
|
| 207 |
+
--mem_priority_wb 5
|
| 208 |
+
--mem_priority_wb_nodirty 5
|
| 209 |
+
|
| 210 |
+
--mem_req_buffer_entries 32
|
| 211 |
+
--bus_width_in_bytes 8
|
| 212 |
+
|
| 213 |
+
--ramulator_standard DDR4
|
| 214 |
+
--ramulator_speed DDR4_2400R
|
| 215 |
+
--ramulator_org DDR4_8Gb_x8
|
| 216 |
+
--ramulator_channels 1
|
| 217 |
+
--ramulator_ranks 1
|
| 218 |
+
--ramulator_bankgroups 4
|
| 219 |
+
--ramulator_banks 4
|
| 220 |
+
--ramulator_chip_width 8
|
| 221 |
+
--ramulator_rows 65536
|
| 222 |
+
--ramulator_cols 1024
|
| 223 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 224 |
+
--ramulator_readq_entries 32
|
| 225 |
+
--ramulator_writeq_entries 32
|
| 226 |
+
--ramulator_record_cmd_trace FALSE
|
| 227 |
+
--ramulator_print_cmd_trace FALSE
|
| 228 |
+
--ramulator_tCK 833333
|
| 229 |
+
--ramulator_tCL 16
|
| 230 |
+
--ramulator_tCCD 6
|
| 231 |
+
--ramulator_tCCDS 4
|
| 232 |
+
--ramulator_tCCDL 6
|
| 233 |
+
--ramulator_tCWL 12
|
| 234 |
+
--ramulator_tBL 4
|
| 235 |
+
--ramulator_tWTR 9
|
| 236 |
+
--ramulator_tWTRS 3
|
| 237 |
+
--ramulator_tWTRL 9
|
| 238 |
+
--ramulator_tRP 16
|
| 239 |
+
--ramulator_tRPpb 16
|
| 240 |
+
--ramulator_tRPab 16
|
| 241 |
+
--ramulator_tRCD 16
|
| 242 |
+
--ramulator_tRCDR 16
|
| 243 |
+
--ramulator_tRCDW 16
|
| 244 |
+
--ramulator_tRAS 39
|
| 245 |
+
--dram_tech_in_nm 32
|
| 246 |
+
|
| 247 |
+
## Other
|
| 248 |
+
|
| 249 |
+
|
| 250 |
+
### Debug
|
| 251 |
+
--debug_inst_start 0
|
| 252 |
+
--debug_inst_stop -1
|
| 253 |
+
--debug_cycle_start 0
|
| 254 |
+
--debug_cycle_stop -1
|
| 255 |
+
|
| 256 |
+
|
| 257 |
+
## Stats and Params
|
| 258 |
+
--dump_params 1
|
| 259 |
+
--dump_stats 1
|
| 260 |
+
--dump_trace 0
|
| 261 |
+
|
| 262 |
+
####################################
|
| 263 |
+
--set_off_path_confirmed 1
|
| 264 |
+
|
| 265 |
+
--order_beyond_bus 1
|
| 266 |
+
|
| 267 |
+
--mem_ooo_stores 1
|
| 268 |
+
--mem_obey_store_dep 1
|
sssp_facebook/fingerprint/run_5/PARAMS.out
ADDED
|
@@ -0,0 +1,1102 @@
|
|
|
|
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|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
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|
|
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|
|
|
|
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|
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|
|
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|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
|
|
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|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
--mode trace_bbv_distributed
|
| 2 |
+
--model cmp
|
| 3 |
+
--frontend memtrace
|
| 4 |
+
--sim_limit none
|
| 5 |
+
--memtrace_roi_begin 50000001
|
| 6 |
+
--memtrace_roi_end 60000000
|
| 7 |
+
--use_fetched_count 1
|
| 8 |
+
--dump_params 1
|
| 9 |
+
--dump_stats 1
|
| 10 |
+
--dump_trace 0
|
| 11 |
+
--trace_bbv_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.5
|
| 12 |
+
--trace_footprint_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.5
|
| 13 |
+
--segment_instr_count 10000000
|
| 14 |
+
--mlc_present 1
|
| 15 |
+
--mlc_size 2097000
|
| 16 |
+
--mlc_assoc 8
|
| 17 |
+
--mlc_cycles 16
|
| 18 |
+
--l1_size 3145728
|
| 19 |
+
--l1_assoc 16
|
| 20 |
+
--l1_line_size 64
|
| 21 |
+
--l1_cycles 36 // just a guess
|
| 22 |
+
--l1_banks 8
|
| 23 |
+
--l1_interleave_factor 64
|
| 24 |
+
--addr_translation random
|
| 25 |
+
--icache_size 32768
|
| 26 |
+
--icache_assoc 8
|
| 27 |
+
--icache_line_size 64
|
| 28 |
+
--uop_cache_enable 1
|
| 29 |
+
--uop_cache_width 8
|
| 30 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 31 |
+
--uop_cache_assoc 8
|
| 32 |
+
--iprf_on_uop_cache_hit 1
|
| 33 |
+
--dcache_size 49152
|
| 34 |
+
--dcache_assoc 12
|
| 35 |
+
--dcache_line_size 64
|
| 36 |
+
--dcache_cycles 5
|
| 37 |
+
--dcache_read_ports 1
|
| 38 |
+
--dcache_write_ports 1
|
| 39 |
+
--dcache_banks 8
|
| 40 |
+
--mem_ooo_stores 1
|
| 41 |
+
--mem_obey_store_dep 1
|
| 42 |
+
--mem_req_buffer_entries 32
|
| 43 |
+
--mem_priority_ifetch 0
|
| 44 |
+
--mem_priority_dfetch 1
|
| 45 |
+
--mem_priority_dstore 2
|
| 46 |
+
--mem_priority_iprf 3
|
| 47 |
+
--mem_priority_dprf 4
|
| 48 |
+
--mem_priority_wb 5
|
| 49 |
+
--mem_priority_wb_nodirty 5
|
| 50 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 51 |
+
--mem_req_buffer_pref_watermark 4
|
| 52 |
+
--order_beyond_bus 1
|
| 53 |
+
--set_off_path_confirmed 1
|
| 54 |
+
--ramulator_standard DDR4
|
| 55 |
+
--ramulator_speed DDR4_2400R
|
| 56 |
+
--ramulator_org DDR4_8Gb_x8
|
| 57 |
+
--ramulator_channels 1
|
| 58 |
+
--ramulator_ranks 1
|
| 59 |
+
--ramulator_bankgroups 4
|
| 60 |
+
--ramulator_banks 4
|
| 61 |
+
--ramulator_chip_width 8
|
| 62 |
+
--bus_width_in_bytes 8
|
| 63 |
+
--ramulator_rows 65536
|
| 64 |
+
--ramulator_cols 1024
|
| 65 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 66 |
+
--ramulator_readq_entries 32
|
| 67 |
+
--ramulator_writeq_entries 32
|
| 68 |
+
--ramulator_record_cmd_trace FALSE
|
| 69 |
+
--ramulator_print_cmd_trace FALSE
|
| 70 |
+
--ramulator_tCK 833333
|
| 71 |
+
--ramulator_tCL 16
|
| 72 |
+
--ramulator_tCCD 6
|
| 73 |
+
--ramulator_tCCDS 4
|
| 74 |
+
--ramulator_tCCDL 6
|
| 75 |
+
--ramulator_tCWL 12
|
| 76 |
+
--ramulator_tBL 4
|
| 77 |
+
--ramulator_tWTR 9
|
| 78 |
+
--ramulator_tWTRS 3
|
| 79 |
+
--ramulator_tWTRL 9
|
| 80 |
+
--ramulator_tRP 16
|
| 81 |
+
--ramulator_tRPpb 16
|
| 82 |
+
--ramulator_tRPab 16
|
| 83 |
+
--ramulator_tRCD 16
|
| 84 |
+
--ramulator_tRCDR 16
|
| 85 |
+
--ramulator_tRCDW 16
|
| 86 |
+
--ramulator_tRAS 39
|
| 87 |
+
--dram_tech_in_nm 32
|
| 88 |
+
--chip_cycle_time 312500
|
| 89 |
+
--issue_width 6
|
| 90 |
+
--rs_fill_width 0
|
| 91 |
+
--node_table_size 512
|
| 92 |
+
--node_ret_width 8
|
| 93 |
+
--decode_width 6
|
| 94 |
+
--idq_size 144
|
| 95 |
+
--reg_renaming_scheme 1
|
| 96 |
+
--reg_table_integer_physical_size 280
|
| 97 |
+
--reg_table_vector_physical_size 332
|
| 98 |
+
--rs_sizes 97 70 19
|
| 99 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 100 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 101 |
+
--decode_cycles 5
|
| 102 |
+
--map_cycles 5
|
| 103 |
+
--fetch_off_path_ops 1
|
| 104 |
+
--stores_do_not_block_window 1
|
| 105 |
+
--prefs_do_not_block_window 1
|
| 106 |
+
--cbp_trace_r0 /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 107 |
+
--debug_cycle_start 0
|
| 108 |
+
--debug_cycle_stop -1
|
| 109 |
+
--debug_inst_start 0
|
| 110 |
+
--debug_inst_stop -1
|
| 111 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 112 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 113 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 114 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 115 |
+
--bp_mech tage64k
|
| 116 |
+
--btb_mech generic
|
| 117 |
+
--btb_entries 12288
|
| 118 |
+
--btb_assoc 4
|
| 119 |
+
--btb_off_path_writes 1
|
| 120 |
+
--btb_main_latency 3
|
| 121 |
+
--btb_l0_present 1
|
| 122 |
+
--btb_l0_entries 128
|
| 123 |
+
--btb_l0_assoc 4
|
| 124 |
+
--btb_l0_latency 1
|
| 125 |
+
--btb_l1_present 1
|
| 126 |
+
--btb_l1_entries 6144
|
| 127 |
+
--btb_l1_assoc 4
|
| 128 |
+
--btb_l1_latency 2
|
| 129 |
+
--enable_crs 1
|
| 130 |
+
--crs_entries 128
|
| 131 |
+
--crs_realistic 1
|
| 132 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 133 |
+
--ibtb_mech tc_tagged
|
| 134 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 135 |
+
--tc_entries 4096
|
| 136 |
+
--tc_assoc 4
|
| 137 |
+
--pref_stream_on 1
|
| 138 |
+
--stream_prefetch_n 4
|
| 139 |
+
--stream_start_dis 1
|
| 140 |
+
--stream_length 64
|
| 141 |
+
--stream_train_num 4
|
| 142 |
+
--stream_create_on_dc_miss 0
|
| 143 |
+
--stream_create_on_l1_miss 1
|
| 144 |
+
--pref_framework_on 1
|
| 145 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 146 |
+
--pref_train_on_pref_misses 0
|
| 147 |
+
--pref_oracle_train_on 0
|
| 148 |
+
--pref_throttlefb_on 1
|
| 149 |
+
--pref_acc_thresh_1 0.75
|
| 150 |
+
--pref_acc_thresh_2 0.4
|
| 151 |
+
--pref_acc_thresh_3 0.4
|
| 152 |
+
--pref_update_interval 8192
|
| 153 |
+
--pref_timely_thresh 0.01
|
| 154 |
+
--pref_polpf_thresh 0.005
|
| 155 |
+
1 1 1 1 1 1 1
|
| 156 |
+
|
| 157 |
+
--- Cut out everything below to use this file as PARAMS.in ---
|
| 158 |
+
|
| 159 |
+
Parameter status at compile time and values supplied on the command line:
|
| 160 |
+
|
| 161 |
+
SIM_MODE 0 trace_bbv_distributed
|
| 162 |
+
SIM_MODEL 0 cmp
|
| 163 |
+
FRONTEND FE_PIN_EXEC_DRIVEN memtrace
|
| 164 |
+
INST_LIMIT NULL
|
| 165 |
+
SIM_LIMIT "none" none
|
| 166 |
+
FORWARD_PROGRESS_LIMIT 100000000
|
| 167 |
+
FORWARD_PROGRESS_INTERVAL 10000
|
| 168 |
+
FAST_FORWARD 0
|
| 169 |
+
FAST_FORWARD_TRACE_INS 0
|
| 170 |
+
FAST_FORWARD_UNTIL_ADDR 0
|
| 171 |
+
MEMTRACE_ROI_BEGIN 0 50000001
|
| 172 |
+
MEMTRACE_ROI_END 0 60000000
|
| 173 |
+
FULL_WARMUP 0
|
| 174 |
+
WARMUP 0
|
| 175 |
+
HEARTBEAT_INTERVAL 1000000
|
| 176 |
+
NUM_HEARTBEATS 0
|
| 177 |
+
USE_FETCHED_COUNT FALSE 1
|
| 178 |
+
PERIODIC_DUMP FALSE
|
| 179 |
+
FILE_TAG ""
|
| 180 |
+
OUTPUT_DIR "."
|
| 181 |
+
STATUS_FILE NULL
|
| 182 |
+
BINDIR NULL
|
| 183 |
+
DUMP_PARAMS TRUE 1
|
| 184 |
+
DUMP_STATS TRUE 1
|
| 185 |
+
DUMP_TRACE FALSE 0
|
| 186 |
+
CLEAR_STATS "never"
|
| 187 |
+
STATS_TO_TRACE NULL
|
| 188 |
+
STAT_TRACE_FILE "stats.trace"
|
| 189 |
+
STAT_TRACE_INTERVAL "i:100000"
|
| 190 |
+
PIPEVIEW FALSE
|
| 191 |
+
PIPEVIEW_FILE "pipeview"
|
| 192 |
+
MEMVIEW FALSE
|
| 193 |
+
MEMVIEW_FILE "memview.out"
|
| 194 |
+
MEMVIEW_START "never"
|
| 195 |
+
INST_HASH_TABLE_SIZE 524288 const
|
| 196 |
+
STDOUT_FILE NULL
|
| 197 |
+
STDERR_FILE NULL
|
| 198 |
+
PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp"
|
| 199 |
+
PRINT_PID FALSE
|
| 200 |
+
USE_UNSURE_FREE_LISTS FALSE
|
| 201 |
+
OPTIMIZER2_MAX_NUM_SLAVES 64
|
| 202 |
+
OPTIMIZER2_PERFECT_MEMORYLESS FALSE
|
| 203 |
+
EXIT_COND 0
|
| 204 |
+
NUM_NOPS 0
|
| 205 |
+
NOPS_BB_START 0x5000000
|
| 206 |
+
IGNORE_BAR_FETCH FALSE
|
| 207 |
+
TRACE_BBV_OUTPUT NULL /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.5
|
| 208 |
+
TRACE_FOOTPRINT_OUTPUT "" /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.5
|
| 209 |
+
SEGMENT_INSTR_COUNT 0 10000000
|
| 210 |
+
ENABLE_SWPRF FALSE
|
| 211 |
+
MLC_PRESENT FALSE 1
|
| 212 |
+
MLC_SIZE (512 * 1024) 2097000
|
| 213 |
+
MLC_ASSOC 4 8
|
| 214 |
+
MLC_LINE_SIZE 64
|
| 215 |
+
MLC_CYCLES 12 16
|
| 216 |
+
PERFECT_MLC FALSE
|
| 217 |
+
MLC_READ_PORTS 1
|
| 218 |
+
MLC_WRITE_PORTS 1
|
| 219 |
+
MLC_BANKS 8
|
| 220 |
+
MLC_INTERLEAVE_FACTOR 64
|
| 221 |
+
MLC_CACHE_REPL_POLICY 0
|
| 222 |
+
MLC_WRITE_THROUGH FALSE
|
| 223 |
+
PREFETCH_UPDATE_LRU_MLC TRUE
|
| 224 |
+
FORCE_L1_MISS FALSE
|
| 225 |
+
L1_SIZE (4 * 1024 * 1024) 3145728
|
| 226 |
+
L1_ASSOC 8 16
|
| 227 |
+
L1_LINE_SIZE 64 64
|
| 228 |
+
L1_CYCLES 24 36 // just a guess
|
| 229 |
+
PERFECT_L1 FALSE
|
| 230 |
+
PRIVATE_L1 FALSE
|
| 231 |
+
L1_READ_PORTS 1
|
| 232 |
+
L1_WRITE_PORTS 1
|
| 233 |
+
L1_BANKS 8 8
|
| 234 |
+
L1_INTERLEAVE_FACTOR 64 64
|
| 235 |
+
L1_CACHE_REPL_POLICY 0
|
| 236 |
+
L1_WRITE_THROUGH FALSE
|
| 237 |
+
L1_IGNORE_WB FALSE
|
| 238 |
+
L1_USE_CORE_FREQ FALSE
|
| 239 |
+
MARK_L1_MISSES TRUE
|
| 240 |
+
PREFETCH_UPDATE_LRU_L1 TRUE
|
| 241 |
+
MEMORY_RANDOM_ADDR FALSE
|
| 242 |
+
VA_PAGE_SIZE_BYTES 4096
|
| 243 |
+
NUM_ADDR_NON_SIGN_EXTEND_BITS 48
|
| 244 |
+
ADDR_TRANSLATION 0 random
|
| 245 |
+
CONSTANT_MEMORY_LATENCY FALSE
|
| 246 |
+
MEMORY_CYCLES 100
|
| 247 |
+
STALL_MEM_REQS_ONLY FALSE
|
| 248 |
+
ICACHE_SIZE (64 * 1024) 32768
|
| 249 |
+
ICACHE_ASSOC 4 8
|
| 250 |
+
ICACHE_LINE_SIZE 64 64
|
| 251 |
+
PERFECT_ICACHE FALSE
|
| 252 |
+
ICACHE_READ_PORTS 1
|
| 253 |
+
ICACHE_WRITE_PORTS 1
|
| 254 |
+
ICACHE_BANKS 8
|
| 255 |
+
ICACHE_REPL 0
|
| 256 |
+
UOP_CACHE_ENABLE 1 1
|
| 257 |
+
UOP_CACHE_WIDTH 6 8
|
| 258 |
+
ALWAYS_LOOKUP_ICACHE 0
|
| 259 |
+
UOP_CACHE_INSERT_ONLY_ONPATH FALSE
|
| 260 |
+
UOP_CACHE_READ_PORTS 1
|
| 261 |
+
UOP_CACHE_LINES 384 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 262 |
+
UOP_CACHE_ASSOC 8 8
|
| 263 |
+
UOP_CACHE_MAX_IMM_DISP_LINE 4
|
| 264 |
+
IPRF_ON_UOP_CACHE_HIT FALSE 1
|
| 265 |
+
UOP_CACHE_REPL 0
|
| 266 |
+
PRIORITY_LINE_STICKINESS_PERCENT 50
|
| 267 |
+
PW_PRIORITY_LIST_FILEPATH "pw_priority_list.csv"
|
| 268 |
+
NUM_PRIORITY_PWS 10
|
| 269 |
+
PRIORITIZE_PWS_AFTER_FIRST_STICKY_UNTIL_BACKEND_STALL FALSE
|
| 270 |
+
NO_REPL_AFTER_QUEUE_SIZE 0
|
| 271 |
+
FDIP_UC_SIZE 0
|
| 272 |
+
FDIP_UC_ASSOC 4
|
| 273 |
+
FDIP_UC_INSERT_REPLPOL 0
|
| 274 |
+
MAP_STAGE_CONSUME_FROM_ICACHE_AND_UOC_SAME_CYCLE TRUE
|
| 275 |
+
UOP_QUEUE_LENGTH 7
|
| 276 |
+
DCACHE_SIZE (64 * 1024) 49152
|
| 277 |
+
DCACHE_ASSOC 1 12
|
| 278 |
+
DCACHE_LINE_SIZE 64 64
|
| 279 |
+
DCACHE_CYCLES 2 5
|
| 280 |
+
PERFECT_DCACHE FALSE
|
| 281 |
+
DCACHE_READ_PORTS 8 1
|
| 282 |
+
DCACHE_WRITE_PORTS 1 1
|
| 283 |
+
DCACHE_BANKS 1 8
|
| 284 |
+
DCACHE_INTERLEAVE_FACTOR 4
|
| 285 |
+
DCACHE_REPL 0
|
| 286 |
+
DCACHE_REPL_PREF_THRESH 1
|
| 287 |
+
MEM_OOO_STORES TRUE 1
|
| 288 |
+
MEM_OBEY_STORE_DEP TRUE 1
|
| 289 |
+
PREF_INSERT_LRU FALSE
|
| 290 |
+
PREF_INSERT_MIDDLE FALSE
|
| 291 |
+
PREF_INSERT_LOWQTR FALSE
|
| 292 |
+
PREF_INSERT_DYNACC FALSE
|
| 293 |
+
MEM_REQ_BUFFER_ENTRIES 32 32
|
| 294 |
+
PRIVATE_MSHR_ON TRUE
|
| 295 |
+
MEM_PRIORITY_IFETCH 0 0
|
| 296 |
+
MEM_PRIORITY_DFETCH 0 1
|
| 297 |
+
MEM_PRIORITY_DSTORE 0 2
|
| 298 |
+
MEM_PRIORITY_IPRF 9 3
|
| 299 |
+
MEM_PRIORITY_UOCPRF 9
|
| 300 |
+
MEM_PRIORITY_FDIPPRFON 8
|
| 301 |
+
MEM_PRIORITY_FDIPPRFOFF 9
|
| 302 |
+
MEM_PRIORITY_DPRF 10 4
|
| 303 |
+
MEM_PRIORITY_WB 0 5
|
| 304 |
+
MEM_PRIORITY_WB_NODIRTY 0 5
|
| 305 |
+
PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1
|
| 306 |
+
MEM_REQ_BUFFER_PREF_WATERMARK 0 4
|
| 307 |
+
MEM_REQ_BUFFER_WB_VALVE 2
|
| 308 |
+
MEM_L1_FILL_QUEUE_ENTRIES 32
|
| 309 |
+
MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE
|
| 310 |
+
MEM_MEM_QUEUE_PARTITION_ENABLE FALSE
|
| 311 |
+
MEM_BUS_OUT_QUEUE_AS_FIFO TRUE
|
| 312 |
+
OLDEST_FIRST_TO_MEM_QUEUE TRUE
|
| 313 |
+
ROUND_ROBIN_TO_MEM_QUEUE FALSE
|
| 314 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE FALSE
|
| 315 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0
|
| 316 |
+
L1_CYCLE_TIME 312500
|
| 317 |
+
MLCQ_TO_L1Q_TRANSFER_LATENCY 1
|
| 318 |
+
L1Q_TO_FSB_TRANSFER_LATENCY 1
|
| 319 |
+
PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE
|
| 320 |
+
KICKOUT_PREFETCHES FALSE
|
| 321 |
+
KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE
|
| 322 |
+
KICKOUT_OLDEST_PREFETCH FALSE
|
| 323 |
+
KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE
|
| 324 |
+
ORDER_BEYOND_BUS FALSE 1
|
| 325 |
+
ALL_FIFO_QUEUES FALSE
|
| 326 |
+
QUEUE_MLC_SIZE 0
|
| 327 |
+
QUEUE_L1_SIZE 0
|
| 328 |
+
QUEUE_BUS_OUT_SIZE 0
|
| 329 |
+
QUEUE_CORE_FILL_SIZE 0
|
| 330 |
+
ALLOW_TYPE_MATCHES FALSE
|
| 331 |
+
STREAM_PREFETCH_ON FALSE
|
| 332 |
+
DC_PREF_CACHE_ENABLE FALSE
|
| 333 |
+
DC_PREF_CACHE_CYCLE 0
|
| 334 |
+
PREF_INSERT_DCACHE_IMM TRUE
|
| 335 |
+
DC_PREF_CACHE_SIZE (64 * 1024)
|
| 336 |
+
DC_PREF_CACHE_ASSOC 4
|
| 337 |
+
DC_PREF_ONLY_L1HIT FALSE
|
| 338 |
+
PREF_CACHE_USE_RDY_CYCLE FALSE
|
| 339 |
+
IC_PREF_CACHE_ENABLE FALSE
|
| 340 |
+
IC_PREF_CACHE_SIZE (64 * 1024)
|
| 341 |
+
IC_PREF_CACHE_ASSOC 4
|
| 342 |
+
L1_PREF_CACHE_ENABLE FALSE
|
| 343 |
+
L1_PREF_CACHE_SIZE (1024 * 1024)
|
| 344 |
+
L1_PREF_CACHE_ASSOC 8
|
| 345 |
+
SET_OFF_PATH_CONFIRMED FALSE 1
|
| 346 |
+
USE_CONFIRMED_OFF FALSE
|
| 347 |
+
PREFCACHE_MOVE_OFFPATH FALSE
|
| 348 |
+
CACHE_STAT_ENABLE FALSE
|
| 349 |
+
PREF_DCACHE_HIT_FILL_L1 TRUE
|
| 350 |
+
PREF_ICACHE_HIT_FILL_L1 TRUE
|
| 351 |
+
CRITICAL_ACCESS_PLOT_ENABLE FALSE
|
| 352 |
+
CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat"
|
| 353 |
+
ROUND_ROBIN_TO_L1 FALSE
|
| 354 |
+
PREF_I_TOGETHER FALSE
|
| 355 |
+
ONE_MORE_CACHE_LINE_ENABLE FALSE
|
| 356 |
+
L1_STATIC_PARTITION_ENABLE 0
|
| 357 |
+
L1_STATIC_PARTITION NULL
|
| 358 |
+
L1_DYNAMIC_PARTITION_ENABLE FALSE
|
| 359 |
+
L1_DYNAMIC_PARTITION_POLICY 0
|
| 360 |
+
PARTITION_UMON_DSS_PREF_ENABLE FALSE
|
| 361 |
+
L1_CACHE_HIT_POSITION_COLLECT FALSE
|
| 362 |
+
L1_PART_ON FALSE
|
| 363 |
+
L1_PART_TRIGGER "c:1000000"
|
| 364 |
+
L1_PART_START "t:0"
|
| 365 |
+
L1_PART_WARMUP FALSE
|
| 366 |
+
L1_PART_SHADOW_WARMUP FALSE
|
| 367 |
+
L1_PART_METRIC 0
|
| 368 |
+
L1_PART_SEARCH 0
|
| 369 |
+
L1_PART_USE_STALLING TRUE
|
| 370 |
+
L1_PART_FILL_DELAY 0
|
| 371 |
+
L1_SHADOW_TAGS_MODULO 1
|
| 372 |
+
HIER_MSHR_ON FALSE
|
| 373 |
+
PERF_PRED_ENABLE FALSE
|
| 374 |
+
PERF_PRED_MECH PERF_PRED_CP
|
| 375 |
+
PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY
|
| 376 |
+
PERF_PRED_COUNT_ALL FALSE
|
| 377 |
+
PERF_PRED_COUNT_INST_MISSES TRUE
|
| 378 |
+
PERF_PRED_COUNT_PREFETCHES FALSE
|
| 379 |
+
PERF_PRED_COUNT_OFFPATH_REQS FALSE
|
| 380 |
+
PERF_PRED_COUNT_BW_REQS TRUE
|
| 381 |
+
PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE
|
| 382 |
+
PERF_PRED_SLACK_PERIOD_SIZE 32
|
| 383 |
+
PERF_PRED_REQS_FINISH_AT_FILL FALSE
|
| 384 |
+
PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE
|
| 385 |
+
PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE
|
| 386 |
+
DUMB_MODEL_AVG_REQ_DISTANCE 100
|
| 387 |
+
DUMB_MODEL_RANDOMIZE_DISTANCE FALSE
|
| 388 |
+
DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL
|
| 389 |
+
DUMB_MODEL_AVG_ROW_HITS 1
|
| 390 |
+
DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL
|
| 391 |
+
DUMB_MODEL_MLP 1
|
| 392 |
+
DUMB_MODEL_MLP_PER_CORE NULL
|
| 393 |
+
RAMULATOR_STANDARD "DDR4" DDR4
|
| 394 |
+
RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R
|
| 395 |
+
RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8
|
| 396 |
+
RAMULATOR_CHANNELS 1 1
|
| 397 |
+
RAMULATOR_RANKS 1 1
|
| 398 |
+
RAMULATOR_BANKGROUPS 4 4
|
| 399 |
+
RAMULATOR_BANKS 4 4
|
| 400 |
+
RAMULATOR_CHIP_WIDTH 8 8
|
| 401 |
+
BUS_WIDTH_IN_BYTES 8 8
|
| 402 |
+
RAMULATOR_ROWS 65536 65536
|
| 403 |
+
RAMULATOR_COLS 1024 1024
|
| 404 |
+
RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap
|
| 405 |
+
RAMULATOR_READQ_ENTRIES 32 32
|
| 406 |
+
RAMULATOR_WRITEQ_ENTRIES 32 32
|
| 407 |
+
RAMULATOR_REC_CMD_TRACE "off" FALSE
|
| 408 |
+
RAMULATOR_PRINT_CMD_TRACE "off" FALSE
|
| 409 |
+
RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on"
|
| 410 |
+
RAMULATOR_TCK 833333 833333
|
| 411 |
+
RAMULATOR_TCL 16 16
|
| 412 |
+
RAMULATOR_TCCD 6 6
|
| 413 |
+
RAMULATOR_TCCDS 4 4
|
| 414 |
+
RAMULATOR_TCCDL 6 6
|
| 415 |
+
RAMULATOR_TCWL 12 12
|
| 416 |
+
RAMULATOR_TBL 4 4
|
| 417 |
+
RAMULATOR_TWTR 9 9
|
| 418 |
+
RAMULATOR_TWTRS 3 3
|
| 419 |
+
RAMULATOR_TWTRL 9 9
|
| 420 |
+
RAMULATOR_TRP 16 16
|
| 421 |
+
RAMULATOR_TRPpb 16 16
|
| 422 |
+
RAMULATOR_TRPab 16 16
|
| 423 |
+
RAMULATOR_TRCD 16 16
|
| 424 |
+
RAMULATOR_TRCDR 16 16
|
| 425 |
+
RAMULATOR_TRCDW 16 16
|
| 426 |
+
RAMULATOR_TRAS 39 39
|
| 427 |
+
DRAM_TECH_IN_NM 32 32
|
| 428 |
+
DVFS_ON FALSE
|
| 429 |
+
DVFS_METRIC DVFS_METRIC_NUM_ELEMS
|
| 430 |
+
DVFS_CONFIGS NULL
|
| 431 |
+
DVFS_CONFIG_FILE NULL
|
| 432 |
+
DVFS_START "t:0"
|
| 433 |
+
DVFS_PERIOD "t:312500000000"
|
| 434 |
+
DVFS_LOG TRUE
|
| 435 |
+
DVFS_INDIVIDUAL_CORES FALSE
|
| 436 |
+
DVFS_CHIP_LEVEL FALSE
|
| 437 |
+
DVFS_STATIC NULL
|
| 438 |
+
DVFS_FORCE_CONFIG NULL
|
| 439 |
+
DVFS_REPLAY_CONFIG_TRACE NULL
|
| 440 |
+
DVFS_USE_ORACLE FALSE
|
| 441 |
+
DVFS_USE_BW_SHARING FALSE
|
| 442 |
+
DVFS_USE_DRAM_SHARING FALSE
|
| 443 |
+
DVFS_USE_STALL_TIME FALSE
|
| 444 |
+
DVFS_DRAM_SHARING_SOLVER_BIN NULL
|
| 445 |
+
DVFS_DRAM_SHARING_SOLVER_STRICT TRUE
|
| 446 |
+
DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95
|
| 447 |
+
DVFS_BW_SHARING_MAX_REQS 28.0
|
| 448 |
+
DVFS_BW_SHARING_MAX_RW_COST 0.25
|
| 449 |
+
DVFS_BW_SHARING_NO_PREF_STALL TRUE
|
| 450 |
+
DVFS_BW_SHARING_CRIT_STATS TRUE
|
| 451 |
+
DVFS_COUNT_L1_ACCESS_STALL FALSE
|
| 452 |
+
NUM_CORES 1
|
| 453 |
+
CHIP_CYCLE_TIME 312500 312500
|
| 454 |
+
CORE_0_CYCLE_TIME 312500
|
| 455 |
+
CORE_1_CYCLE_TIME 312500
|
| 456 |
+
CORE_2_CYCLE_TIME 312500
|
| 457 |
+
CORE_3_CYCLE_TIME 312500
|
| 458 |
+
CORE_4_CYCLE_TIME 312500
|
| 459 |
+
CORE_5_CYCLE_TIME 312500
|
| 460 |
+
CORE_6_CYCLE_TIME 312500
|
| 461 |
+
CORE_7_CYCLE_TIME 312500
|
| 462 |
+
CORE_8_CYCLE_TIME 312500
|
| 463 |
+
CORE_9_CYCLE_TIME 312500
|
| 464 |
+
CORE_10_CYCLE_TIME 312500
|
| 465 |
+
CORE_11_CYCLE_TIME 312500
|
| 466 |
+
CORE_12_CYCLE_TIME 312500
|
| 467 |
+
CORE_13_CYCLE_TIME 312500
|
| 468 |
+
CORE_14_CYCLE_TIME 312500
|
| 469 |
+
CORE_15_CYCLE_TIME 312500
|
| 470 |
+
CORE_16_CYCLE_TIME 312500
|
| 471 |
+
CORE_17_CYCLE_TIME 312500
|
| 472 |
+
CORE_18_CYCLE_TIME 312500
|
| 473 |
+
CORE_19_CYCLE_TIME 312500
|
| 474 |
+
CORE_20_CYCLE_TIME 312500
|
| 475 |
+
CORE_21_CYCLE_TIME 312500
|
| 476 |
+
CORE_22_CYCLE_TIME 312500
|
| 477 |
+
CORE_23_CYCLE_TIME 312500
|
| 478 |
+
CORE_24_CYCLE_TIME 312500
|
| 479 |
+
CORE_25_CYCLE_TIME 312500
|
| 480 |
+
CORE_26_CYCLE_TIME 312500
|
| 481 |
+
CORE_27_CYCLE_TIME 312500
|
| 482 |
+
CORE_28_CYCLE_TIME 312500
|
| 483 |
+
CORE_29_CYCLE_TIME 312500
|
| 484 |
+
CORE_30_CYCLE_TIME 312500
|
| 485 |
+
CORE_31_CYCLE_TIME 312500
|
| 486 |
+
CORE_32_CYCLE_TIME 312500
|
| 487 |
+
CORE_33_CYCLE_TIME 312500
|
| 488 |
+
CORE_34_CYCLE_TIME 312500
|
| 489 |
+
CORE_35_CYCLE_TIME 312500
|
| 490 |
+
CORE_36_CYCLE_TIME 312500
|
| 491 |
+
CORE_37_CYCLE_TIME 312500
|
| 492 |
+
CORE_38_CYCLE_TIME 312500
|
| 493 |
+
CORE_39_CYCLE_TIME 312500
|
| 494 |
+
CORE_40_CYCLE_TIME 312500
|
| 495 |
+
CORE_41_CYCLE_TIME 312500
|
| 496 |
+
CORE_42_CYCLE_TIME 312500
|
| 497 |
+
CORE_43_CYCLE_TIME 312500
|
| 498 |
+
CORE_44_CYCLE_TIME 312500
|
| 499 |
+
CORE_45_CYCLE_TIME 312500
|
| 500 |
+
CORE_46_CYCLE_TIME 312500
|
| 501 |
+
CORE_47_CYCLE_TIME 312500
|
| 502 |
+
CORE_48_CYCLE_TIME 312500
|
| 503 |
+
CORE_49_CYCLE_TIME 312500
|
| 504 |
+
CORE_50_CYCLE_TIME 312500
|
| 505 |
+
CORE_51_CYCLE_TIME 312500
|
| 506 |
+
CORE_52_CYCLE_TIME 312500
|
| 507 |
+
CORE_53_CYCLE_TIME 312500
|
| 508 |
+
CORE_54_CYCLE_TIME 312500
|
| 509 |
+
CORE_55_CYCLE_TIME 312500
|
| 510 |
+
CORE_56_CYCLE_TIME 312500
|
| 511 |
+
CORE_57_CYCLE_TIME 312500
|
| 512 |
+
CORE_58_CYCLE_TIME 312500
|
| 513 |
+
CORE_59_CYCLE_TIME 312500
|
| 514 |
+
CORE_60_CYCLE_TIME 312500
|
| 515 |
+
CORE_61_CYCLE_TIME 312500
|
| 516 |
+
CORE_62_CYCLE_TIME 312500
|
| 517 |
+
CORE_63_CYCLE_TIME 312500
|
| 518 |
+
TOPDOWN_FU_EXEC_FEW 0
|
| 519 |
+
ISSUE_WIDTH 4 6
|
| 520 |
+
RS_FILL_WIDTH 8 0
|
| 521 |
+
NODE_TABLE_SIZE 256 512
|
| 522 |
+
NODE_RET_WIDTH 4 8
|
| 523 |
+
NODE_RETIRE_RATE 10
|
| 524 |
+
DECODE_WIDTH 4 6
|
| 525 |
+
IDQ_SIZE 140 144
|
| 526 |
+
REG_RENAMING_SCHEME 0 1
|
| 527 |
+
REG_TABLE_INTEGER_PHYSICAL_SIZE 256 280
|
| 528 |
+
REG_TABLE_VECTOR_PHYSICAL_SIZE 256 332
|
| 529 |
+
REG_TABLE_INTEGER_VIRTUAL_SIZE 256
|
| 530 |
+
REG_TABLE_VECTOR_VIRTUAL_SIZE 256
|
| 531 |
+
REG_RENAMING_MOVE_ELIMINATE FALSE
|
| 532 |
+
NODE_ISSUE_QUEUE_DISPATCH_SCHEME 0
|
| 533 |
+
NODE_ISSUE_QUEUE_SCHEDULE_SCHEME 0
|
| 534 |
+
ISSUE_QUEUE_PARALLEL_PICK FALSE
|
| 535 |
+
RS_SIZES "256" 97 70 19
|
| 536 |
+
RS_CONNECTIONS "xF" b0100110011 b1000001100 b0011000000
|
| 537 |
+
FU_TYPES "0, 0, 0, 0" b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 538 |
+
LSQ_ENABLE TRUE
|
| 539 |
+
LOAD_QUEUE_ENTRY_NUM 128
|
| 540 |
+
STORE_QUEUE_ENTRY_NUM 72
|
| 541 |
+
DECODE_CYCLES 1 5
|
| 542 |
+
MAP_CYCLES 1 5
|
| 543 |
+
ICACHE_LATENCY 3
|
| 544 |
+
EXTRA_REDIRECT_CYCLES 0
|
| 545 |
+
EXTRA_RECOVERY_CYCLES 0
|
| 546 |
+
EXTRA_CALLSYS_CYCLES 20 const
|
| 547 |
+
DIE_ON_CALLSYS FALSE
|
| 548 |
+
DIE_ON_RET_STALL_THRESH 0
|
| 549 |
+
DIE_ON_RET_STALL_CORE 0
|
| 550 |
+
DIE_ON_MEM_BLOCK_THRESH 0
|
| 551 |
+
DIE_ON_MEM_BLOCK_CORE 0
|
| 552 |
+
ICACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 553 |
+
UOP_CACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 554 |
+
FETCH_OFF_PATH_OPS TRUE 1
|
| 555 |
+
WP_COLLECT_STATS TRUE
|
| 556 |
+
OP_INV_DELAY 1
|
| 557 |
+
OP_NOP_DELAY 1
|
| 558 |
+
OP_CF_DELAY 1
|
| 559 |
+
OP_MOV_DELAY 1
|
| 560 |
+
OP_CMOV_DELAY 1
|
| 561 |
+
OP_LDA_DELAY 1
|
| 562 |
+
OP_ILD_DELAY 1
|
| 563 |
+
OP_IST_DELAY 1
|
| 564 |
+
OP_IADD_DELAY 1
|
| 565 |
+
OP_IMUL_DELAY 3
|
| 566 |
+
OP_IDIV_DELAY -20
|
| 567 |
+
OP_ICMP_DELAY 1
|
| 568 |
+
OP_LOGIC_DELAY 1
|
| 569 |
+
OP_SHIFT_DELAY 1
|
| 570 |
+
OP_FLD_DELAY 1
|
| 571 |
+
OP_FST_DELAY 1
|
| 572 |
+
OP_FCVT_DELAY 3
|
| 573 |
+
OP_FADD_DELAY 3
|
| 574 |
+
OP_FMUL_DELAY 5
|
| 575 |
+
OP_FMA_DELAY 5
|
| 576 |
+
OP_FDIV_DELAY -20
|
| 577 |
+
OP_FCMP_DELAY 3
|
| 578 |
+
OP_FCMOV_DELAY 1
|
| 579 |
+
OP_GATHER_DELAY 12
|
| 580 |
+
OP_SCATTER_DELAY 18
|
| 581 |
+
OP_PIPELINED_FAST_DELAY 2
|
| 582 |
+
OP_PIPELINED_MEDIUM_DELAY 5
|
| 583 |
+
OP_PIPELINED_SLOW_DELAY 10
|
| 584 |
+
OP_NOTPIPELINED_MEDIUM_DELAY -5
|
| 585 |
+
OP_NOTPIPELINED_SLOW_DELAY -20
|
| 586 |
+
OP_NOTPIPELINED_VERY_SLOW_DELAY -100
|
| 587 |
+
UNIFORM_OP_DELAY 0
|
| 588 |
+
STALL_ON_WAIT_MEM TRUE
|
| 589 |
+
STORES_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 590 |
+
PREFS_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 591 |
+
OBEY_REG_DEP TRUE
|
| 592 |
+
TRACK_L1_MISS_DEPS FALSE
|
| 593 |
+
CBP_TRACE_R0 NULL /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 594 |
+
CBP_TRACE_R1 NULL
|
| 595 |
+
CBP_TRACE_R2 NULL
|
| 596 |
+
CBP_TRACE_R3 NULL
|
| 597 |
+
CBP_TRACE_R4 NULL
|
| 598 |
+
CBP_TRACE_R5 NULL
|
| 599 |
+
CBP_TRACE_R6 NULL
|
| 600 |
+
CBP_TRACE_R7 NULL
|
| 601 |
+
CBP_TRACE_R8 NULL
|
| 602 |
+
CBP_TRACE_R9 NULL
|
| 603 |
+
CBP_TRACE_R10 NULL
|
| 604 |
+
CBP_TRACE_R11 NULL
|
| 605 |
+
CBP_TRACE_R12 NULL
|
| 606 |
+
CBP_TRACE_R13 NULL
|
| 607 |
+
CBP_TRACE_R14 NULL
|
| 608 |
+
CBP_TRACE_R15 NULL
|
| 609 |
+
CBP_TRACE_R16 NULL
|
| 610 |
+
CBP_TRACE_R17 NULL
|
| 611 |
+
CBP_TRACE_R18 NULL
|
| 612 |
+
CBP_TRACE_R19 NULL
|
| 613 |
+
CBP_TRACE_R20 NULL
|
| 614 |
+
CBP_TRACE_R21 NULL
|
| 615 |
+
CBP_TRACE_R22 NULL
|
| 616 |
+
CBP_TRACE_R23 NULL
|
| 617 |
+
CBP_TRACE_R24 NULL
|
| 618 |
+
CBP_TRACE_R25 NULL
|
| 619 |
+
CBP_TRACE_R26 NULL
|
| 620 |
+
CBP_TRACE_R27 NULL
|
| 621 |
+
CBP_TRACE_R28 NULL
|
| 622 |
+
CBP_TRACE_R29 NULL
|
| 623 |
+
CBP_TRACE_R30 NULL
|
| 624 |
+
CBP_TRACE_R31 NULL
|
| 625 |
+
CBP_TRACE_R32 NULL
|
| 626 |
+
CBP_TRACE_R33 NULL
|
| 627 |
+
CBP_TRACE_R34 NULL
|
| 628 |
+
CBP_TRACE_R35 NULL
|
| 629 |
+
CBP_TRACE_R36 NULL
|
| 630 |
+
CBP_TRACE_R37 NULL
|
| 631 |
+
CBP_TRACE_R38 NULL
|
| 632 |
+
CBP_TRACE_R39 NULL
|
| 633 |
+
CBP_TRACE_R40 NULL
|
| 634 |
+
CBP_TRACE_R41 NULL
|
| 635 |
+
CBP_TRACE_R42 NULL
|
| 636 |
+
CBP_TRACE_R43 NULL
|
| 637 |
+
CBP_TRACE_R44 NULL
|
| 638 |
+
CBP_TRACE_R45 NULL
|
| 639 |
+
CBP_TRACE_R46 NULL
|
| 640 |
+
CBP_TRACE_R47 NULL
|
| 641 |
+
CBP_TRACE_R48 NULL
|
| 642 |
+
CBP_TRACE_R49 NULL
|
| 643 |
+
CBP_TRACE_R50 NULL
|
| 644 |
+
CBP_TRACE_R51 NULL
|
| 645 |
+
CBP_TRACE_R52 NULL
|
| 646 |
+
CBP_TRACE_R53 NULL
|
| 647 |
+
CBP_TRACE_R54 NULL
|
| 648 |
+
CBP_TRACE_R55 NULL
|
| 649 |
+
CBP_TRACE_R56 NULL
|
| 650 |
+
CBP_TRACE_R57 NULL
|
| 651 |
+
CBP_TRACE_R58 NULL
|
| 652 |
+
CBP_TRACE_R59 NULL
|
| 653 |
+
CBP_TRACE_R60 NULL
|
| 654 |
+
CBP_TRACE_R61 NULL
|
| 655 |
+
CBP_TRACE_R62 NULL
|
| 656 |
+
CBP_TRACE_R63 NULL
|
| 657 |
+
FE_FTQ_BLOCK_NUM 32
|
| 658 |
+
FE_FTQ_TAKEN_CFS_PER_CYCLE 2
|
| 659 |
+
FE_FTQ_FT_PER_CYCLE 1
|
| 660 |
+
DUMB_CORE_ON FALSE
|
| 661 |
+
DUMB_CORE 1
|
| 662 |
+
DCACHE_MISS_RATE 10
|
| 663 |
+
L1_MISS_RATE 10
|
| 664 |
+
TRACE_BUF_SIZE 0
|
| 665 |
+
PERFECT_CONFIDENCE FALSE
|
| 666 |
+
CONFIDENCE_ENABLE FALSE
|
| 667 |
+
CONFIDENCE_MECH 0
|
| 668 |
+
CONF_OFF_PATH_THRESHOLD 15
|
| 669 |
+
CONF_OFF_PATH_INC 5
|
| 670 |
+
CONF_BTB_MISS_BP_TAKEN FALSE
|
| 671 |
+
CONF_IPC_RATE_CONF FALSE
|
| 672 |
+
CONF_BTB_MISS_BP_TAKEN_THRESHOLD 0
|
| 673 |
+
CONF_BTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 674 |
+
CONF_IBTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 675 |
+
CONF_MISFETCH_RATE_CYCLES_THRESHOLD 1.0
|
| 676 |
+
CONF_MISPRED_RATE_CYCLES_THRESHOLD 1.0
|
| 677 |
+
CONF_BTB_MISS_SAMPLE_RATE 100000
|
| 678 |
+
CONF_IBTB_MISS_SAMPLE_RATE 100000
|
| 679 |
+
CONF_MISFETCH_SAMPLE_RATE 100000
|
| 680 |
+
CONF_MISPRED_SAMPLE_RATE 100000
|
| 681 |
+
CONF_IPC_SAMPLE_RATE 100000
|
| 682 |
+
CONF_BTB_MISS_RATE_WEIGHT 200
|
| 683 |
+
CONF_BTB_MISS_BP_TAKEN_CONF TRUE
|
| 684 |
+
CONF_IBTB_MISS_BP_TAKEN_CONF TRUE
|
| 685 |
+
CONF_BTB_MISS_RATE_CONF TRUE
|
| 686 |
+
CONF_IBTB_MISS_RATE_CONF TRUE
|
| 687 |
+
CONF_MISFETCH_RATE_CONF TRUE
|
| 688 |
+
CONF_MISPRED_RATE_CONF TRUE
|
| 689 |
+
CONF_INV_BP_CONF TRUE
|
| 690 |
+
CONF_PERFECT_BTB_MISS_CONF FALSE
|
| 691 |
+
CONF_PERFECT_IBTB_MISS_CONF FALSE
|
| 692 |
+
CONF_PERFECT_MISFETCH_CONF FALSE
|
| 693 |
+
CONF_PERFECT_MISPRED_CONF FALSE
|
| 694 |
+
CONF_LOG_DFE_TO_REC FALSE
|
| 695 |
+
CONF_LOG_PHASE_CYCLES FALSE
|
| 696 |
+
NUM_BPS 1
|
| 697 |
+
DFE0_TRIGGER_POLICY 0
|
| 698 |
+
DFE1_TRIGGER_POLICY 1
|
| 699 |
+
DFE2_TRIGGER_POLICY 1
|
| 700 |
+
DFE3_TRIGGER_POLICY 1
|
| 701 |
+
DFE4_TRIGGER_POLICY 1
|
| 702 |
+
DFE0_STOP_POLICY 0
|
| 703 |
+
DFE1_STOP_POLICY 1
|
| 704 |
+
DFE2_STOP_POLICY 1
|
| 705 |
+
DFE3_STOP_POLICY 1
|
| 706 |
+
DFE4_STOP_POLICY 1
|
| 707 |
+
LOOKAHEAD_BUF_SIZE 0
|
| 708 |
+
DEBUG_CYCLE_START 0 0
|
| 709 |
+
DEBUG_CYCLE_STOP 0 -1
|
| 710 |
+
DEBUG_TIME_START 0
|
| 711 |
+
DEBUG_TIME_STOP 0
|
| 712 |
+
DEBUG_INST_START 0 0
|
| 713 |
+
DEBUG_INST_STOP 0 -1
|
| 714 |
+
DEBUG_OP_START 0
|
| 715 |
+
DEBUG_OP_STOP 0
|
| 716 |
+
DEBUG_CACHE_LIB FALSE
|
| 717 |
+
DEBUG_HASH_LIB FALSE
|
| 718 |
+
DEBUG_LIST_LIB FALSE
|
| 719 |
+
DEBUG_PORT_LIB FALSE
|
| 720 |
+
DEBUG_BUS_LIB FALSE
|
| 721 |
+
DEBUG_OP_POOL FALSE
|
| 722 |
+
DEBUG_ORACLE FALSE
|
| 723 |
+
DEBUG_FRONTEND FALSE
|
| 724 |
+
DEBUG_ADDR_TRANS FALSE
|
| 725 |
+
DEBUG_BP FALSE
|
| 726 |
+
DEBUG_BP_DIR FALSE
|
| 727 |
+
DEBUG_BTB FALSE
|
| 728 |
+
DEBUG_CRS FALSE
|
| 729 |
+
DEBUG_MAP FALSE
|
| 730 |
+
DEBUG_MEMORY FALSE
|
| 731 |
+
DEBUG_REPLAY FALSE
|
| 732 |
+
DEBUG_FREQ FALSE
|
| 733 |
+
DEBUG_MODEL FALSE
|
| 734 |
+
DEBUG_THREAD FALSE
|
| 735 |
+
DEBUG_DECOUPLED_FE FALSE
|
| 736 |
+
DEBUG_CONF FALSE
|
| 737 |
+
DEBUG_ICACHE_STAGE FALSE
|
| 738 |
+
DEBUG_DECODE_STAGE FALSE
|
| 739 |
+
DEBUG_CPP_CACHE FALSE
|
| 740 |
+
DEBUG_UOP_CACHE FALSE
|
| 741 |
+
DEBUG_UOP_QUEUE_STAGE FALSE
|
| 742 |
+
DEBUG_IDQ_STAGE FALSE
|
| 743 |
+
DEBUG_MAP_STAGE FALSE
|
| 744 |
+
DEBUG_NODE_STAGE FALSE
|
| 745 |
+
DEBUG_EXEC_STAGE FALSE
|
| 746 |
+
DEBUG_DCACHE_STAGE FALSE
|
| 747 |
+
DEBUG_RETIRED_UOPS FALSE
|
| 748 |
+
DEBUG_EXC_INSERTS FALSE
|
| 749 |
+
DEBUG_BP_CONF FALSE
|
| 750 |
+
DEBUG_ONPATH_CONF FALSE
|
| 751 |
+
DEBUG_STREAM FALSE
|
| 752 |
+
DEBUG_STREAM_MEM FALSE
|
| 753 |
+
DEBUG_WAY FALSE
|
| 754 |
+
DEBUG_L2MARKV FALSE
|
| 755 |
+
DEBUG_L2L1PREF FALSE
|
| 756 |
+
DEBUG_PERF_PRED FALSE
|
| 757 |
+
DEBUG_POWER_UTILS FALSE
|
| 758 |
+
DEBUG_DVFS FALSE
|
| 759 |
+
DEBUG_TRACE_READ FALSE
|
| 760 |
+
DEBUG_INST_FIELDS FALSE
|
| 761 |
+
DEBUG_OP_FIELDS FALSE
|
| 762 |
+
DEBUG_PIN_EXEC_DRIVEN FALSE
|
| 763 |
+
DEBUG_CACHE_PART FALSE
|
| 764 |
+
DEBUG_OPTIMIZER2 FALSE
|
| 765 |
+
DEBUG_PREF FALSE
|
| 766 |
+
DEBUG_FDIP FALSE
|
| 767 |
+
DEBUG_EIP FALSE
|
| 768 |
+
DEBUG_DJOLT FALSE
|
| 769 |
+
DEBUG_FNLMMA FALSE
|
| 770 |
+
PERFECT_BP FALSE
|
| 771 |
+
PERFECT_BTB FALSE
|
| 772 |
+
PERFECT_IBP FALSE
|
| 773 |
+
PERFECT_CRS FALSE
|
| 774 |
+
PERFECT_CBR_BTB FALSE
|
| 775 |
+
PERFECT_NT_BTB FALSE 0 # deprecated, effectively always true.
|
| 776 |
+
CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle
|
| 777 |
+
UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 778 |
+
BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec.
|
| 779 |
+
BP_MECH TAGE64K_BP tage64k
|
| 780 |
+
BP_MECH_L0 BIMODAL_BP
|
| 781 |
+
BP_L0_LATENCY 1
|
| 782 |
+
BP_MAIN_LATENCY 3
|
| 783 |
+
BIMODAL_ENTRIES (4 * 1024)
|
| 784 |
+
HIST_LENGTH 16
|
| 785 |
+
PHT_CTR_BITS 2 const
|
| 786 |
+
BHT_ENTRIES (4 * 1024)
|
| 787 |
+
BHT_ASSOC 4
|
| 788 |
+
HYBRIDS_INDEX_LENGTH 16
|
| 789 |
+
HYBRIDG_HIST_LENGTH 16
|
| 790 |
+
HYBRIDP_HIST_LENGTH 16
|
| 791 |
+
FILTER_INDEX_LENGTH 16
|
| 792 |
+
USE_FILTER FALSE
|
| 793 |
+
INF_HYBRIDGP FALSE
|
| 794 |
+
BP_HASH_TOS FALSE
|
| 795 |
+
IBTB_HASH_TOS FALSE
|
| 796 |
+
BTB_MECH GENERIC_BTB generic
|
| 797 |
+
BTB_ENTRIES 12288 12288
|
| 798 |
+
BTB_ASSOC 4 4
|
| 799 |
+
BTB_NUM_BRSLOT 1
|
| 800 |
+
BTB_BLOCK_SIZE 64
|
| 801 |
+
BTB_OFF_PATH_WRITES TRUE 1
|
| 802 |
+
BTB_MAIN_LATENCY 3 3
|
| 803 |
+
BTB_L0_PRESENT FALSE 1
|
| 804 |
+
BTB_L0_ENTRIES 128 128
|
| 805 |
+
BTB_L0_ASSOC 4 4
|
| 806 |
+
BTB_L0_LATENCY 1 1
|
| 807 |
+
BTB_L1_PRESENT FALSE 1
|
| 808 |
+
BTB_L1_ENTRIES 6144 6144
|
| 809 |
+
BTB_L1_ASSOC 4 4
|
| 810 |
+
BTB_L1_LATENCY 2 2
|
| 811 |
+
ENABLE_CRS TRUE 1
|
| 812 |
+
CRS_ENTRIES 32 128
|
| 813 |
+
CRS_REALISTIC 0 1
|
| 814 |
+
ENABLE_IBP TRUE 1 # Enable the indirect branch predictor
|
| 815 |
+
USE_PAT_HIST TRUE
|
| 816 |
+
IBTB_MECH 1 tc_tagged
|
| 817 |
+
IBTB_HIST_LENGTH 16
|
| 818 |
+
IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb.
|
| 819 |
+
TARGETS_IN_HIST 4
|
| 820 |
+
TC_ENTRIES (4 * 1024) 4096
|
| 821 |
+
TC_ASSOC 4 4
|
| 822 |
+
NUM_CORR_BRANCHES 3
|
| 823 |
+
SEL_HIST_BP_ENTRIES 8192
|
| 824 |
+
SEL_HIST_LENGTH 16
|
| 825 |
+
SEL_HIST_DYN_CNT_TH 16
|
| 826 |
+
SEL_HIST_MISPRED_TH 4
|
| 827 |
+
ENABLE_BP_CONF FALSE
|
| 828 |
+
CONF_MECH 0
|
| 829 |
+
PERF_BP_CONF_PRED FALSE
|
| 830 |
+
BPC_BITS 16
|
| 831 |
+
BPC_MECH 1
|
| 832 |
+
BPC_CTR_RESET TRUE
|
| 833 |
+
BPC_CIT_BITS 8
|
| 834 |
+
BPC_CIT_TH 50
|
| 835 |
+
BPC_CTR_BITS 3
|
| 836 |
+
OPC_COUNT_ZEROS FALSE
|
| 837 |
+
OPC_COUNT_THRESH 10
|
| 838 |
+
INF_LOOP FALSE
|
| 839 |
+
INF_LOOP_BUCKETS 811
|
| 840 |
+
LOOP_ENTRIES (4 * 1024)
|
| 841 |
+
LOOP_ASSOC 4
|
| 842 |
+
LOOP_COUNT_MAX 127
|
| 843 |
+
LOOP_REPEAT_MAX 15
|
| 844 |
+
KNOB_PRINT_BRINFO FALSE
|
| 845 |
+
BR_MISPRED_FILE NULL
|
| 846 |
+
SPEC_LEVEL 3
|
| 847 |
+
RANDOM_DETERMINISTIC TRUE
|
| 848 |
+
TAGESCL64KB_SC TRUE
|
| 849 |
+
TAGESCL64KB_LOOP TRUE
|
| 850 |
+
TAGESCL64KB_ALT TRUE
|
| 851 |
+
CONF_PERCEPTRON_TH 0
|
| 852 |
+
CONF_PERCEPTRON_CTR_BITS 8
|
| 853 |
+
CONF_PERCEPTRON_ENTRIES 127
|
| 854 |
+
CONF_PERCEPTRON_THRESH_OVRD 0
|
| 855 |
+
CONF_HIST_LENGTH 32
|
| 856 |
+
PERCEPTRON_CONF_USE_CONF FALSE
|
| 857 |
+
PERCEPTRON_CONF_TRAIN_HIS FALSE
|
| 858 |
+
PERCEPTRON_CONF_TRAIN_CONF FALSE
|
| 859 |
+
PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE
|
| 860 |
+
PERCEPTRON_TRAIN_MISP_FACTOR 1
|
| 861 |
+
PERCEPTRON_TRAIN_CORR_FACTOR 1
|
| 862 |
+
PERCEPTRON_CONF_HIS_BOTH FALSE
|
| 863 |
+
PERCEPTRON_CONF_HIS_BOTH_LENGTH 4
|
| 864 |
+
MTAGE_REALISTIC_SC_40K FALSE
|
| 865 |
+
MTAGE_REALISTIC_SC_100K FALSE
|
| 866 |
+
H2P_TABLE_BUCKETS 16384
|
| 867 |
+
H2P_MIN_EXEC 5000
|
| 868 |
+
H2P_MIN_MISPRED 333
|
| 869 |
+
H2P_MISPRED_RATIO_PERMIL 10
|
| 870 |
+
H2P_TRACK_CBR TRUE
|
| 871 |
+
H2P_TRACK_REP TRUE
|
| 872 |
+
H2P_TRACK_CALL FALSE
|
| 873 |
+
H2P_TRACK_IBR FALSE
|
| 874 |
+
H2P_TRACK_ICALL FALSE
|
| 875 |
+
H2P_TRACK_RET FALSE
|
| 876 |
+
POWER_INTF_ON FALSE
|
| 877 |
+
POWER_INTF_ENABLE_SCALING FALSE
|
| 878 |
+
POWER_INTF_EXEC "power/power_intf.py"
|
| 879 |
+
POWER_INTF_REF_CHIP_TECH_NM 22
|
| 880 |
+
POWER_INTF_REF_CHIP_FREQ (3.2e9)
|
| 881 |
+
POWER_INTF_REF_MEMORY_FREQ (0.8e9)
|
| 882 |
+
POWER_OTHER (0.0)
|
| 883 |
+
PREF_STREAM_ON FALSE 1
|
| 884 |
+
PREF_STREAM_PER_CORE_ENABLE FALSE
|
| 885 |
+
STREAM_BUFFER_N 16
|
| 886 |
+
STREAM_PREFETCH_N 2 4
|
| 887 |
+
STREAM_START_DIS 5 1
|
| 888 |
+
STREAM_LENGTH 16 64
|
| 889 |
+
STREAM_FULL_N 1
|
| 890 |
+
STREAM_TRAIN_LENGTH 16
|
| 891 |
+
STREAM_TRAIN_NUM 1 4
|
| 892 |
+
PREF_ACC_USE_CACHE FALSE
|
| 893 |
+
STREAM_STALL_ON_QUEUE_FULL FALSE
|
| 894 |
+
PREF_SCHEDULE_NUM 4
|
| 895 |
+
TRAIN_FILTER_SIZE 32
|
| 896 |
+
PREF_REQ_Q_SIZE 64
|
| 897 |
+
STREAM_CREATE_ON_DC_MISS FALSE 0
|
| 898 |
+
STREAM_CREATE_ON_L1_MISS TRUE 1
|
| 899 |
+
STREAM_TRAIN_ON_WRONGPATH TRUE
|
| 900 |
+
STREAM_CREATE_ON_WRONGPATH TRUE
|
| 901 |
+
STREAM_PREF_INTO_DCACHE FALSE
|
| 902 |
+
REMOVE_REDUNDANT_STREAM FALSE
|
| 903 |
+
L2HIT_STREAM_SCHEDULE_NUM 4
|
| 904 |
+
PREF_REQ_QUEUE_FILTER_ON FALSE
|
| 905 |
+
HW_PREF_HIT_TRAIN_STREAM FALSE
|
| 906 |
+
L2HIT_STREAM_BUFFER_N 32
|
| 907 |
+
L2HIT_STREAM_PREFETCH_N 2
|
| 908 |
+
L2HIT_STREAM_START_DIS 2
|
| 909 |
+
L2HIT_STREAM_LENGTH 8
|
| 910 |
+
L2HIT_PREF_REQ_Q_SIZE 128
|
| 911 |
+
L2HIT_L2ACCESS_REQ_Q_SIZE 64
|
| 912 |
+
PREF_STREAM_ACCPERSTREAM FALSE
|
| 913 |
+
PREF_ACC_DISTANCE_10 128
|
| 914 |
+
PREF_FRAMEWORK_ON FALSE 1
|
| 915 |
+
PREF_TRACE_ON FALSE
|
| 916 |
+
PREF_UMLC_ON FALSE
|
| 917 |
+
PREF_UL1_ON TRUE
|
| 918 |
+
PREF_DL0REQ_QUEUE_SIZE 32
|
| 919 |
+
PREF_UMLC_REQ_QUEUE_SIZE 64
|
| 920 |
+
PREF_UL1REQ_QUEUE_SIZE 128
|
| 921 |
+
PREF_SHARED_QUEUES TRUE
|
| 922 |
+
PREF_DL0_MISS_ON TRUE
|
| 923 |
+
PREF_DL0_HIT_ON TRUE
|
| 924 |
+
PREF_DL0REQ_QUEUE_FILTER_ON TRUE
|
| 925 |
+
PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE
|
| 926 |
+
PREF_UL1REQ_QUEUE_FILTER_ON TRUE
|
| 927 |
+
PREF_DL0REQ_ADD_FILTER_ON TRUE
|
| 928 |
+
PREF_UMLC_REQ_ADD_FILTER_ON TRUE
|
| 929 |
+
PREF_UL1REQ_ADD_FILTER_ON TRUE
|
| 930 |
+
PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 931 |
+
PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 932 |
+
PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1
|
| 933 |
+
PREF_DL0SCHEDULE_NUM 4
|
| 934 |
+
PREF_UMLC_SCHEDULE_NUM 4
|
| 935 |
+
PREF_UL1SCHEDULE_NUM 4
|
| 936 |
+
PREF_L1Q_DEMAND_RESERVE 0
|
| 937 |
+
PREF_REPORT_PREF_MATCH_AS_MISS FALSE
|
| 938 |
+
PREF_REPORT_PREF_MATCH_AS_HIT TRUE
|
| 939 |
+
PREF_UPDATE_ON_WRONGPATH TRUE
|
| 940 |
+
PREF_TRAIN_ON_PREF_MISSES FALSE 0
|
| 941 |
+
PREF_ORACLE_TRAIN_ON FALSE 0
|
| 942 |
+
PREF_REQ_DROP FALSE
|
| 943 |
+
PREF_THROTTLE_ON FALSE
|
| 944 |
+
PREF_THROTTLEFB_ON FALSE 1
|
| 945 |
+
PREF_ACC_THRESH_1 0.90 0.75
|
| 946 |
+
PREF_ACC_THRESH_2 0.70 0.4
|
| 947 |
+
PREF_ACC_THRESH_3 0.60 0.4
|
| 948 |
+
PREF_ACC_THRESH_4 0.40
|
| 949 |
+
PREF_UPDATE_INTERVAL 0 8192
|
| 950 |
+
PREF_ANALYZE_LOAD FALSE
|
| 951 |
+
PREF_POL_THRESH_1 0.25
|
| 952 |
+
PREF_POL_THRESH_2 0.10
|
| 953 |
+
PREF_POLBV_ON FALSE
|
| 954 |
+
PREF_POLBV_SIZE 1024
|
| 955 |
+
PREF_TIMELY_THRESH 0.05 0.01
|
| 956 |
+
PREF_POLPF_THRESH 0.01 0.005
|
| 957 |
+
PREF_DEGFB_USEONLYACC FALSE
|
| 958 |
+
PREF_DEGFB_USEONLYPOL FALSE
|
| 959 |
+
PREF_DEGFB_USEONLYLATE FALSE
|
| 960 |
+
PREF_TIMELY_THRESH_2 0.005
|
| 961 |
+
PREF_DEGFB_STATPHASEFILE FALSE
|
| 962 |
+
PREF_MAX_DEGFB 4
|
| 963 |
+
PREF_DHAL FALSE
|
| 964 |
+
PREF_DHAL_SENTTHRESH 16
|
| 965 |
+
PREF_DHAL_USETHRESH_MAX 12
|
| 966 |
+
PREF_DHAL_USETHRESH_MIN2 8
|
| 967 |
+
PREF_DHAL_USETHRESH_MIN1 4
|
| 968 |
+
PREF_DHAL_MAXDEG 64
|
| 969 |
+
PREF_HFILTER_ON FALSE
|
| 970 |
+
PREF_HFILTER_INDEX_BITS 12
|
| 971 |
+
PREF_HFILTER_USE_PC FALSE
|
| 972 |
+
PREF_HFILTER_PRED_USELESS_THRES 2
|
| 973 |
+
PREF_HFILTER_RESET_ENABLE FALSE
|
| 974 |
+
PREF_HFILTER_RESET_INTERVAL 100000
|
| 975 |
+
EIP_ENABLE 0
|
| 976 |
+
L1I_ENTANGLED_TABLE_INDEX_BITS 9
|
| 977 |
+
L1I_ENTANGLED_TABLE_WAYS 16
|
| 978 |
+
DJOLT_ENABLE 0
|
| 979 |
+
FNLMMA_ENABLE 0
|
| 980 |
+
FDIP_ENABLE 1
|
| 981 |
+
FDIP_ALWAYS_PREFETCH FALSE
|
| 982 |
+
PERFECT_FDIP FALSE
|
| 983 |
+
IPRF_MAX_FTQ_ENTRY_CYC 2
|
| 984 |
+
FDIP_BLOOM_FILTER FALSE
|
| 985 |
+
FDIP_BLOOM_ENTRIES 4000
|
| 986 |
+
FDIP_BLOOM2_ENTRIES 1000
|
| 987 |
+
FDIP_BLOOM4_ENTRIES 1000
|
| 988 |
+
FDIP_BLOOM_SIZE 16384
|
| 989 |
+
FDIP_BLOOM_HASHES 6
|
| 990 |
+
FDIP_BLOOM_CLEAR_UNUSEFUL_RATIO 0.95
|
| 991 |
+
FDIP_BLOOM_CLEAR_CYC_PERIOD 10000
|
| 992 |
+
FDIP_UTILITY_HASH_ENABLE 0
|
| 993 |
+
FDIP_UTILITY_PREF_POLICY 0
|
| 994 |
+
FDIP_ADJUSTABLE_FTQ 0
|
| 995 |
+
FDIP_ADJUSTABLE_FTQ_CYC 100000
|
| 996 |
+
UTILITY_RATIO_THRESHOLD 0.58
|
| 997 |
+
TIMELINESS_RATIO_THRESHOLD 0.82
|
| 998 |
+
FDIP_PREF_NO_LATENCY FALSE
|
| 999 |
+
UDP_USEFUL_THRESHOLD 0
|
| 1000 |
+
UDP_WEIGHT_USEFUL 4
|
| 1001 |
+
UDP_WEIGHT_UNUSEFUL 1
|
| 1002 |
+
UDP_WEIGHT_POSITIVE_SATURATION 2147483647
|
| 1003 |
+
FDIP_GHIST_HASHING FALSE
|
| 1004 |
+
FDIP_UTILITY_ONLY_TRAIN_OFF_PATH FALSE
|
| 1005 |
+
FDIP_GHIST_BITS 8
|
| 1006 |
+
UFTQ_MIN_FTQ_BLOCK_NUM 4
|
| 1007 |
+
UFTQ_MAX_FTQ_BLOCK_NUM 64
|
| 1008 |
+
FDIP_SENIORITY_FTQ_HOLD_CYC 30000
|
| 1009 |
+
FDIP_PERFECT_PREFETCH FALSE
|
| 1010 |
+
FDIP_FREEZE_AT_MEM_BUF_LIMIT TRUE
|
| 1011 |
+
FDIP_DUAL_PATH_PREF_IC_ENABLE FALSE
|
| 1012 |
+
FDIP_DUAL_PATH_PREF_UOC_ENABLE FALSE
|
| 1013 |
+
TOP_MISPRED_BR_FILEPATH "br_resteer_coverage.csv"
|
| 1014 |
+
TOP_MISPRED_BR_RESTEER_COVERAGE 0
|
| 1015 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_ENABLE FALSE
|
| 1016 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_MISPRED_THRESHOLD 1
|
| 1017 |
+
FDIP_PRINT_CL_INFO FALSE
|
| 1018 |
+
BRANCH_MISPREDICTION_TABLE_SIZE 0
|
| 1019 |
+
UOC_PREF FALSE
|
| 1020 |
+
UOC_ORACLE_PREF FALSE
|
| 1021 |
+
UOC_ZERO_LATENCY_PREF FALSE
|
| 1022 |
+
L2L1PREF_ON FALSE
|
| 1023 |
+
L2WAY_PREF FALSE
|
| 1024 |
+
L2MARKV_PREF_ON FALSE
|
| 1025 |
+
L2NEXT_PREF_ON FALSE
|
| 1026 |
+
L2HIT_STREAM_PREF_ON FALSE
|
| 1027 |
+
L2L1_DC_HIT_TRAIN FALSE
|
| 1028 |
+
L1_HIT_DUMP_FILE_ON FALSE
|
| 1029 |
+
L1_HIT_DUMP_WO_TXT FALSE
|
| 1030 |
+
L1_HIT_DUMPFILE "l1hit_dump.out"
|
| 1031 |
+
IDEAL_L2_L1_PREFETCHER FALSE
|
| 1032 |
+
IDEAL_L2_ICACHE_PREFETCHER FALSE
|
| 1033 |
+
L1WAY_PREF_SEND_QUEUE 4
|
| 1034 |
+
L1PREF_REQ_QUEUE_SIZE 1024
|
| 1035 |
+
L1PREF_IMMEDIATE FALSE
|
| 1036 |
+
L1WAY_PREF_TIMER_DIS 1000
|
| 1037 |
+
L1MARKV_PREF_SEND_QUEUE 4
|
| 1038 |
+
L1PREF_MARKV_REQ_QUEUE_SIZE 1024
|
| 1039 |
+
MARKV_L2ACCESS_REQ_Q_SIZE 64
|
| 1040 |
+
L1MARKV_PREF_IMMEDIATE FALSE
|
| 1041 |
+
L1MARKV_PREF_TIMER_DIS 1
|
| 1042 |
+
L2L1_HIT_TRAIN TRUE
|
| 1043 |
+
L1MARKV_REQ_TH 1
|
| 1044 |
+
L2L1_IMMEDIATE_PREF_CACHE FALSE
|
| 1045 |
+
L2L1_FILL_PREF_CACHE FALSE
|
| 1046 |
+
L2L1_L2_HIT_STAT FALSE
|
| 1047 |
+
PREF_GHB_ON FALSE
|
| 1048 |
+
DEBUG_PREF_GHB FALSE
|
| 1049 |
+
PREF_GHB_BUFFER_N 1024
|
| 1050 |
+
PREF_GHB_INDEX_N 128
|
| 1051 |
+
PREF_GHB_CZONE_BITS 12
|
| 1052 |
+
PREF_GHB_DEGREE 16
|
| 1053 |
+
PREF_GHB_MAX_DEGREE 32
|
| 1054 |
+
PREF_STRIDE_ON FALSE
|
| 1055 |
+
DEBUG_PREF_STRIDE FALSE
|
| 1056 |
+
PREF_STRIDE_TABLE_N 1024
|
| 1057 |
+
PREF_STRIDE_REGION_BITS 16
|
| 1058 |
+
PREF_STRIDE_DEGREE 4
|
| 1059 |
+
PREF_STRIDE_DISTANCE 16
|
| 1060 |
+
PREF_STRIDE_STARTDISTANCE 1
|
| 1061 |
+
PREF_STRIDE_SINGLE_THRESH 6
|
| 1062 |
+
PREF_STRIDE_MULTI_THRESH 6
|
| 1063 |
+
PREF_STRIDE_SINGLE_STRIDE_MODE FALSE
|
| 1064 |
+
PREF_STRIDEPC_ON FALSE
|
| 1065 |
+
DEBUG_PREF_STRIDEPC FALSE
|
| 1066 |
+
PREF_STRIDEPC_TABLE_N 1024
|
| 1067 |
+
PREF_STRIDEPC_DEGREE 4
|
| 1068 |
+
PREF_STRIDEPC_DISTANCE 16
|
| 1069 |
+
PREF_STRIDEPC_USELOADADDR FALSE
|
| 1070 |
+
PREF_STRIDEPC_TRAINNUM 2
|
| 1071 |
+
PREF_STRIDEPC_STARTDIS 4
|
| 1072 |
+
PREF_PHASE_ON FALSE
|
| 1073 |
+
PREF_PHASE_STUDY FALSE
|
| 1074 |
+
DEBUG_PREF_PHASE FALSE
|
| 1075 |
+
PREF_PHASE_PRIME_HASH 16381
|
| 1076 |
+
PREF_PHASE_INFOSIZE 16384
|
| 1077 |
+
PREF_PHASE_LOG2REGIONSIZE 12
|
| 1078 |
+
PREF_PHASE_REGIONENTRIES 64
|
| 1079 |
+
PREF_PHASE_TRACKEDREGIONS 32
|
| 1080 |
+
PREF_PHASE_INTERVAL 100000
|
| 1081 |
+
PREF_PHASE_TABLE_SIZE 64
|
| 1082 |
+
PREF_PHASE_MAXDIFF_THRESH 64
|
| 1083 |
+
PREF_PHASE_MIN_MISSES 64
|
| 1084 |
+
PREF_PHASE_MISSPER 0.4
|
| 1085 |
+
PREF_2DC_ON FALSE
|
| 1086 |
+
DEBUG_PREF_2DC FALSE
|
| 1087 |
+
PREF_2DC_CACHE_SIZE (1 * 1024)
|
| 1088 |
+
PREF_2DC_CACHE_ASSOC 4
|
| 1089 |
+
PREF_2DC_CACHE_LINE_SIZE 1
|
| 1090 |
+
PREF_2DC_DEGREE 16
|
| 1091 |
+
PREF_2DC_ZONE_SHIFT 10
|
| 1092 |
+
PREF_2DC_TAG_SIZE 16
|
| 1093 |
+
PREF_2DC_NUM_REGIONS 64
|
| 1094 |
+
PREF_2DC_REGION_HASH 61
|
| 1095 |
+
PREF_MARKOV_ON FALSE
|
| 1096 |
+
DEBUG_PREF_MARKOV FALSE
|
| 1097 |
+
PREF_MARKOV_NUM_ENTRIES 65536
|
| 1098 |
+
PREF_MARKOV_NUM_NEXT_STATES 8
|
| 1099 |
+
PREF_MARKOV_SEND_ON_PREF_HIT TRUE
|
| 1100 |
+
PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE
|
| 1101 |
+
PREF_MARKOV_TABLE_UPDATE_POLICY 0
|
| 1102 |
+
PREF_MARKOV_SEND_THRESHOLD 0
|
sssp_facebook/fingerprint/run_5/sim.log
ADDED
|
@@ -0,0 +1,59 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
[0]: ad: 0x7ffff3d9b7b7, op: 109
|
| 2 |
+
[0]: ad: 0x7ffff3d9b7bb, op: 315
|
| 3 |
+
new bb detected: 1
|
| 4 |
+
[1]: ad: 0x7ffff3d9b7c1, op: 427
|
| 5 |
+
[1]: ad: 0x7ffff3d9b7c8, op: 427
|
| 6 |
+
[1]: ad: 0x7ffff3d9b7cc, op: 847
|
| 7 |
+
[1]: ad: 0x7ffff3d9b7cf, op: 330
|
| 8 |
+
new bb detected: 2
|
| 9 |
+
[2]: ad: 0x7ffff3d9b7b0, op: 388
|
| 10 |
+
[2]: ad: 0x7ffff3d9b7b3, op: 8
|
| 11 |
+
[2]: ad: 0x7ffff3d9b7b7, op: 109
|
| 12 |
+
[2]: ad: 0x7ffff3d9b7bb, op: 315
|
| 13 |
+
new bb detected: 3
|
| 14 |
+
Scarab gitrev: 7185dea
|
| 15 |
+
Warning: Scarab expects the trace file type to include OFFLINE_FILE_TYPE_ARCH_REGDEPS (0x20000), but got type: 0xe40
|
| 16 |
+
Scarab started at Fri Jul 17 23:07:24 2026
|
| 17 |
+
|
| 18 |
+
read from initialization: 0x7ffff3d9b7b7
|
| 19 |
+
advanceReader: ROI end reached (ordinal 60000002 > roi_end 60000000)
|
| 20 |
+
Reached end of trace (last_inst) pc=0x7ffff3d9b7b7
|
| 21 |
+
[3]: ad: 0x7ffff3d9b7b0, op: 388
|
| 22 |
+
[3]: ad: 0x7ffff3d9b7b3, op: 8
|
| 23 |
+
DUP bb detected at trace end
|
| 24 |
+
to be appened segment num 1
|
| 25 |
+
10000000
|
| 26 |
+
10000000
|
| 27 |
+
====================================
|
| 28 |
+
TRACE_INST_TAKEN_NOT_CF:0
|
| 29 |
+
TRACE_INST_TAKEN_CF_BR:0
|
| 30 |
+
TRACE_INST_TAKEN_CF_CBR:1250000
|
| 31 |
+
TRACE_INST_TAKEN_CF_REP:0
|
| 32 |
+
TRACE_INST_TAKEN_CF_CALL:0
|
| 33 |
+
TRACE_INST_TAKEN_CF_IBR:0
|
| 34 |
+
TRACE_INST_TAKEN_CF_ICALL:0
|
| 35 |
+
TRACE_INST_TAKEN_CF_ICO:0
|
| 36 |
+
TRACE_INST_TAKEN_CF_RET:0
|
| 37 |
+
TRACE_INST_TAKEN_CF_SYS:0
|
| 38 |
+
====================================
|
| 39 |
+
identity within this segment
|
| 40 |
+
2 bbs with same first pc
|
| 41 |
+
[3]: size 4, freq 1249999
|
| 42 |
+
7ffff3d9b7b0: 388, 0
|
| 43 |
+
7ffff3d9b7b3: 8, 0
|
| 44 |
+
7ffff3d9b7b7: 109, 0
|
| 45 |
+
7ffff3d9b7bb: 315, 0
|
| 46 |
+
[3]: size 2, freq 1
|
| 47 |
+
7ffff3d9b7b0: 388, 0
|
| 48 |
+
7ffff3d9b7b3: 8, 0
|
| 49 |
+
1 / 3
|
| 50 |
+
========================================================
|
| 51 |
+
Number of blocks built : 3
|
| 52 |
+
Average size : 3.33 instructions
|
| 53 |
+
Number of blocks executed : 2500001
|
| 54 |
+
Average weighted size : 4.00 instructions
|
| 55 |
+
Number of total instructions : 10000000
|
| 56 |
+
Number of fetched instruction : 10000000
|
| 57 |
+
========================================================
|
| 58 |
+
Scarab finished at Fri Jul 17 23:07:28 2026
|
| 59 |
+
|
sssp_facebook/fingerprint/run_6/PARAMS.in
ADDED
|
@@ -0,0 +1,268 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# File : PARAMS.golden_cove
|
| 2 |
+
# Date : 02/27/25
|
| 3 |
+
# Description : Golden Cove Configuration
|
| 4 |
+
# Author : Surim Oh <[email protected]>
|
| 5 |
+
#
|
| 6 |
+
# Based on documentation found here:
|
| 7 |
+
# https://en.wikipedia.org/wiki/Golden_Cove
|
| 8 |
+
# https://en.wikichip.org/wiki/intel/microarchitectures/golden_cove
|
| 9 |
+
# https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/3
|
| 10 |
+
|
| 11 |
+
## Simulation Parameters
|
| 12 |
+
--mode full
|
| 13 |
+
--model cmp
|
| 14 |
+
--sim_limit none
|
| 15 |
+
|
| 16 |
+
## Core Parameters
|
| 17 |
+
|
| 18 |
+
# Femptoseconds, 3.2GHz, used for energy estimates.
|
| 19 |
+
--chip_cycle_time 312500
|
| 20 |
+
|
| 21 |
+
|
| 22 |
+
### Fetch Stage
|
| 23 |
+
--fetch_off_path_ops 1
|
| 24 |
+
|
| 25 |
+
#### ICache
|
| 26 |
+
--icache_size 32768
|
| 27 |
+
--icache_assoc 8
|
| 28 |
+
--icache_line_size 64
|
| 29 |
+
|
| 30 |
+
### Uop Cache
|
| 31 |
+
# inclusive w/ L1i
|
| 32 |
+
--uop_cache_enable 1
|
| 33 |
+
--uop_cache_width 8
|
| 34 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 35 |
+
--uop_cache_assoc 8
|
| 36 |
+
--iprf_on_uop_cache_hit 1
|
| 37 |
+
|
| 38 |
+
### Branch Predictor
|
| 39 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 40 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 41 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 42 |
+
--bp_mech tage64k
|
| 43 |
+
|
| 44 |
+
|
| 45 |
+
#### BTB
|
| 46 |
+
|
| 47 |
+
# TODO
|
| 48 |
+
# multi-level BTB
|
| 49 |
+
# 128 entry L0 BTB
|
| 50 |
+
# 6144 entry L1 BTB
|
| 51 |
+
# 12888 entry L2 BTB
|
| 52 |
+
# ~2 entry Return Stack
|
| 53 |
+
# roughly 2x8192 for now
|
| 54 |
+
# BTB model to use.
|
| 55 |
+
--btb_mech generic
|
| 56 |
+
--btb_entries 12288
|
| 57 |
+
--btb_assoc 4
|
| 58 |
+
--btb_main_latency 3
|
| 59 |
+
--btb_l0_present 1
|
| 60 |
+
--btb_l0_entries 128
|
| 61 |
+
--btb_l0_assoc 4
|
| 62 |
+
--btb_l0_latency 1
|
| 63 |
+
--btb_l1_present 1
|
| 64 |
+
--btb_l1_entries 6144
|
| 65 |
+
--btb_l1_assoc 4
|
| 66 |
+
--btb_l1_latency 2
|
| 67 |
+
|
| 68 |
+
# Allow the BTB to be updated by off path ops.
|
| 69 |
+
--btb_off_path_writes 1
|
| 70 |
+
|
| 71 |
+
# NT branches are not inserted in BTB, but do not trigger resteer
|
| 72 |
+
# since we continue without a control flow change
|
| 73 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 74 |
+
|
| 75 |
+
#### CRS
|
| 76 |
+
|
| 77 |
+
# Enable return stack
|
| 78 |
+
--enable_crs 1
|
| 79 |
+
--crs_entries 128
|
| 80 |
+
--crs_realistic 1
|
| 81 |
+
|
| 82 |
+
### iBP
|
| 83 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 84 |
+
--ibtb_mech tc_tagged
|
| 85 |
+
# iBTB Model. tc_tagless, tc_tagged, tc_hybrid.
|
| 86 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 87 |
+
--tc_entries 4096
|
| 88 |
+
--tc_assoc 4
|
| 89 |
+
|
| 90 |
+
### Decode Stage
|
| 91 |
+
--decode_width 6
|
| 92 |
+
--decode_cycles 5
|
| 93 |
+
|
| 94 |
+
### Instruction Decode Queue
|
| 95 |
+
--idq_size 144
|
| 96 |
+
|
| 97 |
+
### Map Stage
|
| 98 |
+
--map_cycles 5
|
| 99 |
+
|
| 100 |
+
# register renaming table
|
| 101 |
+
--reg_renaming_scheme 1
|
| 102 |
+
--reg_table_integer_physical_size 280
|
| 103 |
+
--reg_table_vector_physical_size 332
|
| 104 |
+
|
| 105 |
+
### Issue Stage
|
| 106 |
+
|
| 107 |
+
# Max number of instructions to be renamed, and issued per cycle.
|
| 108 |
+
--issue_width 6
|
| 109 |
+
|
| 110 |
+
--rs_fill_width 0
|
| 111 |
+
# rs_sizes ~205 in total, and they are split into three different reservation stations (RS1, RS2, RS3) where each has 97, 70, 38 entries respectively
|
| 112 |
+
# original architecture
|
| 113 |
+
# RS1 connected to port 0,1,5,6,10
|
| 114 |
+
# RS2 connected to port 2,3,11
|
| 115 |
+
# RS3 connected to port 7,8,4,9
|
| 116 |
+
# scarab does not split ST AGU port and ST port, merge them
|
| 117 |
+
# adjusted architecture to scarab ST AGU (port 4 and 9 removed. rs_size reduced to 186 from 205)
|
| 118 |
+
# RS1 connected to port 0,1,4,5,8
|
| 119 |
+
# RS2 connected to port 2,3,9
|
| 120 |
+
# RS3 connected to port 6,7 (port 4,9 removed, entries reduced to 19 from 38)
|
| 121 |
+
--rs_sizes 97 70 19
|
| 122 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 123 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 124 |
+
|
| 125 |
+
### Exec Stage
|
| 126 |
+
|
| 127 |
+
### DCache
|
| 128 |
+
--dcache_size 49152
|
| 129 |
+
--dcache_read_ports 1
|
| 130 |
+
--dcache_write_ports 1
|
| 131 |
+
--dcache_banks 8
|
| 132 |
+
--dcache_assoc 12
|
| 133 |
+
--dcache_line_size 64
|
| 134 |
+
--dcache_cycles 5
|
| 135 |
+
|
| 136 |
+
### Reorder/Retire Stage
|
| 137 |
+
|
| 138 |
+
# Max number of instructions to be retired per cycle.
|
| 139 |
+
--node_ret_width 8
|
| 140 |
+
--node_table_size 512
|
| 141 |
+
|
| 142 |
+
# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does
|
| 143 |
+
--stores_do_not_block_window 1
|
| 144 |
+
|
| 145 |
+
# TODO: confirm what this knob does
|
| 146 |
+
--prefs_do_not_block_window 1
|
| 147 |
+
|
| 148 |
+
|
| 149 |
+
## Uncore
|
| 150 |
+
|
| 151 |
+
### Mid-level cache
|
| 152 |
+
|
| 153 |
+
# Enable use of a midlevel cache between i/d and L1
|
| 154 |
+
# client 1.25 MiB (1310720 bytes) per core, 8-way, 15 cycles
|
| 155 |
+
# server 2 MiB (2097000 bytes) per core, 8-way, 16 cycles
|
| 156 |
+
--mlc_present 1
|
| 157 |
+
--mlc_size 2097000
|
| 158 |
+
--mlc_assoc 8
|
| 159 |
+
--mlc_cycles 16
|
| 160 |
+
|
| 161 |
+
|
| 162 |
+
### LLC
|
| 163 |
+
# 3 MiB per core, 16-way
|
| 164 |
+
--l1_size 3145728
|
| 165 |
+
--l1_banks 8
|
| 166 |
+
--l1_cycles 36 // just a guess
|
| 167 |
+
--l1_assoc 16
|
| 168 |
+
--l1_line_size 64
|
| 169 |
+
--l1_interleave_factor 64
|
| 170 |
+
|
| 171 |
+
|
| 172 |
+
### prefetcher
|
| 173 |
+
# Kept same as Kaby Lake
|
| 174 |
+
--pref_framework_on 1
|
| 175 |
+
--pref_stream_on 1
|
| 176 |
+
--pref_train_on_pref_misses 0
|
| 177 |
+
--pref_oracle_train 0
|
| 178 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 179 |
+
|
| 180 |
+
--stream_length 64
|
| 181 |
+
--stream_prefetch_n 4
|
| 182 |
+
--stream_start_dis 1
|
| 183 |
+
--stream_train_num 4
|
| 184 |
+
--stream_create_on_dc_miss 0
|
| 185 |
+
--stream_create_on_l1_miss 1
|
| 186 |
+
|
| 187 |
+
--pref_throttlefb_on=1
|
| 188 |
+
--pref_acc_thresh_1=0.75
|
| 189 |
+
--pref_acc_thresh_2=0.4
|
| 190 |
+
--pref_acc_thresh_3=0.4
|
| 191 |
+
--pref_timely_thresh=0.01
|
| 192 |
+
--pref_polpf_thresh=0.005
|
| 193 |
+
--pref_update_interval=8192
|
| 194 |
+
|
| 195 |
+
--mem_req_buffer_pref_watermark 4
|
| 196 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 197 |
+
|
| 198 |
+
### Memory
|
| 199 |
+
# Kept same as Kaby Lake
|
| 200 |
+
--addr_translation random
|
| 201 |
+
|
| 202 |
+
--mem_priority_ifetch 0
|
| 203 |
+
--mem_priority_dfetch 1
|
| 204 |
+
--mem_priority_dstore 2
|
| 205 |
+
--mem_priority_iprf 3
|
| 206 |
+
--mem_priority_dprf 4
|
| 207 |
+
--mem_priority_wb 5
|
| 208 |
+
--mem_priority_wb_nodirty 5
|
| 209 |
+
|
| 210 |
+
--mem_req_buffer_entries 32
|
| 211 |
+
--bus_width_in_bytes 8
|
| 212 |
+
|
| 213 |
+
--ramulator_standard DDR4
|
| 214 |
+
--ramulator_speed DDR4_2400R
|
| 215 |
+
--ramulator_org DDR4_8Gb_x8
|
| 216 |
+
--ramulator_channels 1
|
| 217 |
+
--ramulator_ranks 1
|
| 218 |
+
--ramulator_bankgroups 4
|
| 219 |
+
--ramulator_banks 4
|
| 220 |
+
--ramulator_chip_width 8
|
| 221 |
+
--ramulator_rows 65536
|
| 222 |
+
--ramulator_cols 1024
|
| 223 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 224 |
+
--ramulator_readq_entries 32
|
| 225 |
+
--ramulator_writeq_entries 32
|
| 226 |
+
--ramulator_record_cmd_trace FALSE
|
| 227 |
+
--ramulator_print_cmd_trace FALSE
|
| 228 |
+
--ramulator_tCK 833333
|
| 229 |
+
--ramulator_tCL 16
|
| 230 |
+
--ramulator_tCCD 6
|
| 231 |
+
--ramulator_tCCDS 4
|
| 232 |
+
--ramulator_tCCDL 6
|
| 233 |
+
--ramulator_tCWL 12
|
| 234 |
+
--ramulator_tBL 4
|
| 235 |
+
--ramulator_tWTR 9
|
| 236 |
+
--ramulator_tWTRS 3
|
| 237 |
+
--ramulator_tWTRL 9
|
| 238 |
+
--ramulator_tRP 16
|
| 239 |
+
--ramulator_tRPpb 16
|
| 240 |
+
--ramulator_tRPab 16
|
| 241 |
+
--ramulator_tRCD 16
|
| 242 |
+
--ramulator_tRCDR 16
|
| 243 |
+
--ramulator_tRCDW 16
|
| 244 |
+
--ramulator_tRAS 39
|
| 245 |
+
--dram_tech_in_nm 32
|
| 246 |
+
|
| 247 |
+
## Other
|
| 248 |
+
|
| 249 |
+
|
| 250 |
+
### Debug
|
| 251 |
+
--debug_inst_start 0
|
| 252 |
+
--debug_inst_stop -1
|
| 253 |
+
--debug_cycle_start 0
|
| 254 |
+
--debug_cycle_stop -1
|
| 255 |
+
|
| 256 |
+
|
| 257 |
+
## Stats and Params
|
| 258 |
+
--dump_params 1
|
| 259 |
+
--dump_stats 1
|
| 260 |
+
--dump_trace 0
|
| 261 |
+
|
| 262 |
+
####################################
|
| 263 |
+
--set_off_path_confirmed 1
|
| 264 |
+
|
| 265 |
+
--order_beyond_bus 1
|
| 266 |
+
|
| 267 |
+
--mem_ooo_stores 1
|
| 268 |
+
--mem_obey_store_dep 1
|
sssp_facebook/fingerprint/run_6/PARAMS.out
ADDED
|
@@ -0,0 +1,1102 @@
|
|
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|
| 1 |
+
--mode trace_bbv_distributed
|
| 2 |
+
--model cmp
|
| 3 |
+
--frontend memtrace
|
| 4 |
+
--sim_limit none
|
| 5 |
+
--memtrace_roi_begin 60000001
|
| 6 |
+
--memtrace_roi_end 70000000
|
| 7 |
+
--use_fetched_count 1
|
| 8 |
+
--dump_params 1
|
| 9 |
+
--dump_stats 1
|
| 10 |
+
--dump_trace 0
|
| 11 |
+
--trace_bbv_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.6
|
| 12 |
+
--trace_footprint_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.6
|
| 13 |
+
--segment_instr_count 10000000
|
| 14 |
+
--mlc_present 1
|
| 15 |
+
--mlc_size 2097000
|
| 16 |
+
--mlc_assoc 8
|
| 17 |
+
--mlc_cycles 16
|
| 18 |
+
--l1_size 3145728
|
| 19 |
+
--l1_assoc 16
|
| 20 |
+
--l1_line_size 64
|
| 21 |
+
--l1_cycles 36 // just a guess
|
| 22 |
+
--l1_banks 8
|
| 23 |
+
--l1_interleave_factor 64
|
| 24 |
+
--addr_translation random
|
| 25 |
+
--icache_size 32768
|
| 26 |
+
--icache_assoc 8
|
| 27 |
+
--icache_line_size 64
|
| 28 |
+
--uop_cache_enable 1
|
| 29 |
+
--uop_cache_width 8
|
| 30 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 31 |
+
--uop_cache_assoc 8
|
| 32 |
+
--iprf_on_uop_cache_hit 1
|
| 33 |
+
--dcache_size 49152
|
| 34 |
+
--dcache_assoc 12
|
| 35 |
+
--dcache_line_size 64
|
| 36 |
+
--dcache_cycles 5
|
| 37 |
+
--dcache_read_ports 1
|
| 38 |
+
--dcache_write_ports 1
|
| 39 |
+
--dcache_banks 8
|
| 40 |
+
--mem_ooo_stores 1
|
| 41 |
+
--mem_obey_store_dep 1
|
| 42 |
+
--mem_req_buffer_entries 32
|
| 43 |
+
--mem_priority_ifetch 0
|
| 44 |
+
--mem_priority_dfetch 1
|
| 45 |
+
--mem_priority_dstore 2
|
| 46 |
+
--mem_priority_iprf 3
|
| 47 |
+
--mem_priority_dprf 4
|
| 48 |
+
--mem_priority_wb 5
|
| 49 |
+
--mem_priority_wb_nodirty 5
|
| 50 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 51 |
+
--mem_req_buffer_pref_watermark 4
|
| 52 |
+
--order_beyond_bus 1
|
| 53 |
+
--set_off_path_confirmed 1
|
| 54 |
+
--ramulator_standard DDR4
|
| 55 |
+
--ramulator_speed DDR4_2400R
|
| 56 |
+
--ramulator_org DDR4_8Gb_x8
|
| 57 |
+
--ramulator_channels 1
|
| 58 |
+
--ramulator_ranks 1
|
| 59 |
+
--ramulator_bankgroups 4
|
| 60 |
+
--ramulator_banks 4
|
| 61 |
+
--ramulator_chip_width 8
|
| 62 |
+
--bus_width_in_bytes 8
|
| 63 |
+
--ramulator_rows 65536
|
| 64 |
+
--ramulator_cols 1024
|
| 65 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 66 |
+
--ramulator_readq_entries 32
|
| 67 |
+
--ramulator_writeq_entries 32
|
| 68 |
+
--ramulator_record_cmd_trace FALSE
|
| 69 |
+
--ramulator_print_cmd_trace FALSE
|
| 70 |
+
--ramulator_tCK 833333
|
| 71 |
+
--ramulator_tCL 16
|
| 72 |
+
--ramulator_tCCD 6
|
| 73 |
+
--ramulator_tCCDS 4
|
| 74 |
+
--ramulator_tCCDL 6
|
| 75 |
+
--ramulator_tCWL 12
|
| 76 |
+
--ramulator_tBL 4
|
| 77 |
+
--ramulator_tWTR 9
|
| 78 |
+
--ramulator_tWTRS 3
|
| 79 |
+
--ramulator_tWTRL 9
|
| 80 |
+
--ramulator_tRP 16
|
| 81 |
+
--ramulator_tRPpb 16
|
| 82 |
+
--ramulator_tRPab 16
|
| 83 |
+
--ramulator_tRCD 16
|
| 84 |
+
--ramulator_tRCDR 16
|
| 85 |
+
--ramulator_tRCDW 16
|
| 86 |
+
--ramulator_tRAS 39
|
| 87 |
+
--dram_tech_in_nm 32
|
| 88 |
+
--chip_cycle_time 312500
|
| 89 |
+
--issue_width 6
|
| 90 |
+
--rs_fill_width 0
|
| 91 |
+
--node_table_size 512
|
| 92 |
+
--node_ret_width 8
|
| 93 |
+
--decode_width 6
|
| 94 |
+
--idq_size 144
|
| 95 |
+
--reg_renaming_scheme 1
|
| 96 |
+
--reg_table_integer_physical_size 280
|
| 97 |
+
--reg_table_vector_physical_size 332
|
| 98 |
+
--rs_sizes 97 70 19
|
| 99 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 100 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 101 |
+
--decode_cycles 5
|
| 102 |
+
--map_cycles 5
|
| 103 |
+
--fetch_off_path_ops 1
|
| 104 |
+
--stores_do_not_block_window 1
|
| 105 |
+
--prefs_do_not_block_window 1
|
| 106 |
+
--cbp_trace_r0 /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 107 |
+
--debug_cycle_start 0
|
| 108 |
+
--debug_cycle_stop -1
|
| 109 |
+
--debug_inst_start 0
|
| 110 |
+
--debug_inst_stop -1
|
| 111 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 112 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 113 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 114 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 115 |
+
--bp_mech tage64k
|
| 116 |
+
--btb_mech generic
|
| 117 |
+
--btb_entries 12288
|
| 118 |
+
--btb_assoc 4
|
| 119 |
+
--btb_off_path_writes 1
|
| 120 |
+
--btb_main_latency 3
|
| 121 |
+
--btb_l0_present 1
|
| 122 |
+
--btb_l0_entries 128
|
| 123 |
+
--btb_l0_assoc 4
|
| 124 |
+
--btb_l0_latency 1
|
| 125 |
+
--btb_l1_present 1
|
| 126 |
+
--btb_l1_entries 6144
|
| 127 |
+
--btb_l1_assoc 4
|
| 128 |
+
--btb_l1_latency 2
|
| 129 |
+
--enable_crs 1
|
| 130 |
+
--crs_entries 128
|
| 131 |
+
--crs_realistic 1
|
| 132 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 133 |
+
--ibtb_mech tc_tagged
|
| 134 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 135 |
+
--tc_entries 4096
|
| 136 |
+
--tc_assoc 4
|
| 137 |
+
--pref_stream_on 1
|
| 138 |
+
--stream_prefetch_n 4
|
| 139 |
+
--stream_start_dis 1
|
| 140 |
+
--stream_length 64
|
| 141 |
+
--stream_train_num 4
|
| 142 |
+
--stream_create_on_dc_miss 0
|
| 143 |
+
--stream_create_on_l1_miss 1
|
| 144 |
+
--pref_framework_on 1
|
| 145 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 146 |
+
--pref_train_on_pref_misses 0
|
| 147 |
+
--pref_oracle_train_on 0
|
| 148 |
+
--pref_throttlefb_on 1
|
| 149 |
+
--pref_acc_thresh_1 0.75
|
| 150 |
+
--pref_acc_thresh_2 0.4
|
| 151 |
+
--pref_acc_thresh_3 0.4
|
| 152 |
+
--pref_update_interval 8192
|
| 153 |
+
--pref_timely_thresh 0.01
|
| 154 |
+
--pref_polpf_thresh 0.005
|
| 155 |
+
1 1 1 1 1 1 1
|
| 156 |
+
|
| 157 |
+
--- Cut out everything below to use this file as PARAMS.in ---
|
| 158 |
+
|
| 159 |
+
Parameter status at compile time and values supplied on the command line:
|
| 160 |
+
|
| 161 |
+
SIM_MODE 0 trace_bbv_distributed
|
| 162 |
+
SIM_MODEL 0 cmp
|
| 163 |
+
FRONTEND FE_PIN_EXEC_DRIVEN memtrace
|
| 164 |
+
INST_LIMIT NULL
|
| 165 |
+
SIM_LIMIT "none" none
|
| 166 |
+
FORWARD_PROGRESS_LIMIT 100000000
|
| 167 |
+
FORWARD_PROGRESS_INTERVAL 10000
|
| 168 |
+
FAST_FORWARD 0
|
| 169 |
+
FAST_FORWARD_TRACE_INS 0
|
| 170 |
+
FAST_FORWARD_UNTIL_ADDR 0
|
| 171 |
+
MEMTRACE_ROI_BEGIN 0 60000001
|
| 172 |
+
MEMTRACE_ROI_END 0 70000000
|
| 173 |
+
FULL_WARMUP 0
|
| 174 |
+
WARMUP 0
|
| 175 |
+
HEARTBEAT_INTERVAL 1000000
|
| 176 |
+
NUM_HEARTBEATS 0
|
| 177 |
+
USE_FETCHED_COUNT FALSE 1
|
| 178 |
+
PERIODIC_DUMP FALSE
|
| 179 |
+
FILE_TAG ""
|
| 180 |
+
OUTPUT_DIR "."
|
| 181 |
+
STATUS_FILE NULL
|
| 182 |
+
BINDIR NULL
|
| 183 |
+
DUMP_PARAMS TRUE 1
|
| 184 |
+
DUMP_STATS TRUE 1
|
| 185 |
+
DUMP_TRACE FALSE 0
|
| 186 |
+
CLEAR_STATS "never"
|
| 187 |
+
STATS_TO_TRACE NULL
|
| 188 |
+
STAT_TRACE_FILE "stats.trace"
|
| 189 |
+
STAT_TRACE_INTERVAL "i:100000"
|
| 190 |
+
PIPEVIEW FALSE
|
| 191 |
+
PIPEVIEW_FILE "pipeview"
|
| 192 |
+
MEMVIEW FALSE
|
| 193 |
+
MEMVIEW_FILE "memview.out"
|
| 194 |
+
MEMVIEW_START "never"
|
| 195 |
+
INST_HASH_TABLE_SIZE 524288 const
|
| 196 |
+
STDOUT_FILE NULL
|
| 197 |
+
STDERR_FILE NULL
|
| 198 |
+
PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp"
|
| 199 |
+
PRINT_PID FALSE
|
| 200 |
+
USE_UNSURE_FREE_LISTS FALSE
|
| 201 |
+
OPTIMIZER2_MAX_NUM_SLAVES 64
|
| 202 |
+
OPTIMIZER2_PERFECT_MEMORYLESS FALSE
|
| 203 |
+
EXIT_COND 0
|
| 204 |
+
NUM_NOPS 0
|
| 205 |
+
NOPS_BB_START 0x5000000
|
| 206 |
+
IGNORE_BAR_FETCH FALSE
|
| 207 |
+
TRACE_BBV_OUTPUT NULL /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.6
|
| 208 |
+
TRACE_FOOTPRINT_OUTPUT "" /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.6
|
| 209 |
+
SEGMENT_INSTR_COUNT 0 10000000
|
| 210 |
+
ENABLE_SWPRF FALSE
|
| 211 |
+
MLC_PRESENT FALSE 1
|
| 212 |
+
MLC_SIZE (512 * 1024) 2097000
|
| 213 |
+
MLC_ASSOC 4 8
|
| 214 |
+
MLC_LINE_SIZE 64
|
| 215 |
+
MLC_CYCLES 12 16
|
| 216 |
+
PERFECT_MLC FALSE
|
| 217 |
+
MLC_READ_PORTS 1
|
| 218 |
+
MLC_WRITE_PORTS 1
|
| 219 |
+
MLC_BANKS 8
|
| 220 |
+
MLC_INTERLEAVE_FACTOR 64
|
| 221 |
+
MLC_CACHE_REPL_POLICY 0
|
| 222 |
+
MLC_WRITE_THROUGH FALSE
|
| 223 |
+
PREFETCH_UPDATE_LRU_MLC TRUE
|
| 224 |
+
FORCE_L1_MISS FALSE
|
| 225 |
+
L1_SIZE (4 * 1024 * 1024) 3145728
|
| 226 |
+
L1_ASSOC 8 16
|
| 227 |
+
L1_LINE_SIZE 64 64
|
| 228 |
+
L1_CYCLES 24 36 // just a guess
|
| 229 |
+
PERFECT_L1 FALSE
|
| 230 |
+
PRIVATE_L1 FALSE
|
| 231 |
+
L1_READ_PORTS 1
|
| 232 |
+
L1_WRITE_PORTS 1
|
| 233 |
+
L1_BANKS 8 8
|
| 234 |
+
L1_INTERLEAVE_FACTOR 64 64
|
| 235 |
+
L1_CACHE_REPL_POLICY 0
|
| 236 |
+
L1_WRITE_THROUGH FALSE
|
| 237 |
+
L1_IGNORE_WB FALSE
|
| 238 |
+
L1_USE_CORE_FREQ FALSE
|
| 239 |
+
MARK_L1_MISSES TRUE
|
| 240 |
+
PREFETCH_UPDATE_LRU_L1 TRUE
|
| 241 |
+
MEMORY_RANDOM_ADDR FALSE
|
| 242 |
+
VA_PAGE_SIZE_BYTES 4096
|
| 243 |
+
NUM_ADDR_NON_SIGN_EXTEND_BITS 48
|
| 244 |
+
ADDR_TRANSLATION 0 random
|
| 245 |
+
CONSTANT_MEMORY_LATENCY FALSE
|
| 246 |
+
MEMORY_CYCLES 100
|
| 247 |
+
STALL_MEM_REQS_ONLY FALSE
|
| 248 |
+
ICACHE_SIZE (64 * 1024) 32768
|
| 249 |
+
ICACHE_ASSOC 4 8
|
| 250 |
+
ICACHE_LINE_SIZE 64 64
|
| 251 |
+
PERFECT_ICACHE FALSE
|
| 252 |
+
ICACHE_READ_PORTS 1
|
| 253 |
+
ICACHE_WRITE_PORTS 1
|
| 254 |
+
ICACHE_BANKS 8
|
| 255 |
+
ICACHE_REPL 0
|
| 256 |
+
UOP_CACHE_ENABLE 1 1
|
| 257 |
+
UOP_CACHE_WIDTH 6 8
|
| 258 |
+
ALWAYS_LOOKUP_ICACHE 0
|
| 259 |
+
UOP_CACHE_INSERT_ONLY_ONPATH FALSE
|
| 260 |
+
UOP_CACHE_READ_PORTS 1
|
| 261 |
+
UOP_CACHE_LINES 384 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 262 |
+
UOP_CACHE_ASSOC 8 8
|
| 263 |
+
UOP_CACHE_MAX_IMM_DISP_LINE 4
|
| 264 |
+
IPRF_ON_UOP_CACHE_HIT FALSE 1
|
| 265 |
+
UOP_CACHE_REPL 0
|
| 266 |
+
PRIORITY_LINE_STICKINESS_PERCENT 50
|
| 267 |
+
PW_PRIORITY_LIST_FILEPATH "pw_priority_list.csv"
|
| 268 |
+
NUM_PRIORITY_PWS 10
|
| 269 |
+
PRIORITIZE_PWS_AFTER_FIRST_STICKY_UNTIL_BACKEND_STALL FALSE
|
| 270 |
+
NO_REPL_AFTER_QUEUE_SIZE 0
|
| 271 |
+
FDIP_UC_SIZE 0
|
| 272 |
+
FDIP_UC_ASSOC 4
|
| 273 |
+
FDIP_UC_INSERT_REPLPOL 0
|
| 274 |
+
MAP_STAGE_CONSUME_FROM_ICACHE_AND_UOC_SAME_CYCLE TRUE
|
| 275 |
+
UOP_QUEUE_LENGTH 7
|
| 276 |
+
DCACHE_SIZE (64 * 1024) 49152
|
| 277 |
+
DCACHE_ASSOC 1 12
|
| 278 |
+
DCACHE_LINE_SIZE 64 64
|
| 279 |
+
DCACHE_CYCLES 2 5
|
| 280 |
+
PERFECT_DCACHE FALSE
|
| 281 |
+
DCACHE_READ_PORTS 8 1
|
| 282 |
+
DCACHE_WRITE_PORTS 1 1
|
| 283 |
+
DCACHE_BANKS 1 8
|
| 284 |
+
DCACHE_INTERLEAVE_FACTOR 4
|
| 285 |
+
DCACHE_REPL 0
|
| 286 |
+
DCACHE_REPL_PREF_THRESH 1
|
| 287 |
+
MEM_OOO_STORES TRUE 1
|
| 288 |
+
MEM_OBEY_STORE_DEP TRUE 1
|
| 289 |
+
PREF_INSERT_LRU FALSE
|
| 290 |
+
PREF_INSERT_MIDDLE FALSE
|
| 291 |
+
PREF_INSERT_LOWQTR FALSE
|
| 292 |
+
PREF_INSERT_DYNACC FALSE
|
| 293 |
+
MEM_REQ_BUFFER_ENTRIES 32 32
|
| 294 |
+
PRIVATE_MSHR_ON TRUE
|
| 295 |
+
MEM_PRIORITY_IFETCH 0 0
|
| 296 |
+
MEM_PRIORITY_DFETCH 0 1
|
| 297 |
+
MEM_PRIORITY_DSTORE 0 2
|
| 298 |
+
MEM_PRIORITY_IPRF 9 3
|
| 299 |
+
MEM_PRIORITY_UOCPRF 9
|
| 300 |
+
MEM_PRIORITY_FDIPPRFON 8
|
| 301 |
+
MEM_PRIORITY_FDIPPRFOFF 9
|
| 302 |
+
MEM_PRIORITY_DPRF 10 4
|
| 303 |
+
MEM_PRIORITY_WB 0 5
|
| 304 |
+
MEM_PRIORITY_WB_NODIRTY 0 5
|
| 305 |
+
PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1
|
| 306 |
+
MEM_REQ_BUFFER_PREF_WATERMARK 0 4
|
| 307 |
+
MEM_REQ_BUFFER_WB_VALVE 2
|
| 308 |
+
MEM_L1_FILL_QUEUE_ENTRIES 32
|
| 309 |
+
MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE
|
| 310 |
+
MEM_MEM_QUEUE_PARTITION_ENABLE FALSE
|
| 311 |
+
MEM_BUS_OUT_QUEUE_AS_FIFO TRUE
|
| 312 |
+
OLDEST_FIRST_TO_MEM_QUEUE TRUE
|
| 313 |
+
ROUND_ROBIN_TO_MEM_QUEUE FALSE
|
| 314 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE FALSE
|
| 315 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0
|
| 316 |
+
L1_CYCLE_TIME 312500
|
| 317 |
+
MLCQ_TO_L1Q_TRANSFER_LATENCY 1
|
| 318 |
+
L1Q_TO_FSB_TRANSFER_LATENCY 1
|
| 319 |
+
PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE
|
| 320 |
+
KICKOUT_PREFETCHES FALSE
|
| 321 |
+
KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE
|
| 322 |
+
KICKOUT_OLDEST_PREFETCH FALSE
|
| 323 |
+
KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE
|
| 324 |
+
ORDER_BEYOND_BUS FALSE 1
|
| 325 |
+
ALL_FIFO_QUEUES FALSE
|
| 326 |
+
QUEUE_MLC_SIZE 0
|
| 327 |
+
QUEUE_L1_SIZE 0
|
| 328 |
+
QUEUE_BUS_OUT_SIZE 0
|
| 329 |
+
QUEUE_CORE_FILL_SIZE 0
|
| 330 |
+
ALLOW_TYPE_MATCHES FALSE
|
| 331 |
+
STREAM_PREFETCH_ON FALSE
|
| 332 |
+
DC_PREF_CACHE_ENABLE FALSE
|
| 333 |
+
DC_PREF_CACHE_CYCLE 0
|
| 334 |
+
PREF_INSERT_DCACHE_IMM TRUE
|
| 335 |
+
DC_PREF_CACHE_SIZE (64 * 1024)
|
| 336 |
+
DC_PREF_CACHE_ASSOC 4
|
| 337 |
+
DC_PREF_ONLY_L1HIT FALSE
|
| 338 |
+
PREF_CACHE_USE_RDY_CYCLE FALSE
|
| 339 |
+
IC_PREF_CACHE_ENABLE FALSE
|
| 340 |
+
IC_PREF_CACHE_SIZE (64 * 1024)
|
| 341 |
+
IC_PREF_CACHE_ASSOC 4
|
| 342 |
+
L1_PREF_CACHE_ENABLE FALSE
|
| 343 |
+
L1_PREF_CACHE_SIZE (1024 * 1024)
|
| 344 |
+
L1_PREF_CACHE_ASSOC 8
|
| 345 |
+
SET_OFF_PATH_CONFIRMED FALSE 1
|
| 346 |
+
USE_CONFIRMED_OFF FALSE
|
| 347 |
+
PREFCACHE_MOVE_OFFPATH FALSE
|
| 348 |
+
CACHE_STAT_ENABLE FALSE
|
| 349 |
+
PREF_DCACHE_HIT_FILL_L1 TRUE
|
| 350 |
+
PREF_ICACHE_HIT_FILL_L1 TRUE
|
| 351 |
+
CRITICAL_ACCESS_PLOT_ENABLE FALSE
|
| 352 |
+
CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat"
|
| 353 |
+
ROUND_ROBIN_TO_L1 FALSE
|
| 354 |
+
PREF_I_TOGETHER FALSE
|
| 355 |
+
ONE_MORE_CACHE_LINE_ENABLE FALSE
|
| 356 |
+
L1_STATIC_PARTITION_ENABLE 0
|
| 357 |
+
L1_STATIC_PARTITION NULL
|
| 358 |
+
L1_DYNAMIC_PARTITION_ENABLE FALSE
|
| 359 |
+
L1_DYNAMIC_PARTITION_POLICY 0
|
| 360 |
+
PARTITION_UMON_DSS_PREF_ENABLE FALSE
|
| 361 |
+
L1_CACHE_HIT_POSITION_COLLECT FALSE
|
| 362 |
+
L1_PART_ON FALSE
|
| 363 |
+
L1_PART_TRIGGER "c:1000000"
|
| 364 |
+
L1_PART_START "t:0"
|
| 365 |
+
L1_PART_WARMUP FALSE
|
| 366 |
+
L1_PART_SHADOW_WARMUP FALSE
|
| 367 |
+
L1_PART_METRIC 0
|
| 368 |
+
L1_PART_SEARCH 0
|
| 369 |
+
L1_PART_USE_STALLING TRUE
|
| 370 |
+
L1_PART_FILL_DELAY 0
|
| 371 |
+
L1_SHADOW_TAGS_MODULO 1
|
| 372 |
+
HIER_MSHR_ON FALSE
|
| 373 |
+
PERF_PRED_ENABLE FALSE
|
| 374 |
+
PERF_PRED_MECH PERF_PRED_CP
|
| 375 |
+
PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY
|
| 376 |
+
PERF_PRED_COUNT_ALL FALSE
|
| 377 |
+
PERF_PRED_COUNT_INST_MISSES TRUE
|
| 378 |
+
PERF_PRED_COUNT_PREFETCHES FALSE
|
| 379 |
+
PERF_PRED_COUNT_OFFPATH_REQS FALSE
|
| 380 |
+
PERF_PRED_COUNT_BW_REQS TRUE
|
| 381 |
+
PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE
|
| 382 |
+
PERF_PRED_SLACK_PERIOD_SIZE 32
|
| 383 |
+
PERF_PRED_REQS_FINISH_AT_FILL FALSE
|
| 384 |
+
PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE
|
| 385 |
+
PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE
|
| 386 |
+
DUMB_MODEL_AVG_REQ_DISTANCE 100
|
| 387 |
+
DUMB_MODEL_RANDOMIZE_DISTANCE FALSE
|
| 388 |
+
DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL
|
| 389 |
+
DUMB_MODEL_AVG_ROW_HITS 1
|
| 390 |
+
DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL
|
| 391 |
+
DUMB_MODEL_MLP 1
|
| 392 |
+
DUMB_MODEL_MLP_PER_CORE NULL
|
| 393 |
+
RAMULATOR_STANDARD "DDR4" DDR4
|
| 394 |
+
RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R
|
| 395 |
+
RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8
|
| 396 |
+
RAMULATOR_CHANNELS 1 1
|
| 397 |
+
RAMULATOR_RANKS 1 1
|
| 398 |
+
RAMULATOR_BANKGROUPS 4 4
|
| 399 |
+
RAMULATOR_BANKS 4 4
|
| 400 |
+
RAMULATOR_CHIP_WIDTH 8 8
|
| 401 |
+
BUS_WIDTH_IN_BYTES 8 8
|
| 402 |
+
RAMULATOR_ROWS 65536 65536
|
| 403 |
+
RAMULATOR_COLS 1024 1024
|
| 404 |
+
RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap
|
| 405 |
+
RAMULATOR_READQ_ENTRIES 32 32
|
| 406 |
+
RAMULATOR_WRITEQ_ENTRIES 32 32
|
| 407 |
+
RAMULATOR_REC_CMD_TRACE "off" FALSE
|
| 408 |
+
RAMULATOR_PRINT_CMD_TRACE "off" FALSE
|
| 409 |
+
RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on"
|
| 410 |
+
RAMULATOR_TCK 833333 833333
|
| 411 |
+
RAMULATOR_TCL 16 16
|
| 412 |
+
RAMULATOR_TCCD 6 6
|
| 413 |
+
RAMULATOR_TCCDS 4 4
|
| 414 |
+
RAMULATOR_TCCDL 6 6
|
| 415 |
+
RAMULATOR_TCWL 12 12
|
| 416 |
+
RAMULATOR_TBL 4 4
|
| 417 |
+
RAMULATOR_TWTR 9 9
|
| 418 |
+
RAMULATOR_TWTRS 3 3
|
| 419 |
+
RAMULATOR_TWTRL 9 9
|
| 420 |
+
RAMULATOR_TRP 16 16
|
| 421 |
+
RAMULATOR_TRPpb 16 16
|
| 422 |
+
RAMULATOR_TRPab 16 16
|
| 423 |
+
RAMULATOR_TRCD 16 16
|
| 424 |
+
RAMULATOR_TRCDR 16 16
|
| 425 |
+
RAMULATOR_TRCDW 16 16
|
| 426 |
+
RAMULATOR_TRAS 39 39
|
| 427 |
+
DRAM_TECH_IN_NM 32 32
|
| 428 |
+
DVFS_ON FALSE
|
| 429 |
+
DVFS_METRIC DVFS_METRIC_NUM_ELEMS
|
| 430 |
+
DVFS_CONFIGS NULL
|
| 431 |
+
DVFS_CONFIG_FILE NULL
|
| 432 |
+
DVFS_START "t:0"
|
| 433 |
+
DVFS_PERIOD "t:312500000000"
|
| 434 |
+
DVFS_LOG TRUE
|
| 435 |
+
DVFS_INDIVIDUAL_CORES FALSE
|
| 436 |
+
DVFS_CHIP_LEVEL FALSE
|
| 437 |
+
DVFS_STATIC NULL
|
| 438 |
+
DVFS_FORCE_CONFIG NULL
|
| 439 |
+
DVFS_REPLAY_CONFIG_TRACE NULL
|
| 440 |
+
DVFS_USE_ORACLE FALSE
|
| 441 |
+
DVFS_USE_BW_SHARING FALSE
|
| 442 |
+
DVFS_USE_DRAM_SHARING FALSE
|
| 443 |
+
DVFS_USE_STALL_TIME FALSE
|
| 444 |
+
DVFS_DRAM_SHARING_SOLVER_BIN NULL
|
| 445 |
+
DVFS_DRAM_SHARING_SOLVER_STRICT TRUE
|
| 446 |
+
DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95
|
| 447 |
+
DVFS_BW_SHARING_MAX_REQS 28.0
|
| 448 |
+
DVFS_BW_SHARING_MAX_RW_COST 0.25
|
| 449 |
+
DVFS_BW_SHARING_NO_PREF_STALL TRUE
|
| 450 |
+
DVFS_BW_SHARING_CRIT_STATS TRUE
|
| 451 |
+
DVFS_COUNT_L1_ACCESS_STALL FALSE
|
| 452 |
+
NUM_CORES 1
|
| 453 |
+
CHIP_CYCLE_TIME 312500 312500
|
| 454 |
+
CORE_0_CYCLE_TIME 312500
|
| 455 |
+
CORE_1_CYCLE_TIME 312500
|
| 456 |
+
CORE_2_CYCLE_TIME 312500
|
| 457 |
+
CORE_3_CYCLE_TIME 312500
|
| 458 |
+
CORE_4_CYCLE_TIME 312500
|
| 459 |
+
CORE_5_CYCLE_TIME 312500
|
| 460 |
+
CORE_6_CYCLE_TIME 312500
|
| 461 |
+
CORE_7_CYCLE_TIME 312500
|
| 462 |
+
CORE_8_CYCLE_TIME 312500
|
| 463 |
+
CORE_9_CYCLE_TIME 312500
|
| 464 |
+
CORE_10_CYCLE_TIME 312500
|
| 465 |
+
CORE_11_CYCLE_TIME 312500
|
| 466 |
+
CORE_12_CYCLE_TIME 312500
|
| 467 |
+
CORE_13_CYCLE_TIME 312500
|
| 468 |
+
CORE_14_CYCLE_TIME 312500
|
| 469 |
+
CORE_15_CYCLE_TIME 312500
|
| 470 |
+
CORE_16_CYCLE_TIME 312500
|
| 471 |
+
CORE_17_CYCLE_TIME 312500
|
| 472 |
+
CORE_18_CYCLE_TIME 312500
|
| 473 |
+
CORE_19_CYCLE_TIME 312500
|
| 474 |
+
CORE_20_CYCLE_TIME 312500
|
| 475 |
+
CORE_21_CYCLE_TIME 312500
|
| 476 |
+
CORE_22_CYCLE_TIME 312500
|
| 477 |
+
CORE_23_CYCLE_TIME 312500
|
| 478 |
+
CORE_24_CYCLE_TIME 312500
|
| 479 |
+
CORE_25_CYCLE_TIME 312500
|
| 480 |
+
CORE_26_CYCLE_TIME 312500
|
| 481 |
+
CORE_27_CYCLE_TIME 312500
|
| 482 |
+
CORE_28_CYCLE_TIME 312500
|
| 483 |
+
CORE_29_CYCLE_TIME 312500
|
| 484 |
+
CORE_30_CYCLE_TIME 312500
|
| 485 |
+
CORE_31_CYCLE_TIME 312500
|
| 486 |
+
CORE_32_CYCLE_TIME 312500
|
| 487 |
+
CORE_33_CYCLE_TIME 312500
|
| 488 |
+
CORE_34_CYCLE_TIME 312500
|
| 489 |
+
CORE_35_CYCLE_TIME 312500
|
| 490 |
+
CORE_36_CYCLE_TIME 312500
|
| 491 |
+
CORE_37_CYCLE_TIME 312500
|
| 492 |
+
CORE_38_CYCLE_TIME 312500
|
| 493 |
+
CORE_39_CYCLE_TIME 312500
|
| 494 |
+
CORE_40_CYCLE_TIME 312500
|
| 495 |
+
CORE_41_CYCLE_TIME 312500
|
| 496 |
+
CORE_42_CYCLE_TIME 312500
|
| 497 |
+
CORE_43_CYCLE_TIME 312500
|
| 498 |
+
CORE_44_CYCLE_TIME 312500
|
| 499 |
+
CORE_45_CYCLE_TIME 312500
|
| 500 |
+
CORE_46_CYCLE_TIME 312500
|
| 501 |
+
CORE_47_CYCLE_TIME 312500
|
| 502 |
+
CORE_48_CYCLE_TIME 312500
|
| 503 |
+
CORE_49_CYCLE_TIME 312500
|
| 504 |
+
CORE_50_CYCLE_TIME 312500
|
| 505 |
+
CORE_51_CYCLE_TIME 312500
|
| 506 |
+
CORE_52_CYCLE_TIME 312500
|
| 507 |
+
CORE_53_CYCLE_TIME 312500
|
| 508 |
+
CORE_54_CYCLE_TIME 312500
|
| 509 |
+
CORE_55_CYCLE_TIME 312500
|
| 510 |
+
CORE_56_CYCLE_TIME 312500
|
| 511 |
+
CORE_57_CYCLE_TIME 312500
|
| 512 |
+
CORE_58_CYCLE_TIME 312500
|
| 513 |
+
CORE_59_CYCLE_TIME 312500
|
| 514 |
+
CORE_60_CYCLE_TIME 312500
|
| 515 |
+
CORE_61_CYCLE_TIME 312500
|
| 516 |
+
CORE_62_CYCLE_TIME 312500
|
| 517 |
+
CORE_63_CYCLE_TIME 312500
|
| 518 |
+
TOPDOWN_FU_EXEC_FEW 0
|
| 519 |
+
ISSUE_WIDTH 4 6
|
| 520 |
+
RS_FILL_WIDTH 8 0
|
| 521 |
+
NODE_TABLE_SIZE 256 512
|
| 522 |
+
NODE_RET_WIDTH 4 8
|
| 523 |
+
NODE_RETIRE_RATE 10
|
| 524 |
+
DECODE_WIDTH 4 6
|
| 525 |
+
IDQ_SIZE 140 144
|
| 526 |
+
REG_RENAMING_SCHEME 0 1
|
| 527 |
+
REG_TABLE_INTEGER_PHYSICAL_SIZE 256 280
|
| 528 |
+
REG_TABLE_VECTOR_PHYSICAL_SIZE 256 332
|
| 529 |
+
REG_TABLE_INTEGER_VIRTUAL_SIZE 256
|
| 530 |
+
REG_TABLE_VECTOR_VIRTUAL_SIZE 256
|
| 531 |
+
REG_RENAMING_MOVE_ELIMINATE FALSE
|
| 532 |
+
NODE_ISSUE_QUEUE_DISPATCH_SCHEME 0
|
| 533 |
+
NODE_ISSUE_QUEUE_SCHEDULE_SCHEME 0
|
| 534 |
+
ISSUE_QUEUE_PARALLEL_PICK FALSE
|
| 535 |
+
RS_SIZES "256" 97 70 19
|
| 536 |
+
RS_CONNECTIONS "xF" b0100110011 b1000001100 b0011000000
|
| 537 |
+
FU_TYPES "0, 0, 0, 0" b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 538 |
+
LSQ_ENABLE TRUE
|
| 539 |
+
LOAD_QUEUE_ENTRY_NUM 128
|
| 540 |
+
STORE_QUEUE_ENTRY_NUM 72
|
| 541 |
+
DECODE_CYCLES 1 5
|
| 542 |
+
MAP_CYCLES 1 5
|
| 543 |
+
ICACHE_LATENCY 3
|
| 544 |
+
EXTRA_REDIRECT_CYCLES 0
|
| 545 |
+
EXTRA_RECOVERY_CYCLES 0
|
| 546 |
+
EXTRA_CALLSYS_CYCLES 20 const
|
| 547 |
+
DIE_ON_CALLSYS FALSE
|
| 548 |
+
DIE_ON_RET_STALL_THRESH 0
|
| 549 |
+
DIE_ON_RET_STALL_CORE 0
|
| 550 |
+
DIE_ON_MEM_BLOCK_THRESH 0
|
| 551 |
+
DIE_ON_MEM_BLOCK_CORE 0
|
| 552 |
+
ICACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 553 |
+
UOP_CACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 554 |
+
FETCH_OFF_PATH_OPS TRUE 1
|
| 555 |
+
WP_COLLECT_STATS TRUE
|
| 556 |
+
OP_INV_DELAY 1
|
| 557 |
+
OP_NOP_DELAY 1
|
| 558 |
+
OP_CF_DELAY 1
|
| 559 |
+
OP_MOV_DELAY 1
|
| 560 |
+
OP_CMOV_DELAY 1
|
| 561 |
+
OP_LDA_DELAY 1
|
| 562 |
+
OP_ILD_DELAY 1
|
| 563 |
+
OP_IST_DELAY 1
|
| 564 |
+
OP_IADD_DELAY 1
|
| 565 |
+
OP_IMUL_DELAY 3
|
| 566 |
+
OP_IDIV_DELAY -20
|
| 567 |
+
OP_ICMP_DELAY 1
|
| 568 |
+
OP_LOGIC_DELAY 1
|
| 569 |
+
OP_SHIFT_DELAY 1
|
| 570 |
+
OP_FLD_DELAY 1
|
| 571 |
+
OP_FST_DELAY 1
|
| 572 |
+
OP_FCVT_DELAY 3
|
| 573 |
+
OP_FADD_DELAY 3
|
| 574 |
+
OP_FMUL_DELAY 5
|
| 575 |
+
OP_FMA_DELAY 5
|
| 576 |
+
OP_FDIV_DELAY -20
|
| 577 |
+
OP_FCMP_DELAY 3
|
| 578 |
+
OP_FCMOV_DELAY 1
|
| 579 |
+
OP_GATHER_DELAY 12
|
| 580 |
+
OP_SCATTER_DELAY 18
|
| 581 |
+
OP_PIPELINED_FAST_DELAY 2
|
| 582 |
+
OP_PIPELINED_MEDIUM_DELAY 5
|
| 583 |
+
OP_PIPELINED_SLOW_DELAY 10
|
| 584 |
+
OP_NOTPIPELINED_MEDIUM_DELAY -5
|
| 585 |
+
OP_NOTPIPELINED_SLOW_DELAY -20
|
| 586 |
+
OP_NOTPIPELINED_VERY_SLOW_DELAY -100
|
| 587 |
+
UNIFORM_OP_DELAY 0
|
| 588 |
+
STALL_ON_WAIT_MEM TRUE
|
| 589 |
+
STORES_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 590 |
+
PREFS_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 591 |
+
OBEY_REG_DEP TRUE
|
| 592 |
+
TRACK_L1_MISS_DEPS FALSE
|
| 593 |
+
CBP_TRACE_R0 NULL /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 594 |
+
CBP_TRACE_R1 NULL
|
| 595 |
+
CBP_TRACE_R2 NULL
|
| 596 |
+
CBP_TRACE_R3 NULL
|
| 597 |
+
CBP_TRACE_R4 NULL
|
| 598 |
+
CBP_TRACE_R5 NULL
|
| 599 |
+
CBP_TRACE_R6 NULL
|
| 600 |
+
CBP_TRACE_R7 NULL
|
| 601 |
+
CBP_TRACE_R8 NULL
|
| 602 |
+
CBP_TRACE_R9 NULL
|
| 603 |
+
CBP_TRACE_R10 NULL
|
| 604 |
+
CBP_TRACE_R11 NULL
|
| 605 |
+
CBP_TRACE_R12 NULL
|
| 606 |
+
CBP_TRACE_R13 NULL
|
| 607 |
+
CBP_TRACE_R14 NULL
|
| 608 |
+
CBP_TRACE_R15 NULL
|
| 609 |
+
CBP_TRACE_R16 NULL
|
| 610 |
+
CBP_TRACE_R17 NULL
|
| 611 |
+
CBP_TRACE_R18 NULL
|
| 612 |
+
CBP_TRACE_R19 NULL
|
| 613 |
+
CBP_TRACE_R20 NULL
|
| 614 |
+
CBP_TRACE_R21 NULL
|
| 615 |
+
CBP_TRACE_R22 NULL
|
| 616 |
+
CBP_TRACE_R23 NULL
|
| 617 |
+
CBP_TRACE_R24 NULL
|
| 618 |
+
CBP_TRACE_R25 NULL
|
| 619 |
+
CBP_TRACE_R26 NULL
|
| 620 |
+
CBP_TRACE_R27 NULL
|
| 621 |
+
CBP_TRACE_R28 NULL
|
| 622 |
+
CBP_TRACE_R29 NULL
|
| 623 |
+
CBP_TRACE_R30 NULL
|
| 624 |
+
CBP_TRACE_R31 NULL
|
| 625 |
+
CBP_TRACE_R32 NULL
|
| 626 |
+
CBP_TRACE_R33 NULL
|
| 627 |
+
CBP_TRACE_R34 NULL
|
| 628 |
+
CBP_TRACE_R35 NULL
|
| 629 |
+
CBP_TRACE_R36 NULL
|
| 630 |
+
CBP_TRACE_R37 NULL
|
| 631 |
+
CBP_TRACE_R38 NULL
|
| 632 |
+
CBP_TRACE_R39 NULL
|
| 633 |
+
CBP_TRACE_R40 NULL
|
| 634 |
+
CBP_TRACE_R41 NULL
|
| 635 |
+
CBP_TRACE_R42 NULL
|
| 636 |
+
CBP_TRACE_R43 NULL
|
| 637 |
+
CBP_TRACE_R44 NULL
|
| 638 |
+
CBP_TRACE_R45 NULL
|
| 639 |
+
CBP_TRACE_R46 NULL
|
| 640 |
+
CBP_TRACE_R47 NULL
|
| 641 |
+
CBP_TRACE_R48 NULL
|
| 642 |
+
CBP_TRACE_R49 NULL
|
| 643 |
+
CBP_TRACE_R50 NULL
|
| 644 |
+
CBP_TRACE_R51 NULL
|
| 645 |
+
CBP_TRACE_R52 NULL
|
| 646 |
+
CBP_TRACE_R53 NULL
|
| 647 |
+
CBP_TRACE_R54 NULL
|
| 648 |
+
CBP_TRACE_R55 NULL
|
| 649 |
+
CBP_TRACE_R56 NULL
|
| 650 |
+
CBP_TRACE_R57 NULL
|
| 651 |
+
CBP_TRACE_R58 NULL
|
| 652 |
+
CBP_TRACE_R59 NULL
|
| 653 |
+
CBP_TRACE_R60 NULL
|
| 654 |
+
CBP_TRACE_R61 NULL
|
| 655 |
+
CBP_TRACE_R62 NULL
|
| 656 |
+
CBP_TRACE_R63 NULL
|
| 657 |
+
FE_FTQ_BLOCK_NUM 32
|
| 658 |
+
FE_FTQ_TAKEN_CFS_PER_CYCLE 2
|
| 659 |
+
FE_FTQ_FT_PER_CYCLE 1
|
| 660 |
+
DUMB_CORE_ON FALSE
|
| 661 |
+
DUMB_CORE 1
|
| 662 |
+
DCACHE_MISS_RATE 10
|
| 663 |
+
L1_MISS_RATE 10
|
| 664 |
+
TRACE_BUF_SIZE 0
|
| 665 |
+
PERFECT_CONFIDENCE FALSE
|
| 666 |
+
CONFIDENCE_ENABLE FALSE
|
| 667 |
+
CONFIDENCE_MECH 0
|
| 668 |
+
CONF_OFF_PATH_THRESHOLD 15
|
| 669 |
+
CONF_OFF_PATH_INC 5
|
| 670 |
+
CONF_BTB_MISS_BP_TAKEN FALSE
|
| 671 |
+
CONF_IPC_RATE_CONF FALSE
|
| 672 |
+
CONF_BTB_MISS_BP_TAKEN_THRESHOLD 0
|
| 673 |
+
CONF_BTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 674 |
+
CONF_IBTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 675 |
+
CONF_MISFETCH_RATE_CYCLES_THRESHOLD 1.0
|
| 676 |
+
CONF_MISPRED_RATE_CYCLES_THRESHOLD 1.0
|
| 677 |
+
CONF_BTB_MISS_SAMPLE_RATE 100000
|
| 678 |
+
CONF_IBTB_MISS_SAMPLE_RATE 100000
|
| 679 |
+
CONF_MISFETCH_SAMPLE_RATE 100000
|
| 680 |
+
CONF_MISPRED_SAMPLE_RATE 100000
|
| 681 |
+
CONF_IPC_SAMPLE_RATE 100000
|
| 682 |
+
CONF_BTB_MISS_RATE_WEIGHT 200
|
| 683 |
+
CONF_BTB_MISS_BP_TAKEN_CONF TRUE
|
| 684 |
+
CONF_IBTB_MISS_BP_TAKEN_CONF TRUE
|
| 685 |
+
CONF_BTB_MISS_RATE_CONF TRUE
|
| 686 |
+
CONF_IBTB_MISS_RATE_CONF TRUE
|
| 687 |
+
CONF_MISFETCH_RATE_CONF TRUE
|
| 688 |
+
CONF_MISPRED_RATE_CONF TRUE
|
| 689 |
+
CONF_INV_BP_CONF TRUE
|
| 690 |
+
CONF_PERFECT_BTB_MISS_CONF FALSE
|
| 691 |
+
CONF_PERFECT_IBTB_MISS_CONF FALSE
|
| 692 |
+
CONF_PERFECT_MISFETCH_CONF FALSE
|
| 693 |
+
CONF_PERFECT_MISPRED_CONF FALSE
|
| 694 |
+
CONF_LOG_DFE_TO_REC FALSE
|
| 695 |
+
CONF_LOG_PHASE_CYCLES FALSE
|
| 696 |
+
NUM_BPS 1
|
| 697 |
+
DFE0_TRIGGER_POLICY 0
|
| 698 |
+
DFE1_TRIGGER_POLICY 1
|
| 699 |
+
DFE2_TRIGGER_POLICY 1
|
| 700 |
+
DFE3_TRIGGER_POLICY 1
|
| 701 |
+
DFE4_TRIGGER_POLICY 1
|
| 702 |
+
DFE0_STOP_POLICY 0
|
| 703 |
+
DFE1_STOP_POLICY 1
|
| 704 |
+
DFE2_STOP_POLICY 1
|
| 705 |
+
DFE3_STOP_POLICY 1
|
| 706 |
+
DFE4_STOP_POLICY 1
|
| 707 |
+
LOOKAHEAD_BUF_SIZE 0
|
| 708 |
+
DEBUG_CYCLE_START 0 0
|
| 709 |
+
DEBUG_CYCLE_STOP 0 -1
|
| 710 |
+
DEBUG_TIME_START 0
|
| 711 |
+
DEBUG_TIME_STOP 0
|
| 712 |
+
DEBUG_INST_START 0 0
|
| 713 |
+
DEBUG_INST_STOP 0 -1
|
| 714 |
+
DEBUG_OP_START 0
|
| 715 |
+
DEBUG_OP_STOP 0
|
| 716 |
+
DEBUG_CACHE_LIB FALSE
|
| 717 |
+
DEBUG_HASH_LIB FALSE
|
| 718 |
+
DEBUG_LIST_LIB FALSE
|
| 719 |
+
DEBUG_PORT_LIB FALSE
|
| 720 |
+
DEBUG_BUS_LIB FALSE
|
| 721 |
+
DEBUG_OP_POOL FALSE
|
| 722 |
+
DEBUG_ORACLE FALSE
|
| 723 |
+
DEBUG_FRONTEND FALSE
|
| 724 |
+
DEBUG_ADDR_TRANS FALSE
|
| 725 |
+
DEBUG_BP FALSE
|
| 726 |
+
DEBUG_BP_DIR FALSE
|
| 727 |
+
DEBUG_BTB FALSE
|
| 728 |
+
DEBUG_CRS FALSE
|
| 729 |
+
DEBUG_MAP FALSE
|
| 730 |
+
DEBUG_MEMORY FALSE
|
| 731 |
+
DEBUG_REPLAY FALSE
|
| 732 |
+
DEBUG_FREQ FALSE
|
| 733 |
+
DEBUG_MODEL FALSE
|
| 734 |
+
DEBUG_THREAD FALSE
|
| 735 |
+
DEBUG_DECOUPLED_FE FALSE
|
| 736 |
+
DEBUG_CONF FALSE
|
| 737 |
+
DEBUG_ICACHE_STAGE FALSE
|
| 738 |
+
DEBUG_DECODE_STAGE FALSE
|
| 739 |
+
DEBUG_CPP_CACHE FALSE
|
| 740 |
+
DEBUG_UOP_CACHE FALSE
|
| 741 |
+
DEBUG_UOP_QUEUE_STAGE FALSE
|
| 742 |
+
DEBUG_IDQ_STAGE FALSE
|
| 743 |
+
DEBUG_MAP_STAGE FALSE
|
| 744 |
+
DEBUG_NODE_STAGE FALSE
|
| 745 |
+
DEBUG_EXEC_STAGE FALSE
|
| 746 |
+
DEBUG_DCACHE_STAGE FALSE
|
| 747 |
+
DEBUG_RETIRED_UOPS FALSE
|
| 748 |
+
DEBUG_EXC_INSERTS FALSE
|
| 749 |
+
DEBUG_BP_CONF FALSE
|
| 750 |
+
DEBUG_ONPATH_CONF FALSE
|
| 751 |
+
DEBUG_STREAM FALSE
|
| 752 |
+
DEBUG_STREAM_MEM FALSE
|
| 753 |
+
DEBUG_WAY FALSE
|
| 754 |
+
DEBUG_L2MARKV FALSE
|
| 755 |
+
DEBUG_L2L1PREF FALSE
|
| 756 |
+
DEBUG_PERF_PRED FALSE
|
| 757 |
+
DEBUG_POWER_UTILS FALSE
|
| 758 |
+
DEBUG_DVFS FALSE
|
| 759 |
+
DEBUG_TRACE_READ FALSE
|
| 760 |
+
DEBUG_INST_FIELDS FALSE
|
| 761 |
+
DEBUG_OP_FIELDS FALSE
|
| 762 |
+
DEBUG_PIN_EXEC_DRIVEN FALSE
|
| 763 |
+
DEBUG_CACHE_PART FALSE
|
| 764 |
+
DEBUG_OPTIMIZER2 FALSE
|
| 765 |
+
DEBUG_PREF FALSE
|
| 766 |
+
DEBUG_FDIP FALSE
|
| 767 |
+
DEBUG_EIP FALSE
|
| 768 |
+
DEBUG_DJOLT FALSE
|
| 769 |
+
DEBUG_FNLMMA FALSE
|
| 770 |
+
PERFECT_BP FALSE
|
| 771 |
+
PERFECT_BTB FALSE
|
| 772 |
+
PERFECT_IBP FALSE
|
| 773 |
+
PERFECT_CRS FALSE
|
| 774 |
+
PERFECT_CBR_BTB FALSE
|
| 775 |
+
PERFECT_NT_BTB FALSE 0 # deprecated, effectively always true.
|
| 776 |
+
CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle
|
| 777 |
+
UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 778 |
+
BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec.
|
| 779 |
+
BP_MECH TAGE64K_BP tage64k
|
| 780 |
+
BP_MECH_L0 BIMODAL_BP
|
| 781 |
+
BP_L0_LATENCY 1
|
| 782 |
+
BP_MAIN_LATENCY 3
|
| 783 |
+
BIMODAL_ENTRIES (4 * 1024)
|
| 784 |
+
HIST_LENGTH 16
|
| 785 |
+
PHT_CTR_BITS 2 const
|
| 786 |
+
BHT_ENTRIES (4 * 1024)
|
| 787 |
+
BHT_ASSOC 4
|
| 788 |
+
HYBRIDS_INDEX_LENGTH 16
|
| 789 |
+
HYBRIDG_HIST_LENGTH 16
|
| 790 |
+
HYBRIDP_HIST_LENGTH 16
|
| 791 |
+
FILTER_INDEX_LENGTH 16
|
| 792 |
+
USE_FILTER FALSE
|
| 793 |
+
INF_HYBRIDGP FALSE
|
| 794 |
+
BP_HASH_TOS FALSE
|
| 795 |
+
IBTB_HASH_TOS FALSE
|
| 796 |
+
BTB_MECH GENERIC_BTB generic
|
| 797 |
+
BTB_ENTRIES 12288 12288
|
| 798 |
+
BTB_ASSOC 4 4
|
| 799 |
+
BTB_NUM_BRSLOT 1
|
| 800 |
+
BTB_BLOCK_SIZE 64
|
| 801 |
+
BTB_OFF_PATH_WRITES TRUE 1
|
| 802 |
+
BTB_MAIN_LATENCY 3 3
|
| 803 |
+
BTB_L0_PRESENT FALSE 1
|
| 804 |
+
BTB_L0_ENTRIES 128 128
|
| 805 |
+
BTB_L0_ASSOC 4 4
|
| 806 |
+
BTB_L0_LATENCY 1 1
|
| 807 |
+
BTB_L1_PRESENT FALSE 1
|
| 808 |
+
BTB_L1_ENTRIES 6144 6144
|
| 809 |
+
BTB_L1_ASSOC 4 4
|
| 810 |
+
BTB_L1_LATENCY 2 2
|
| 811 |
+
ENABLE_CRS TRUE 1
|
| 812 |
+
CRS_ENTRIES 32 128
|
| 813 |
+
CRS_REALISTIC 0 1
|
| 814 |
+
ENABLE_IBP TRUE 1 # Enable the indirect branch predictor
|
| 815 |
+
USE_PAT_HIST TRUE
|
| 816 |
+
IBTB_MECH 1 tc_tagged
|
| 817 |
+
IBTB_HIST_LENGTH 16
|
| 818 |
+
IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb.
|
| 819 |
+
TARGETS_IN_HIST 4
|
| 820 |
+
TC_ENTRIES (4 * 1024) 4096
|
| 821 |
+
TC_ASSOC 4 4
|
| 822 |
+
NUM_CORR_BRANCHES 3
|
| 823 |
+
SEL_HIST_BP_ENTRIES 8192
|
| 824 |
+
SEL_HIST_LENGTH 16
|
| 825 |
+
SEL_HIST_DYN_CNT_TH 16
|
| 826 |
+
SEL_HIST_MISPRED_TH 4
|
| 827 |
+
ENABLE_BP_CONF FALSE
|
| 828 |
+
CONF_MECH 0
|
| 829 |
+
PERF_BP_CONF_PRED FALSE
|
| 830 |
+
BPC_BITS 16
|
| 831 |
+
BPC_MECH 1
|
| 832 |
+
BPC_CTR_RESET TRUE
|
| 833 |
+
BPC_CIT_BITS 8
|
| 834 |
+
BPC_CIT_TH 50
|
| 835 |
+
BPC_CTR_BITS 3
|
| 836 |
+
OPC_COUNT_ZEROS FALSE
|
| 837 |
+
OPC_COUNT_THRESH 10
|
| 838 |
+
INF_LOOP FALSE
|
| 839 |
+
INF_LOOP_BUCKETS 811
|
| 840 |
+
LOOP_ENTRIES (4 * 1024)
|
| 841 |
+
LOOP_ASSOC 4
|
| 842 |
+
LOOP_COUNT_MAX 127
|
| 843 |
+
LOOP_REPEAT_MAX 15
|
| 844 |
+
KNOB_PRINT_BRINFO FALSE
|
| 845 |
+
BR_MISPRED_FILE NULL
|
| 846 |
+
SPEC_LEVEL 3
|
| 847 |
+
RANDOM_DETERMINISTIC TRUE
|
| 848 |
+
TAGESCL64KB_SC TRUE
|
| 849 |
+
TAGESCL64KB_LOOP TRUE
|
| 850 |
+
TAGESCL64KB_ALT TRUE
|
| 851 |
+
CONF_PERCEPTRON_TH 0
|
| 852 |
+
CONF_PERCEPTRON_CTR_BITS 8
|
| 853 |
+
CONF_PERCEPTRON_ENTRIES 127
|
| 854 |
+
CONF_PERCEPTRON_THRESH_OVRD 0
|
| 855 |
+
CONF_HIST_LENGTH 32
|
| 856 |
+
PERCEPTRON_CONF_USE_CONF FALSE
|
| 857 |
+
PERCEPTRON_CONF_TRAIN_HIS FALSE
|
| 858 |
+
PERCEPTRON_CONF_TRAIN_CONF FALSE
|
| 859 |
+
PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE
|
| 860 |
+
PERCEPTRON_TRAIN_MISP_FACTOR 1
|
| 861 |
+
PERCEPTRON_TRAIN_CORR_FACTOR 1
|
| 862 |
+
PERCEPTRON_CONF_HIS_BOTH FALSE
|
| 863 |
+
PERCEPTRON_CONF_HIS_BOTH_LENGTH 4
|
| 864 |
+
MTAGE_REALISTIC_SC_40K FALSE
|
| 865 |
+
MTAGE_REALISTIC_SC_100K FALSE
|
| 866 |
+
H2P_TABLE_BUCKETS 16384
|
| 867 |
+
H2P_MIN_EXEC 5000
|
| 868 |
+
H2P_MIN_MISPRED 333
|
| 869 |
+
H2P_MISPRED_RATIO_PERMIL 10
|
| 870 |
+
H2P_TRACK_CBR TRUE
|
| 871 |
+
H2P_TRACK_REP TRUE
|
| 872 |
+
H2P_TRACK_CALL FALSE
|
| 873 |
+
H2P_TRACK_IBR FALSE
|
| 874 |
+
H2P_TRACK_ICALL FALSE
|
| 875 |
+
H2P_TRACK_RET FALSE
|
| 876 |
+
POWER_INTF_ON FALSE
|
| 877 |
+
POWER_INTF_ENABLE_SCALING FALSE
|
| 878 |
+
POWER_INTF_EXEC "power/power_intf.py"
|
| 879 |
+
POWER_INTF_REF_CHIP_TECH_NM 22
|
| 880 |
+
POWER_INTF_REF_CHIP_FREQ (3.2e9)
|
| 881 |
+
POWER_INTF_REF_MEMORY_FREQ (0.8e9)
|
| 882 |
+
POWER_OTHER (0.0)
|
| 883 |
+
PREF_STREAM_ON FALSE 1
|
| 884 |
+
PREF_STREAM_PER_CORE_ENABLE FALSE
|
| 885 |
+
STREAM_BUFFER_N 16
|
| 886 |
+
STREAM_PREFETCH_N 2 4
|
| 887 |
+
STREAM_START_DIS 5 1
|
| 888 |
+
STREAM_LENGTH 16 64
|
| 889 |
+
STREAM_FULL_N 1
|
| 890 |
+
STREAM_TRAIN_LENGTH 16
|
| 891 |
+
STREAM_TRAIN_NUM 1 4
|
| 892 |
+
PREF_ACC_USE_CACHE FALSE
|
| 893 |
+
STREAM_STALL_ON_QUEUE_FULL FALSE
|
| 894 |
+
PREF_SCHEDULE_NUM 4
|
| 895 |
+
TRAIN_FILTER_SIZE 32
|
| 896 |
+
PREF_REQ_Q_SIZE 64
|
| 897 |
+
STREAM_CREATE_ON_DC_MISS FALSE 0
|
| 898 |
+
STREAM_CREATE_ON_L1_MISS TRUE 1
|
| 899 |
+
STREAM_TRAIN_ON_WRONGPATH TRUE
|
| 900 |
+
STREAM_CREATE_ON_WRONGPATH TRUE
|
| 901 |
+
STREAM_PREF_INTO_DCACHE FALSE
|
| 902 |
+
REMOVE_REDUNDANT_STREAM FALSE
|
| 903 |
+
L2HIT_STREAM_SCHEDULE_NUM 4
|
| 904 |
+
PREF_REQ_QUEUE_FILTER_ON FALSE
|
| 905 |
+
HW_PREF_HIT_TRAIN_STREAM FALSE
|
| 906 |
+
L2HIT_STREAM_BUFFER_N 32
|
| 907 |
+
L2HIT_STREAM_PREFETCH_N 2
|
| 908 |
+
L2HIT_STREAM_START_DIS 2
|
| 909 |
+
L2HIT_STREAM_LENGTH 8
|
| 910 |
+
L2HIT_PREF_REQ_Q_SIZE 128
|
| 911 |
+
L2HIT_L2ACCESS_REQ_Q_SIZE 64
|
| 912 |
+
PREF_STREAM_ACCPERSTREAM FALSE
|
| 913 |
+
PREF_ACC_DISTANCE_10 128
|
| 914 |
+
PREF_FRAMEWORK_ON FALSE 1
|
| 915 |
+
PREF_TRACE_ON FALSE
|
| 916 |
+
PREF_UMLC_ON FALSE
|
| 917 |
+
PREF_UL1_ON TRUE
|
| 918 |
+
PREF_DL0REQ_QUEUE_SIZE 32
|
| 919 |
+
PREF_UMLC_REQ_QUEUE_SIZE 64
|
| 920 |
+
PREF_UL1REQ_QUEUE_SIZE 128
|
| 921 |
+
PREF_SHARED_QUEUES TRUE
|
| 922 |
+
PREF_DL0_MISS_ON TRUE
|
| 923 |
+
PREF_DL0_HIT_ON TRUE
|
| 924 |
+
PREF_DL0REQ_QUEUE_FILTER_ON TRUE
|
| 925 |
+
PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE
|
| 926 |
+
PREF_UL1REQ_QUEUE_FILTER_ON TRUE
|
| 927 |
+
PREF_DL0REQ_ADD_FILTER_ON TRUE
|
| 928 |
+
PREF_UMLC_REQ_ADD_FILTER_ON TRUE
|
| 929 |
+
PREF_UL1REQ_ADD_FILTER_ON TRUE
|
| 930 |
+
PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 931 |
+
PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 932 |
+
PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1
|
| 933 |
+
PREF_DL0SCHEDULE_NUM 4
|
| 934 |
+
PREF_UMLC_SCHEDULE_NUM 4
|
| 935 |
+
PREF_UL1SCHEDULE_NUM 4
|
| 936 |
+
PREF_L1Q_DEMAND_RESERVE 0
|
| 937 |
+
PREF_REPORT_PREF_MATCH_AS_MISS FALSE
|
| 938 |
+
PREF_REPORT_PREF_MATCH_AS_HIT TRUE
|
| 939 |
+
PREF_UPDATE_ON_WRONGPATH TRUE
|
| 940 |
+
PREF_TRAIN_ON_PREF_MISSES FALSE 0
|
| 941 |
+
PREF_ORACLE_TRAIN_ON FALSE 0
|
| 942 |
+
PREF_REQ_DROP FALSE
|
| 943 |
+
PREF_THROTTLE_ON FALSE
|
| 944 |
+
PREF_THROTTLEFB_ON FALSE 1
|
| 945 |
+
PREF_ACC_THRESH_1 0.90 0.75
|
| 946 |
+
PREF_ACC_THRESH_2 0.70 0.4
|
| 947 |
+
PREF_ACC_THRESH_3 0.60 0.4
|
| 948 |
+
PREF_ACC_THRESH_4 0.40
|
| 949 |
+
PREF_UPDATE_INTERVAL 0 8192
|
| 950 |
+
PREF_ANALYZE_LOAD FALSE
|
| 951 |
+
PREF_POL_THRESH_1 0.25
|
| 952 |
+
PREF_POL_THRESH_2 0.10
|
| 953 |
+
PREF_POLBV_ON FALSE
|
| 954 |
+
PREF_POLBV_SIZE 1024
|
| 955 |
+
PREF_TIMELY_THRESH 0.05 0.01
|
| 956 |
+
PREF_POLPF_THRESH 0.01 0.005
|
| 957 |
+
PREF_DEGFB_USEONLYACC FALSE
|
| 958 |
+
PREF_DEGFB_USEONLYPOL FALSE
|
| 959 |
+
PREF_DEGFB_USEONLYLATE FALSE
|
| 960 |
+
PREF_TIMELY_THRESH_2 0.005
|
| 961 |
+
PREF_DEGFB_STATPHASEFILE FALSE
|
| 962 |
+
PREF_MAX_DEGFB 4
|
| 963 |
+
PREF_DHAL FALSE
|
| 964 |
+
PREF_DHAL_SENTTHRESH 16
|
| 965 |
+
PREF_DHAL_USETHRESH_MAX 12
|
| 966 |
+
PREF_DHAL_USETHRESH_MIN2 8
|
| 967 |
+
PREF_DHAL_USETHRESH_MIN1 4
|
| 968 |
+
PREF_DHAL_MAXDEG 64
|
| 969 |
+
PREF_HFILTER_ON FALSE
|
| 970 |
+
PREF_HFILTER_INDEX_BITS 12
|
| 971 |
+
PREF_HFILTER_USE_PC FALSE
|
| 972 |
+
PREF_HFILTER_PRED_USELESS_THRES 2
|
| 973 |
+
PREF_HFILTER_RESET_ENABLE FALSE
|
| 974 |
+
PREF_HFILTER_RESET_INTERVAL 100000
|
| 975 |
+
EIP_ENABLE 0
|
| 976 |
+
L1I_ENTANGLED_TABLE_INDEX_BITS 9
|
| 977 |
+
L1I_ENTANGLED_TABLE_WAYS 16
|
| 978 |
+
DJOLT_ENABLE 0
|
| 979 |
+
FNLMMA_ENABLE 0
|
| 980 |
+
FDIP_ENABLE 1
|
| 981 |
+
FDIP_ALWAYS_PREFETCH FALSE
|
| 982 |
+
PERFECT_FDIP FALSE
|
| 983 |
+
IPRF_MAX_FTQ_ENTRY_CYC 2
|
| 984 |
+
FDIP_BLOOM_FILTER FALSE
|
| 985 |
+
FDIP_BLOOM_ENTRIES 4000
|
| 986 |
+
FDIP_BLOOM2_ENTRIES 1000
|
| 987 |
+
FDIP_BLOOM4_ENTRIES 1000
|
| 988 |
+
FDIP_BLOOM_SIZE 16384
|
| 989 |
+
FDIP_BLOOM_HASHES 6
|
| 990 |
+
FDIP_BLOOM_CLEAR_UNUSEFUL_RATIO 0.95
|
| 991 |
+
FDIP_BLOOM_CLEAR_CYC_PERIOD 10000
|
| 992 |
+
FDIP_UTILITY_HASH_ENABLE 0
|
| 993 |
+
FDIP_UTILITY_PREF_POLICY 0
|
| 994 |
+
FDIP_ADJUSTABLE_FTQ 0
|
| 995 |
+
FDIP_ADJUSTABLE_FTQ_CYC 100000
|
| 996 |
+
UTILITY_RATIO_THRESHOLD 0.58
|
| 997 |
+
TIMELINESS_RATIO_THRESHOLD 0.82
|
| 998 |
+
FDIP_PREF_NO_LATENCY FALSE
|
| 999 |
+
UDP_USEFUL_THRESHOLD 0
|
| 1000 |
+
UDP_WEIGHT_USEFUL 4
|
| 1001 |
+
UDP_WEIGHT_UNUSEFUL 1
|
| 1002 |
+
UDP_WEIGHT_POSITIVE_SATURATION 2147483647
|
| 1003 |
+
FDIP_GHIST_HASHING FALSE
|
| 1004 |
+
FDIP_UTILITY_ONLY_TRAIN_OFF_PATH FALSE
|
| 1005 |
+
FDIP_GHIST_BITS 8
|
| 1006 |
+
UFTQ_MIN_FTQ_BLOCK_NUM 4
|
| 1007 |
+
UFTQ_MAX_FTQ_BLOCK_NUM 64
|
| 1008 |
+
FDIP_SENIORITY_FTQ_HOLD_CYC 30000
|
| 1009 |
+
FDIP_PERFECT_PREFETCH FALSE
|
| 1010 |
+
FDIP_FREEZE_AT_MEM_BUF_LIMIT TRUE
|
| 1011 |
+
FDIP_DUAL_PATH_PREF_IC_ENABLE FALSE
|
| 1012 |
+
FDIP_DUAL_PATH_PREF_UOC_ENABLE FALSE
|
| 1013 |
+
TOP_MISPRED_BR_FILEPATH "br_resteer_coverage.csv"
|
| 1014 |
+
TOP_MISPRED_BR_RESTEER_COVERAGE 0
|
| 1015 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_ENABLE FALSE
|
| 1016 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_MISPRED_THRESHOLD 1
|
| 1017 |
+
FDIP_PRINT_CL_INFO FALSE
|
| 1018 |
+
BRANCH_MISPREDICTION_TABLE_SIZE 0
|
| 1019 |
+
UOC_PREF FALSE
|
| 1020 |
+
UOC_ORACLE_PREF FALSE
|
| 1021 |
+
UOC_ZERO_LATENCY_PREF FALSE
|
| 1022 |
+
L2L1PREF_ON FALSE
|
| 1023 |
+
L2WAY_PREF FALSE
|
| 1024 |
+
L2MARKV_PREF_ON FALSE
|
| 1025 |
+
L2NEXT_PREF_ON FALSE
|
| 1026 |
+
L2HIT_STREAM_PREF_ON FALSE
|
| 1027 |
+
L2L1_DC_HIT_TRAIN FALSE
|
| 1028 |
+
L1_HIT_DUMP_FILE_ON FALSE
|
| 1029 |
+
L1_HIT_DUMP_WO_TXT FALSE
|
| 1030 |
+
L1_HIT_DUMPFILE "l1hit_dump.out"
|
| 1031 |
+
IDEAL_L2_L1_PREFETCHER FALSE
|
| 1032 |
+
IDEAL_L2_ICACHE_PREFETCHER FALSE
|
| 1033 |
+
L1WAY_PREF_SEND_QUEUE 4
|
| 1034 |
+
L1PREF_REQ_QUEUE_SIZE 1024
|
| 1035 |
+
L1PREF_IMMEDIATE FALSE
|
| 1036 |
+
L1WAY_PREF_TIMER_DIS 1000
|
| 1037 |
+
L1MARKV_PREF_SEND_QUEUE 4
|
| 1038 |
+
L1PREF_MARKV_REQ_QUEUE_SIZE 1024
|
| 1039 |
+
MARKV_L2ACCESS_REQ_Q_SIZE 64
|
| 1040 |
+
L1MARKV_PREF_IMMEDIATE FALSE
|
| 1041 |
+
L1MARKV_PREF_TIMER_DIS 1
|
| 1042 |
+
L2L1_HIT_TRAIN TRUE
|
| 1043 |
+
L1MARKV_REQ_TH 1
|
| 1044 |
+
L2L1_IMMEDIATE_PREF_CACHE FALSE
|
| 1045 |
+
L2L1_FILL_PREF_CACHE FALSE
|
| 1046 |
+
L2L1_L2_HIT_STAT FALSE
|
| 1047 |
+
PREF_GHB_ON FALSE
|
| 1048 |
+
DEBUG_PREF_GHB FALSE
|
| 1049 |
+
PREF_GHB_BUFFER_N 1024
|
| 1050 |
+
PREF_GHB_INDEX_N 128
|
| 1051 |
+
PREF_GHB_CZONE_BITS 12
|
| 1052 |
+
PREF_GHB_DEGREE 16
|
| 1053 |
+
PREF_GHB_MAX_DEGREE 32
|
| 1054 |
+
PREF_STRIDE_ON FALSE
|
| 1055 |
+
DEBUG_PREF_STRIDE FALSE
|
| 1056 |
+
PREF_STRIDE_TABLE_N 1024
|
| 1057 |
+
PREF_STRIDE_REGION_BITS 16
|
| 1058 |
+
PREF_STRIDE_DEGREE 4
|
| 1059 |
+
PREF_STRIDE_DISTANCE 16
|
| 1060 |
+
PREF_STRIDE_STARTDISTANCE 1
|
| 1061 |
+
PREF_STRIDE_SINGLE_THRESH 6
|
| 1062 |
+
PREF_STRIDE_MULTI_THRESH 6
|
| 1063 |
+
PREF_STRIDE_SINGLE_STRIDE_MODE FALSE
|
| 1064 |
+
PREF_STRIDEPC_ON FALSE
|
| 1065 |
+
DEBUG_PREF_STRIDEPC FALSE
|
| 1066 |
+
PREF_STRIDEPC_TABLE_N 1024
|
| 1067 |
+
PREF_STRIDEPC_DEGREE 4
|
| 1068 |
+
PREF_STRIDEPC_DISTANCE 16
|
| 1069 |
+
PREF_STRIDEPC_USELOADADDR FALSE
|
| 1070 |
+
PREF_STRIDEPC_TRAINNUM 2
|
| 1071 |
+
PREF_STRIDEPC_STARTDIS 4
|
| 1072 |
+
PREF_PHASE_ON FALSE
|
| 1073 |
+
PREF_PHASE_STUDY FALSE
|
| 1074 |
+
DEBUG_PREF_PHASE FALSE
|
| 1075 |
+
PREF_PHASE_PRIME_HASH 16381
|
| 1076 |
+
PREF_PHASE_INFOSIZE 16384
|
| 1077 |
+
PREF_PHASE_LOG2REGIONSIZE 12
|
| 1078 |
+
PREF_PHASE_REGIONENTRIES 64
|
| 1079 |
+
PREF_PHASE_TRACKEDREGIONS 32
|
| 1080 |
+
PREF_PHASE_INTERVAL 100000
|
| 1081 |
+
PREF_PHASE_TABLE_SIZE 64
|
| 1082 |
+
PREF_PHASE_MAXDIFF_THRESH 64
|
| 1083 |
+
PREF_PHASE_MIN_MISSES 64
|
| 1084 |
+
PREF_PHASE_MISSPER 0.4
|
| 1085 |
+
PREF_2DC_ON FALSE
|
| 1086 |
+
DEBUG_PREF_2DC FALSE
|
| 1087 |
+
PREF_2DC_CACHE_SIZE (1 * 1024)
|
| 1088 |
+
PREF_2DC_CACHE_ASSOC 4
|
| 1089 |
+
PREF_2DC_CACHE_LINE_SIZE 1
|
| 1090 |
+
PREF_2DC_DEGREE 16
|
| 1091 |
+
PREF_2DC_ZONE_SHIFT 10
|
| 1092 |
+
PREF_2DC_TAG_SIZE 16
|
| 1093 |
+
PREF_2DC_NUM_REGIONS 64
|
| 1094 |
+
PREF_2DC_REGION_HASH 61
|
| 1095 |
+
PREF_MARKOV_ON FALSE
|
| 1096 |
+
DEBUG_PREF_MARKOV FALSE
|
| 1097 |
+
PREF_MARKOV_NUM_ENTRIES 65536
|
| 1098 |
+
PREF_MARKOV_NUM_NEXT_STATES 8
|
| 1099 |
+
PREF_MARKOV_SEND_ON_PREF_HIT TRUE
|
| 1100 |
+
PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE
|
| 1101 |
+
PREF_MARKOV_TABLE_UPDATE_POLICY 0
|
| 1102 |
+
PREF_MARKOV_SEND_THRESHOLD 0
|
sssp_facebook/fingerprint/run_6/sim.log
ADDED
|
@@ -0,0 +1,59 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
[0]: ad: 0x7ffff3d9b7b7, op: 109
|
| 2 |
+
[0]: ad: 0x7ffff3d9b7bb, op: 315
|
| 3 |
+
new bb detected: 1
|
| 4 |
+
[1]: ad: 0x7ffff3d9b7c1, op: 427
|
| 5 |
+
[1]: ad: 0x7ffff3d9b7c8, op: 427
|
| 6 |
+
[1]: ad: 0x7ffff3d9b7cc, op: 847
|
| 7 |
+
[1]: ad: 0x7ffff3d9b7cf, op: 330
|
| 8 |
+
new bb detected: 2
|
| 9 |
+
[2]: ad: 0x7ffff3d9b7b0, op: 388
|
| 10 |
+
[2]: ad: 0x7ffff3d9b7b3, op: 8
|
| 11 |
+
[2]: ad: 0x7ffff3d9b7b7, op: 109
|
| 12 |
+
[2]: ad: 0x7ffff3d9b7bb, op: 315
|
| 13 |
+
new bb detected: 3
|
| 14 |
+
Scarab gitrev: 7185dea
|
| 15 |
+
Warning: Scarab expects the trace file type to include OFFLINE_FILE_TYPE_ARCH_REGDEPS (0x20000), but got type: 0xe40
|
| 16 |
+
Scarab started at Fri Jul 17 23:07:24 2026
|
| 17 |
+
|
| 18 |
+
read from initialization: 0x7ffff3d9b7b7
|
| 19 |
+
advanceReader: ROI end reached (ordinal 70000002 > roi_end 70000000)
|
| 20 |
+
Reached end of trace (last_inst) pc=0x7ffff3d9b7b7
|
| 21 |
+
[3]: ad: 0x7ffff3d9b7b0, op: 388
|
| 22 |
+
[3]: ad: 0x7ffff3d9b7b3, op: 8
|
| 23 |
+
DUP bb detected at trace end
|
| 24 |
+
to be appened segment num 1
|
| 25 |
+
10000000
|
| 26 |
+
10000000
|
| 27 |
+
====================================
|
| 28 |
+
TRACE_INST_TAKEN_NOT_CF:0
|
| 29 |
+
TRACE_INST_TAKEN_CF_BR:0
|
| 30 |
+
TRACE_INST_TAKEN_CF_CBR:1250000
|
| 31 |
+
TRACE_INST_TAKEN_CF_REP:0
|
| 32 |
+
TRACE_INST_TAKEN_CF_CALL:0
|
| 33 |
+
TRACE_INST_TAKEN_CF_IBR:0
|
| 34 |
+
TRACE_INST_TAKEN_CF_ICALL:0
|
| 35 |
+
TRACE_INST_TAKEN_CF_ICO:0
|
| 36 |
+
TRACE_INST_TAKEN_CF_RET:0
|
| 37 |
+
TRACE_INST_TAKEN_CF_SYS:0
|
| 38 |
+
====================================
|
| 39 |
+
identity within this segment
|
| 40 |
+
2 bbs with same first pc
|
| 41 |
+
[3]: size 4, freq 1249999
|
| 42 |
+
7ffff3d9b7b0: 388, 0
|
| 43 |
+
7ffff3d9b7b3: 8, 0
|
| 44 |
+
7ffff3d9b7b7: 109, 0
|
| 45 |
+
7ffff3d9b7bb: 315, 0
|
| 46 |
+
[3]: size 2, freq 1
|
| 47 |
+
7ffff3d9b7b0: 388, 0
|
| 48 |
+
7ffff3d9b7b3: 8, 0
|
| 49 |
+
1 / 3
|
| 50 |
+
========================================================
|
| 51 |
+
Number of blocks built : 3
|
| 52 |
+
Average size : 3.33 instructions
|
| 53 |
+
Number of blocks executed : 2500001
|
| 54 |
+
Average weighted size : 4.00 instructions
|
| 55 |
+
Number of total instructions : 10000000
|
| 56 |
+
Number of fetched instruction : 10000000
|
| 57 |
+
========================================================
|
| 58 |
+
Scarab finished at Fri Jul 17 23:07:28 2026
|
| 59 |
+
|
sssp_facebook/fingerprint/run_7/PARAMS.in
ADDED
|
@@ -0,0 +1,268 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# File : PARAMS.golden_cove
|
| 2 |
+
# Date : 02/27/25
|
| 3 |
+
# Description : Golden Cove Configuration
|
| 4 |
+
# Author : Surim Oh <[email protected]>
|
| 5 |
+
#
|
| 6 |
+
# Based on documentation found here:
|
| 7 |
+
# https://en.wikipedia.org/wiki/Golden_Cove
|
| 8 |
+
# https://en.wikichip.org/wiki/intel/microarchitectures/golden_cove
|
| 9 |
+
# https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/3
|
| 10 |
+
|
| 11 |
+
## Simulation Parameters
|
| 12 |
+
--mode full
|
| 13 |
+
--model cmp
|
| 14 |
+
--sim_limit none
|
| 15 |
+
|
| 16 |
+
## Core Parameters
|
| 17 |
+
|
| 18 |
+
# Femptoseconds, 3.2GHz, used for energy estimates.
|
| 19 |
+
--chip_cycle_time 312500
|
| 20 |
+
|
| 21 |
+
|
| 22 |
+
### Fetch Stage
|
| 23 |
+
--fetch_off_path_ops 1
|
| 24 |
+
|
| 25 |
+
#### ICache
|
| 26 |
+
--icache_size 32768
|
| 27 |
+
--icache_assoc 8
|
| 28 |
+
--icache_line_size 64
|
| 29 |
+
|
| 30 |
+
### Uop Cache
|
| 31 |
+
# inclusive w/ L1i
|
| 32 |
+
--uop_cache_enable 1
|
| 33 |
+
--uop_cache_width 8
|
| 34 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 35 |
+
--uop_cache_assoc 8
|
| 36 |
+
--iprf_on_uop_cache_hit 1
|
| 37 |
+
|
| 38 |
+
### Branch Predictor
|
| 39 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 40 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 41 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 42 |
+
--bp_mech tage64k
|
| 43 |
+
|
| 44 |
+
|
| 45 |
+
#### BTB
|
| 46 |
+
|
| 47 |
+
# TODO
|
| 48 |
+
# multi-level BTB
|
| 49 |
+
# 128 entry L0 BTB
|
| 50 |
+
# 6144 entry L1 BTB
|
| 51 |
+
# 12888 entry L2 BTB
|
| 52 |
+
# ~2 entry Return Stack
|
| 53 |
+
# roughly 2x8192 for now
|
| 54 |
+
# BTB model to use.
|
| 55 |
+
--btb_mech generic
|
| 56 |
+
--btb_entries 12288
|
| 57 |
+
--btb_assoc 4
|
| 58 |
+
--btb_main_latency 3
|
| 59 |
+
--btb_l0_present 1
|
| 60 |
+
--btb_l0_entries 128
|
| 61 |
+
--btb_l0_assoc 4
|
| 62 |
+
--btb_l0_latency 1
|
| 63 |
+
--btb_l1_present 1
|
| 64 |
+
--btb_l1_entries 6144
|
| 65 |
+
--btb_l1_assoc 4
|
| 66 |
+
--btb_l1_latency 2
|
| 67 |
+
|
| 68 |
+
# Allow the BTB to be updated by off path ops.
|
| 69 |
+
--btb_off_path_writes 1
|
| 70 |
+
|
| 71 |
+
# NT branches are not inserted in BTB, but do not trigger resteer
|
| 72 |
+
# since we continue without a control flow change
|
| 73 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 74 |
+
|
| 75 |
+
#### CRS
|
| 76 |
+
|
| 77 |
+
# Enable return stack
|
| 78 |
+
--enable_crs 1
|
| 79 |
+
--crs_entries 128
|
| 80 |
+
--crs_realistic 1
|
| 81 |
+
|
| 82 |
+
### iBP
|
| 83 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 84 |
+
--ibtb_mech tc_tagged
|
| 85 |
+
# iBTB Model. tc_tagless, tc_tagged, tc_hybrid.
|
| 86 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 87 |
+
--tc_entries 4096
|
| 88 |
+
--tc_assoc 4
|
| 89 |
+
|
| 90 |
+
### Decode Stage
|
| 91 |
+
--decode_width 6
|
| 92 |
+
--decode_cycles 5
|
| 93 |
+
|
| 94 |
+
### Instruction Decode Queue
|
| 95 |
+
--idq_size 144
|
| 96 |
+
|
| 97 |
+
### Map Stage
|
| 98 |
+
--map_cycles 5
|
| 99 |
+
|
| 100 |
+
# register renaming table
|
| 101 |
+
--reg_renaming_scheme 1
|
| 102 |
+
--reg_table_integer_physical_size 280
|
| 103 |
+
--reg_table_vector_physical_size 332
|
| 104 |
+
|
| 105 |
+
### Issue Stage
|
| 106 |
+
|
| 107 |
+
# Max number of instructions to be renamed, and issued per cycle.
|
| 108 |
+
--issue_width 6
|
| 109 |
+
|
| 110 |
+
--rs_fill_width 0
|
| 111 |
+
# rs_sizes ~205 in total, and they are split into three different reservation stations (RS1, RS2, RS3) where each has 97, 70, 38 entries respectively
|
| 112 |
+
# original architecture
|
| 113 |
+
# RS1 connected to port 0,1,5,6,10
|
| 114 |
+
# RS2 connected to port 2,3,11
|
| 115 |
+
# RS3 connected to port 7,8,4,9
|
| 116 |
+
# scarab does not split ST AGU port and ST port, merge them
|
| 117 |
+
# adjusted architecture to scarab ST AGU (port 4 and 9 removed. rs_size reduced to 186 from 205)
|
| 118 |
+
# RS1 connected to port 0,1,4,5,8
|
| 119 |
+
# RS2 connected to port 2,3,9
|
| 120 |
+
# RS3 connected to port 6,7 (port 4,9 removed, entries reduced to 19 from 38)
|
| 121 |
+
--rs_sizes 97 70 19
|
| 122 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 123 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 124 |
+
|
| 125 |
+
### Exec Stage
|
| 126 |
+
|
| 127 |
+
### DCache
|
| 128 |
+
--dcache_size 49152
|
| 129 |
+
--dcache_read_ports 1
|
| 130 |
+
--dcache_write_ports 1
|
| 131 |
+
--dcache_banks 8
|
| 132 |
+
--dcache_assoc 12
|
| 133 |
+
--dcache_line_size 64
|
| 134 |
+
--dcache_cycles 5
|
| 135 |
+
|
| 136 |
+
### Reorder/Retire Stage
|
| 137 |
+
|
| 138 |
+
# Max number of instructions to be retired per cycle.
|
| 139 |
+
--node_ret_width 8
|
| 140 |
+
--node_table_size 512
|
| 141 |
+
|
| 142 |
+
# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does
|
| 143 |
+
--stores_do_not_block_window 1
|
| 144 |
+
|
| 145 |
+
# TODO: confirm what this knob does
|
| 146 |
+
--prefs_do_not_block_window 1
|
| 147 |
+
|
| 148 |
+
|
| 149 |
+
## Uncore
|
| 150 |
+
|
| 151 |
+
### Mid-level cache
|
| 152 |
+
|
| 153 |
+
# Enable use of a midlevel cache between i/d and L1
|
| 154 |
+
# client 1.25 MiB (1310720 bytes) per core, 8-way, 15 cycles
|
| 155 |
+
# server 2 MiB (2097000 bytes) per core, 8-way, 16 cycles
|
| 156 |
+
--mlc_present 1
|
| 157 |
+
--mlc_size 2097000
|
| 158 |
+
--mlc_assoc 8
|
| 159 |
+
--mlc_cycles 16
|
| 160 |
+
|
| 161 |
+
|
| 162 |
+
### LLC
|
| 163 |
+
# 3 MiB per core, 16-way
|
| 164 |
+
--l1_size 3145728
|
| 165 |
+
--l1_banks 8
|
| 166 |
+
--l1_cycles 36 // just a guess
|
| 167 |
+
--l1_assoc 16
|
| 168 |
+
--l1_line_size 64
|
| 169 |
+
--l1_interleave_factor 64
|
| 170 |
+
|
| 171 |
+
|
| 172 |
+
### prefetcher
|
| 173 |
+
# Kept same as Kaby Lake
|
| 174 |
+
--pref_framework_on 1
|
| 175 |
+
--pref_stream_on 1
|
| 176 |
+
--pref_train_on_pref_misses 0
|
| 177 |
+
--pref_oracle_train 0
|
| 178 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 179 |
+
|
| 180 |
+
--stream_length 64
|
| 181 |
+
--stream_prefetch_n 4
|
| 182 |
+
--stream_start_dis 1
|
| 183 |
+
--stream_train_num 4
|
| 184 |
+
--stream_create_on_dc_miss 0
|
| 185 |
+
--stream_create_on_l1_miss 1
|
| 186 |
+
|
| 187 |
+
--pref_throttlefb_on=1
|
| 188 |
+
--pref_acc_thresh_1=0.75
|
| 189 |
+
--pref_acc_thresh_2=0.4
|
| 190 |
+
--pref_acc_thresh_3=0.4
|
| 191 |
+
--pref_timely_thresh=0.01
|
| 192 |
+
--pref_polpf_thresh=0.005
|
| 193 |
+
--pref_update_interval=8192
|
| 194 |
+
|
| 195 |
+
--mem_req_buffer_pref_watermark 4
|
| 196 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 197 |
+
|
| 198 |
+
### Memory
|
| 199 |
+
# Kept same as Kaby Lake
|
| 200 |
+
--addr_translation random
|
| 201 |
+
|
| 202 |
+
--mem_priority_ifetch 0
|
| 203 |
+
--mem_priority_dfetch 1
|
| 204 |
+
--mem_priority_dstore 2
|
| 205 |
+
--mem_priority_iprf 3
|
| 206 |
+
--mem_priority_dprf 4
|
| 207 |
+
--mem_priority_wb 5
|
| 208 |
+
--mem_priority_wb_nodirty 5
|
| 209 |
+
|
| 210 |
+
--mem_req_buffer_entries 32
|
| 211 |
+
--bus_width_in_bytes 8
|
| 212 |
+
|
| 213 |
+
--ramulator_standard DDR4
|
| 214 |
+
--ramulator_speed DDR4_2400R
|
| 215 |
+
--ramulator_org DDR4_8Gb_x8
|
| 216 |
+
--ramulator_channels 1
|
| 217 |
+
--ramulator_ranks 1
|
| 218 |
+
--ramulator_bankgroups 4
|
| 219 |
+
--ramulator_banks 4
|
| 220 |
+
--ramulator_chip_width 8
|
| 221 |
+
--ramulator_rows 65536
|
| 222 |
+
--ramulator_cols 1024
|
| 223 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 224 |
+
--ramulator_readq_entries 32
|
| 225 |
+
--ramulator_writeq_entries 32
|
| 226 |
+
--ramulator_record_cmd_trace FALSE
|
| 227 |
+
--ramulator_print_cmd_trace FALSE
|
| 228 |
+
--ramulator_tCK 833333
|
| 229 |
+
--ramulator_tCL 16
|
| 230 |
+
--ramulator_tCCD 6
|
| 231 |
+
--ramulator_tCCDS 4
|
| 232 |
+
--ramulator_tCCDL 6
|
| 233 |
+
--ramulator_tCWL 12
|
| 234 |
+
--ramulator_tBL 4
|
| 235 |
+
--ramulator_tWTR 9
|
| 236 |
+
--ramulator_tWTRS 3
|
| 237 |
+
--ramulator_tWTRL 9
|
| 238 |
+
--ramulator_tRP 16
|
| 239 |
+
--ramulator_tRPpb 16
|
| 240 |
+
--ramulator_tRPab 16
|
| 241 |
+
--ramulator_tRCD 16
|
| 242 |
+
--ramulator_tRCDR 16
|
| 243 |
+
--ramulator_tRCDW 16
|
| 244 |
+
--ramulator_tRAS 39
|
| 245 |
+
--dram_tech_in_nm 32
|
| 246 |
+
|
| 247 |
+
## Other
|
| 248 |
+
|
| 249 |
+
|
| 250 |
+
### Debug
|
| 251 |
+
--debug_inst_start 0
|
| 252 |
+
--debug_inst_stop -1
|
| 253 |
+
--debug_cycle_start 0
|
| 254 |
+
--debug_cycle_stop -1
|
| 255 |
+
|
| 256 |
+
|
| 257 |
+
## Stats and Params
|
| 258 |
+
--dump_params 1
|
| 259 |
+
--dump_stats 1
|
| 260 |
+
--dump_trace 0
|
| 261 |
+
|
| 262 |
+
####################################
|
| 263 |
+
--set_off_path_confirmed 1
|
| 264 |
+
|
| 265 |
+
--order_beyond_bus 1
|
| 266 |
+
|
| 267 |
+
--mem_ooo_stores 1
|
| 268 |
+
--mem_obey_store_dep 1
|
sssp_facebook/fingerprint/run_7/PARAMS.out
ADDED
|
@@ -0,0 +1,1102 @@
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|
|
| 1 |
+
--mode trace_bbv_distributed
|
| 2 |
+
--model cmp
|
| 3 |
+
--frontend memtrace
|
| 4 |
+
--sim_limit none
|
| 5 |
+
--memtrace_roi_begin 70000001
|
| 6 |
+
--memtrace_roi_end 80000000
|
| 7 |
+
--use_fetched_count 1
|
| 8 |
+
--dump_params 1
|
| 9 |
+
--dump_stats 1
|
| 10 |
+
--dump_trace 0
|
| 11 |
+
--trace_bbv_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.7
|
| 12 |
+
--trace_footprint_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.7
|
| 13 |
+
--segment_instr_count 10000000
|
| 14 |
+
--mlc_present 1
|
| 15 |
+
--mlc_size 2097000
|
| 16 |
+
--mlc_assoc 8
|
| 17 |
+
--mlc_cycles 16
|
| 18 |
+
--l1_size 3145728
|
| 19 |
+
--l1_assoc 16
|
| 20 |
+
--l1_line_size 64
|
| 21 |
+
--l1_cycles 36 // just a guess
|
| 22 |
+
--l1_banks 8
|
| 23 |
+
--l1_interleave_factor 64
|
| 24 |
+
--addr_translation random
|
| 25 |
+
--icache_size 32768
|
| 26 |
+
--icache_assoc 8
|
| 27 |
+
--icache_line_size 64
|
| 28 |
+
--uop_cache_enable 1
|
| 29 |
+
--uop_cache_width 8
|
| 30 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 31 |
+
--uop_cache_assoc 8
|
| 32 |
+
--iprf_on_uop_cache_hit 1
|
| 33 |
+
--dcache_size 49152
|
| 34 |
+
--dcache_assoc 12
|
| 35 |
+
--dcache_line_size 64
|
| 36 |
+
--dcache_cycles 5
|
| 37 |
+
--dcache_read_ports 1
|
| 38 |
+
--dcache_write_ports 1
|
| 39 |
+
--dcache_banks 8
|
| 40 |
+
--mem_ooo_stores 1
|
| 41 |
+
--mem_obey_store_dep 1
|
| 42 |
+
--mem_req_buffer_entries 32
|
| 43 |
+
--mem_priority_ifetch 0
|
| 44 |
+
--mem_priority_dfetch 1
|
| 45 |
+
--mem_priority_dstore 2
|
| 46 |
+
--mem_priority_iprf 3
|
| 47 |
+
--mem_priority_dprf 4
|
| 48 |
+
--mem_priority_wb 5
|
| 49 |
+
--mem_priority_wb_nodirty 5
|
| 50 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 51 |
+
--mem_req_buffer_pref_watermark 4
|
| 52 |
+
--order_beyond_bus 1
|
| 53 |
+
--set_off_path_confirmed 1
|
| 54 |
+
--ramulator_standard DDR4
|
| 55 |
+
--ramulator_speed DDR4_2400R
|
| 56 |
+
--ramulator_org DDR4_8Gb_x8
|
| 57 |
+
--ramulator_channels 1
|
| 58 |
+
--ramulator_ranks 1
|
| 59 |
+
--ramulator_bankgroups 4
|
| 60 |
+
--ramulator_banks 4
|
| 61 |
+
--ramulator_chip_width 8
|
| 62 |
+
--bus_width_in_bytes 8
|
| 63 |
+
--ramulator_rows 65536
|
| 64 |
+
--ramulator_cols 1024
|
| 65 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 66 |
+
--ramulator_readq_entries 32
|
| 67 |
+
--ramulator_writeq_entries 32
|
| 68 |
+
--ramulator_record_cmd_trace FALSE
|
| 69 |
+
--ramulator_print_cmd_trace FALSE
|
| 70 |
+
--ramulator_tCK 833333
|
| 71 |
+
--ramulator_tCL 16
|
| 72 |
+
--ramulator_tCCD 6
|
| 73 |
+
--ramulator_tCCDS 4
|
| 74 |
+
--ramulator_tCCDL 6
|
| 75 |
+
--ramulator_tCWL 12
|
| 76 |
+
--ramulator_tBL 4
|
| 77 |
+
--ramulator_tWTR 9
|
| 78 |
+
--ramulator_tWTRS 3
|
| 79 |
+
--ramulator_tWTRL 9
|
| 80 |
+
--ramulator_tRP 16
|
| 81 |
+
--ramulator_tRPpb 16
|
| 82 |
+
--ramulator_tRPab 16
|
| 83 |
+
--ramulator_tRCD 16
|
| 84 |
+
--ramulator_tRCDR 16
|
| 85 |
+
--ramulator_tRCDW 16
|
| 86 |
+
--ramulator_tRAS 39
|
| 87 |
+
--dram_tech_in_nm 32
|
| 88 |
+
--chip_cycle_time 312500
|
| 89 |
+
--issue_width 6
|
| 90 |
+
--rs_fill_width 0
|
| 91 |
+
--node_table_size 512
|
| 92 |
+
--node_ret_width 8
|
| 93 |
+
--decode_width 6
|
| 94 |
+
--idq_size 144
|
| 95 |
+
--reg_renaming_scheme 1
|
| 96 |
+
--reg_table_integer_physical_size 280
|
| 97 |
+
--reg_table_vector_physical_size 332
|
| 98 |
+
--rs_sizes 97 70 19
|
| 99 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 100 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 101 |
+
--decode_cycles 5
|
| 102 |
+
--map_cycles 5
|
| 103 |
+
--fetch_off_path_ops 1
|
| 104 |
+
--stores_do_not_block_window 1
|
| 105 |
+
--prefs_do_not_block_window 1
|
| 106 |
+
--cbp_trace_r0 /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 107 |
+
--debug_cycle_start 0
|
| 108 |
+
--debug_cycle_stop -1
|
| 109 |
+
--debug_inst_start 0
|
| 110 |
+
--debug_inst_stop -1
|
| 111 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 112 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 113 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 114 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 115 |
+
--bp_mech tage64k
|
| 116 |
+
--btb_mech generic
|
| 117 |
+
--btb_entries 12288
|
| 118 |
+
--btb_assoc 4
|
| 119 |
+
--btb_off_path_writes 1
|
| 120 |
+
--btb_main_latency 3
|
| 121 |
+
--btb_l0_present 1
|
| 122 |
+
--btb_l0_entries 128
|
| 123 |
+
--btb_l0_assoc 4
|
| 124 |
+
--btb_l0_latency 1
|
| 125 |
+
--btb_l1_present 1
|
| 126 |
+
--btb_l1_entries 6144
|
| 127 |
+
--btb_l1_assoc 4
|
| 128 |
+
--btb_l1_latency 2
|
| 129 |
+
--enable_crs 1
|
| 130 |
+
--crs_entries 128
|
| 131 |
+
--crs_realistic 1
|
| 132 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 133 |
+
--ibtb_mech tc_tagged
|
| 134 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 135 |
+
--tc_entries 4096
|
| 136 |
+
--tc_assoc 4
|
| 137 |
+
--pref_stream_on 1
|
| 138 |
+
--stream_prefetch_n 4
|
| 139 |
+
--stream_start_dis 1
|
| 140 |
+
--stream_length 64
|
| 141 |
+
--stream_train_num 4
|
| 142 |
+
--stream_create_on_dc_miss 0
|
| 143 |
+
--stream_create_on_l1_miss 1
|
| 144 |
+
--pref_framework_on 1
|
| 145 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 146 |
+
--pref_train_on_pref_misses 0
|
| 147 |
+
--pref_oracle_train_on 0
|
| 148 |
+
--pref_throttlefb_on 1
|
| 149 |
+
--pref_acc_thresh_1 0.75
|
| 150 |
+
--pref_acc_thresh_2 0.4
|
| 151 |
+
--pref_acc_thresh_3 0.4
|
| 152 |
+
--pref_update_interval 8192
|
| 153 |
+
--pref_timely_thresh 0.01
|
| 154 |
+
--pref_polpf_thresh 0.005
|
| 155 |
+
1 1 1 1 1 1 1
|
| 156 |
+
|
| 157 |
+
--- Cut out everything below to use this file as PARAMS.in ---
|
| 158 |
+
|
| 159 |
+
Parameter status at compile time and values supplied on the command line:
|
| 160 |
+
|
| 161 |
+
SIM_MODE 0 trace_bbv_distributed
|
| 162 |
+
SIM_MODEL 0 cmp
|
| 163 |
+
FRONTEND FE_PIN_EXEC_DRIVEN memtrace
|
| 164 |
+
INST_LIMIT NULL
|
| 165 |
+
SIM_LIMIT "none" none
|
| 166 |
+
FORWARD_PROGRESS_LIMIT 100000000
|
| 167 |
+
FORWARD_PROGRESS_INTERVAL 10000
|
| 168 |
+
FAST_FORWARD 0
|
| 169 |
+
FAST_FORWARD_TRACE_INS 0
|
| 170 |
+
FAST_FORWARD_UNTIL_ADDR 0
|
| 171 |
+
MEMTRACE_ROI_BEGIN 0 70000001
|
| 172 |
+
MEMTRACE_ROI_END 0 80000000
|
| 173 |
+
FULL_WARMUP 0
|
| 174 |
+
WARMUP 0
|
| 175 |
+
HEARTBEAT_INTERVAL 1000000
|
| 176 |
+
NUM_HEARTBEATS 0
|
| 177 |
+
USE_FETCHED_COUNT FALSE 1
|
| 178 |
+
PERIODIC_DUMP FALSE
|
| 179 |
+
FILE_TAG ""
|
| 180 |
+
OUTPUT_DIR "."
|
| 181 |
+
STATUS_FILE NULL
|
| 182 |
+
BINDIR NULL
|
| 183 |
+
DUMP_PARAMS TRUE 1
|
| 184 |
+
DUMP_STATS TRUE 1
|
| 185 |
+
DUMP_TRACE FALSE 0
|
| 186 |
+
CLEAR_STATS "never"
|
| 187 |
+
STATS_TO_TRACE NULL
|
| 188 |
+
STAT_TRACE_FILE "stats.trace"
|
| 189 |
+
STAT_TRACE_INTERVAL "i:100000"
|
| 190 |
+
PIPEVIEW FALSE
|
| 191 |
+
PIPEVIEW_FILE "pipeview"
|
| 192 |
+
MEMVIEW FALSE
|
| 193 |
+
MEMVIEW_FILE "memview.out"
|
| 194 |
+
MEMVIEW_START "never"
|
| 195 |
+
INST_HASH_TABLE_SIZE 524288 const
|
| 196 |
+
STDOUT_FILE NULL
|
| 197 |
+
STDERR_FILE NULL
|
| 198 |
+
PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp"
|
| 199 |
+
PRINT_PID FALSE
|
| 200 |
+
USE_UNSURE_FREE_LISTS FALSE
|
| 201 |
+
OPTIMIZER2_MAX_NUM_SLAVES 64
|
| 202 |
+
OPTIMIZER2_PERFECT_MEMORYLESS FALSE
|
| 203 |
+
EXIT_COND 0
|
| 204 |
+
NUM_NOPS 0
|
| 205 |
+
NOPS_BB_START 0x5000000
|
| 206 |
+
IGNORE_BAR_FETCH FALSE
|
| 207 |
+
TRACE_BBV_OUTPUT NULL /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.7
|
| 208 |
+
TRACE_FOOTPRINT_OUTPUT "" /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.7
|
| 209 |
+
SEGMENT_INSTR_COUNT 0 10000000
|
| 210 |
+
ENABLE_SWPRF FALSE
|
| 211 |
+
MLC_PRESENT FALSE 1
|
| 212 |
+
MLC_SIZE (512 * 1024) 2097000
|
| 213 |
+
MLC_ASSOC 4 8
|
| 214 |
+
MLC_LINE_SIZE 64
|
| 215 |
+
MLC_CYCLES 12 16
|
| 216 |
+
PERFECT_MLC FALSE
|
| 217 |
+
MLC_READ_PORTS 1
|
| 218 |
+
MLC_WRITE_PORTS 1
|
| 219 |
+
MLC_BANKS 8
|
| 220 |
+
MLC_INTERLEAVE_FACTOR 64
|
| 221 |
+
MLC_CACHE_REPL_POLICY 0
|
| 222 |
+
MLC_WRITE_THROUGH FALSE
|
| 223 |
+
PREFETCH_UPDATE_LRU_MLC TRUE
|
| 224 |
+
FORCE_L1_MISS FALSE
|
| 225 |
+
L1_SIZE (4 * 1024 * 1024) 3145728
|
| 226 |
+
L1_ASSOC 8 16
|
| 227 |
+
L1_LINE_SIZE 64 64
|
| 228 |
+
L1_CYCLES 24 36 // just a guess
|
| 229 |
+
PERFECT_L1 FALSE
|
| 230 |
+
PRIVATE_L1 FALSE
|
| 231 |
+
L1_READ_PORTS 1
|
| 232 |
+
L1_WRITE_PORTS 1
|
| 233 |
+
L1_BANKS 8 8
|
| 234 |
+
L1_INTERLEAVE_FACTOR 64 64
|
| 235 |
+
L1_CACHE_REPL_POLICY 0
|
| 236 |
+
L1_WRITE_THROUGH FALSE
|
| 237 |
+
L1_IGNORE_WB FALSE
|
| 238 |
+
L1_USE_CORE_FREQ FALSE
|
| 239 |
+
MARK_L1_MISSES TRUE
|
| 240 |
+
PREFETCH_UPDATE_LRU_L1 TRUE
|
| 241 |
+
MEMORY_RANDOM_ADDR FALSE
|
| 242 |
+
VA_PAGE_SIZE_BYTES 4096
|
| 243 |
+
NUM_ADDR_NON_SIGN_EXTEND_BITS 48
|
| 244 |
+
ADDR_TRANSLATION 0 random
|
| 245 |
+
CONSTANT_MEMORY_LATENCY FALSE
|
| 246 |
+
MEMORY_CYCLES 100
|
| 247 |
+
STALL_MEM_REQS_ONLY FALSE
|
| 248 |
+
ICACHE_SIZE (64 * 1024) 32768
|
| 249 |
+
ICACHE_ASSOC 4 8
|
| 250 |
+
ICACHE_LINE_SIZE 64 64
|
| 251 |
+
PERFECT_ICACHE FALSE
|
| 252 |
+
ICACHE_READ_PORTS 1
|
| 253 |
+
ICACHE_WRITE_PORTS 1
|
| 254 |
+
ICACHE_BANKS 8
|
| 255 |
+
ICACHE_REPL 0
|
| 256 |
+
UOP_CACHE_ENABLE 1 1
|
| 257 |
+
UOP_CACHE_WIDTH 6 8
|
| 258 |
+
ALWAYS_LOOKUP_ICACHE 0
|
| 259 |
+
UOP_CACHE_INSERT_ONLY_ONPATH FALSE
|
| 260 |
+
UOP_CACHE_READ_PORTS 1
|
| 261 |
+
UOP_CACHE_LINES 384 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 262 |
+
UOP_CACHE_ASSOC 8 8
|
| 263 |
+
UOP_CACHE_MAX_IMM_DISP_LINE 4
|
| 264 |
+
IPRF_ON_UOP_CACHE_HIT FALSE 1
|
| 265 |
+
UOP_CACHE_REPL 0
|
| 266 |
+
PRIORITY_LINE_STICKINESS_PERCENT 50
|
| 267 |
+
PW_PRIORITY_LIST_FILEPATH "pw_priority_list.csv"
|
| 268 |
+
NUM_PRIORITY_PWS 10
|
| 269 |
+
PRIORITIZE_PWS_AFTER_FIRST_STICKY_UNTIL_BACKEND_STALL FALSE
|
| 270 |
+
NO_REPL_AFTER_QUEUE_SIZE 0
|
| 271 |
+
FDIP_UC_SIZE 0
|
| 272 |
+
FDIP_UC_ASSOC 4
|
| 273 |
+
FDIP_UC_INSERT_REPLPOL 0
|
| 274 |
+
MAP_STAGE_CONSUME_FROM_ICACHE_AND_UOC_SAME_CYCLE TRUE
|
| 275 |
+
UOP_QUEUE_LENGTH 7
|
| 276 |
+
DCACHE_SIZE (64 * 1024) 49152
|
| 277 |
+
DCACHE_ASSOC 1 12
|
| 278 |
+
DCACHE_LINE_SIZE 64 64
|
| 279 |
+
DCACHE_CYCLES 2 5
|
| 280 |
+
PERFECT_DCACHE FALSE
|
| 281 |
+
DCACHE_READ_PORTS 8 1
|
| 282 |
+
DCACHE_WRITE_PORTS 1 1
|
| 283 |
+
DCACHE_BANKS 1 8
|
| 284 |
+
DCACHE_INTERLEAVE_FACTOR 4
|
| 285 |
+
DCACHE_REPL 0
|
| 286 |
+
DCACHE_REPL_PREF_THRESH 1
|
| 287 |
+
MEM_OOO_STORES TRUE 1
|
| 288 |
+
MEM_OBEY_STORE_DEP TRUE 1
|
| 289 |
+
PREF_INSERT_LRU FALSE
|
| 290 |
+
PREF_INSERT_MIDDLE FALSE
|
| 291 |
+
PREF_INSERT_LOWQTR FALSE
|
| 292 |
+
PREF_INSERT_DYNACC FALSE
|
| 293 |
+
MEM_REQ_BUFFER_ENTRIES 32 32
|
| 294 |
+
PRIVATE_MSHR_ON TRUE
|
| 295 |
+
MEM_PRIORITY_IFETCH 0 0
|
| 296 |
+
MEM_PRIORITY_DFETCH 0 1
|
| 297 |
+
MEM_PRIORITY_DSTORE 0 2
|
| 298 |
+
MEM_PRIORITY_IPRF 9 3
|
| 299 |
+
MEM_PRIORITY_UOCPRF 9
|
| 300 |
+
MEM_PRIORITY_FDIPPRFON 8
|
| 301 |
+
MEM_PRIORITY_FDIPPRFOFF 9
|
| 302 |
+
MEM_PRIORITY_DPRF 10 4
|
| 303 |
+
MEM_PRIORITY_WB 0 5
|
| 304 |
+
MEM_PRIORITY_WB_NODIRTY 0 5
|
| 305 |
+
PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1
|
| 306 |
+
MEM_REQ_BUFFER_PREF_WATERMARK 0 4
|
| 307 |
+
MEM_REQ_BUFFER_WB_VALVE 2
|
| 308 |
+
MEM_L1_FILL_QUEUE_ENTRIES 32
|
| 309 |
+
MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE
|
| 310 |
+
MEM_MEM_QUEUE_PARTITION_ENABLE FALSE
|
| 311 |
+
MEM_BUS_OUT_QUEUE_AS_FIFO TRUE
|
| 312 |
+
OLDEST_FIRST_TO_MEM_QUEUE TRUE
|
| 313 |
+
ROUND_ROBIN_TO_MEM_QUEUE FALSE
|
| 314 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE FALSE
|
| 315 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0
|
| 316 |
+
L1_CYCLE_TIME 312500
|
| 317 |
+
MLCQ_TO_L1Q_TRANSFER_LATENCY 1
|
| 318 |
+
L1Q_TO_FSB_TRANSFER_LATENCY 1
|
| 319 |
+
PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE
|
| 320 |
+
KICKOUT_PREFETCHES FALSE
|
| 321 |
+
KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE
|
| 322 |
+
KICKOUT_OLDEST_PREFETCH FALSE
|
| 323 |
+
KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE
|
| 324 |
+
ORDER_BEYOND_BUS FALSE 1
|
| 325 |
+
ALL_FIFO_QUEUES FALSE
|
| 326 |
+
QUEUE_MLC_SIZE 0
|
| 327 |
+
QUEUE_L1_SIZE 0
|
| 328 |
+
QUEUE_BUS_OUT_SIZE 0
|
| 329 |
+
QUEUE_CORE_FILL_SIZE 0
|
| 330 |
+
ALLOW_TYPE_MATCHES FALSE
|
| 331 |
+
STREAM_PREFETCH_ON FALSE
|
| 332 |
+
DC_PREF_CACHE_ENABLE FALSE
|
| 333 |
+
DC_PREF_CACHE_CYCLE 0
|
| 334 |
+
PREF_INSERT_DCACHE_IMM TRUE
|
| 335 |
+
DC_PREF_CACHE_SIZE (64 * 1024)
|
| 336 |
+
DC_PREF_CACHE_ASSOC 4
|
| 337 |
+
DC_PREF_ONLY_L1HIT FALSE
|
| 338 |
+
PREF_CACHE_USE_RDY_CYCLE FALSE
|
| 339 |
+
IC_PREF_CACHE_ENABLE FALSE
|
| 340 |
+
IC_PREF_CACHE_SIZE (64 * 1024)
|
| 341 |
+
IC_PREF_CACHE_ASSOC 4
|
| 342 |
+
L1_PREF_CACHE_ENABLE FALSE
|
| 343 |
+
L1_PREF_CACHE_SIZE (1024 * 1024)
|
| 344 |
+
L1_PREF_CACHE_ASSOC 8
|
| 345 |
+
SET_OFF_PATH_CONFIRMED FALSE 1
|
| 346 |
+
USE_CONFIRMED_OFF FALSE
|
| 347 |
+
PREFCACHE_MOVE_OFFPATH FALSE
|
| 348 |
+
CACHE_STAT_ENABLE FALSE
|
| 349 |
+
PREF_DCACHE_HIT_FILL_L1 TRUE
|
| 350 |
+
PREF_ICACHE_HIT_FILL_L1 TRUE
|
| 351 |
+
CRITICAL_ACCESS_PLOT_ENABLE FALSE
|
| 352 |
+
CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat"
|
| 353 |
+
ROUND_ROBIN_TO_L1 FALSE
|
| 354 |
+
PREF_I_TOGETHER FALSE
|
| 355 |
+
ONE_MORE_CACHE_LINE_ENABLE FALSE
|
| 356 |
+
L1_STATIC_PARTITION_ENABLE 0
|
| 357 |
+
L1_STATIC_PARTITION NULL
|
| 358 |
+
L1_DYNAMIC_PARTITION_ENABLE FALSE
|
| 359 |
+
L1_DYNAMIC_PARTITION_POLICY 0
|
| 360 |
+
PARTITION_UMON_DSS_PREF_ENABLE FALSE
|
| 361 |
+
L1_CACHE_HIT_POSITION_COLLECT FALSE
|
| 362 |
+
L1_PART_ON FALSE
|
| 363 |
+
L1_PART_TRIGGER "c:1000000"
|
| 364 |
+
L1_PART_START "t:0"
|
| 365 |
+
L1_PART_WARMUP FALSE
|
| 366 |
+
L1_PART_SHADOW_WARMUP FALSE
|
| 367 |
+
L1_PART_METRIC 0
|
| 368 |
+
L1_PART_SEARCH 0
|
| 369 |
+
L1_PART_USE_STALLING TRUE
|
| 370 |
+
L1_PART_FILL_DELAY 0
|
| 371 |
+
L1_SHADOW_TAGS_MODULO 1
|
| 372 |
+
HIER_MSHR_ON FALSE
|
| 373 |
+
PERF_PRED_ENABLE FALSE
|
| 374 |
+
PERF_PRED_MECH PERF_PRED_CP
|
| 375 |
+
PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY
|
| 376 |
+
PERF_PRED_COUNT_ALL FALSE
|
| 377 |
+
PERF_PRED_COUNT_INST_MISSES TRUE
|
| 378 |
+
PERF_PRED_COUNT_PREFETCHES FALSE
|
| 379 |
+
PERF_PRED_COUNT_OFFPATH_REQS FALSE
|
| 380 |
+
PERF_PRED_COUNT_BW_REQS TRUE
|
| 381 |
+
PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE
|
| 382 |
+
PERF_PRED_SLACK_PERIOD_SIZE 32
|
| 383 |
+
PERF_PRED_REQS_FINISH_AT_FILL FALSE
|
| 384 |
+
PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE
|
| 385 |
+
PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE
|
| 386 |
+
DUMB_MODEL_AVG_REQ_DISTANCE 100
|
| 387 |
+
DUMB_MODEL_RANDOMIZE_DISTANCE FALSE
|
| 388 |
+
DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL
|
| 389 |
+
DUMB_MODEL_AVG_ROW_HITS 1
|
| 390 |
+
DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL
|
| 391 |
+
DUMB_MODEL_MLP 1
|
| 392 |
+
DUMB_MODEL_MLP_PER_CORE NULL
|
| 393 |
+
RAMULATOR_STANDARD "DDR4" DDR4
|
| 394 |
+
RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R
|
| 395 |
+
RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8
|
| 396 |
+
RAMULATOR_CHANNELS 1 1
|
| 397 |
+
RAMULATOR_RANKS 1 1
|
| 398 |
+
RAMULATOR_BANKGROUPS 4 4
|
| 399 |
+
RAMULATOR_BANKS 4 4
|
| 400 |
+
RAMULATOR_CHIP_WIDTH 8 8
|
| 401 |
+
BUS_WIDTH_IN_BYTES 8 8
|
| 402 |
+
RAMULATOR_ROWS 65536 65536
|
| 403 |
+
RAMULATOR_COLS 1024 1024
|
| 404 |
+
RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap
|
| 405 |
+
RAMULATOR_READQ_ENTRIES 32 32
|
| 406 |
+
RAMULATOR_WRITEQ_ENTRIES 32 32
|
| 407 |
+
RAMULATOR_REC_CMD_TRACE "off" FALSE
|
| 408 |
+
RAMULATOR_PRINT_CMD_TRACE "off" FALSE
|
| 409 |
+
RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on"
|
| 410 |
+
RAMULATOR_TCK 833333 833333
|
| 411 |
+
RAMULATOR_TCL 16 16
|
| 412 |
+
RAMULATOR_TCCD 6 6
|
| 413 |
+
RAMULATOR_TCCDS 4 4
|
| 414 |
+
RAMULATOR_TCCDL 6 6
|
| 415 |
+
RAMULATOR_TCWL 12 12
|
| 416 |
+
RAMULATOR_TBL 4 4
|
| 417 |
+
RAMULATOR_TWTR 9 9
|
| 418 |
+
RAMULATOR_TWTRS 3 3
|
| 419 |
+
RAMULATOR_TWTRL 9 9
|
| 420 |
+
RAMULATOR_TRP 16 16
|
| 421 |
+
RAMULATOR_TRPpb 16 16
|
| 422 |
+
RAMULATOR_TRPab 16 16
|
| 423 |
+
RAMULATOR_TRCD 16 16
|
| 424 |
+
RAMULATOR_TRCDR 16 16
|
| 425 |
+
RAMULATOR_TRCDW 16 16
|
| 426 |
+
RAMULATOR_TRAS 39 39
|
| 427 |
+
DRAM_TECH_IN_NM 32 32
|
| 428 |
+
DVFS_ON FALSE
|
| 429 |
+
DVFS_METRIC DVFS_METRIC_NUM_ELEMS
|
| 430 |
+
DVFS_CONFIGS NULL
|
| 431 |
+
DVFS_CONFIG_FILE NULL
|
| 432 |
+
DVFS_START "t:0"
|
| 433 |
+
DVFS_PERIOD "t:312500000000"
|
| 434 |
+
DVFS_LOG TRUE
|
| 435 |
+
DVFS_INDIVIDUAL_CORES FALSE
|
| 436 |
+
DVFS_CHIP_LEVEL FALSE
|
| 437 |
+
DVFS_STATIC NULL
|
| 438 |
+
DVFS_FORCE_CONFIG NULL
|
| 439 |
+
DVFS_REPLAY_CONFIG_TRACE NULL
|
| 440 |
+
DVFS_USE_ORACLE FALSE
|
| 441 |
+
DVFS_USE_BW_SHARING FALSE
|
| 442 |
+
DVFS_USE_DRAM_SHARING FALSE
|
| 443 |
+
DVFS_USE_STALL_TIME FALSE
|
| 444 |
+
DVFS_DRAM_SHARING_SOLVER_BIN NULL
|
| 445 |
+
DVFS_DRAM_SHARING_SOLVER_STRICT TRUE
|
| 446 |
+
DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95
|
| 447 |
+
DVFS_BW_SHARING_MAX_REQS 28.0
|
| 448 |
+
DVFS_BW_SHARING_MAX_RW_COST 0.25
|
| 449 |
+
DVFS_BW_SHARING_NO_PREF_STALL TRUE
|
| 450 |
+
DVFS_BW_SHARING_CRIT_STATS TRUE
|
| 451 |
+
DVFS_COUNT_L1_ACCESS_STALL FALSE
|
| 452 |
+
NUM_CORES 1
|
| 453 |
+
CHIP_CYCLE_TIME 312500 312500
|
| 454 |
+
CORE_0_CYCLE_TIME 312500
|
| 455 |
+
CORE_1_CYCLE_TIME 312500
|
| 456 |
+
CORE_2_CYCLE_TIME 312500
|
| 457 |
+
CORE_3_CYCLE_TIME 312500
|
| 458 |
+
CORE_4_CYCLE_TIME 312500
|
| 459 |
+
CORE_5_CYCLE_TIME 312500
|
| 460 |
+
CORE_6_CYCLE_TIME 312500
|
| 461 |
+
CORE_7_CYCLE_TIME 312500
|
| 462 |
+
CORE_8_CYCLE_TIME 312500
|
| 463 |
+
CORE_9_CYCLE_TIME 312500
|
| 464 |
+
CORE_10_CYCLE_TIME 312500
|
| 465 |
+
CORE_11_CYCLE_TIME 312500
|
| 466 |
+
CORE_12_CYCLE_TIME 312500
|
| 467 |
+
CORE_13_CYCLE_TIME 312500
|
| 468 |
+
CORE_14_CYCLE_TIME 312500
|
| 469 |
+
CORE_15_CYCLE_TIME 312500
|
| 470 |
+
CORE_16_CYCLE_TIME 312500
|
| 471 |
+
CORE_17_CYCLE_TIME 312500
|
| 472 |
+
CORE_18_CYCLE_TIME 312500
|
| 473 |
+
CORE_19_CYCLE_TIME 312500
|
| 474 |
+
CORE_20_CYCLE_TIME 312500
|
| 475 |
+
CORE_21_CYCLE_TIME 312500
|
| 476 |
+
CORE_22_CYCLE_TIME 312500
|
| 477 |
+
CORE_23_CYCLE_TIME 312500
|
| 478 |
+
CORE_24_CYCLE_TIME 312500
|
| 479 |
+
CORE_25_CYCLE_TIME 312500
|
| 480 |
+
CORE_26_CYCLE_TIME 312500
|
| 481 |
+
CORE_27_CYCLE_TIME 312500
|
| 482 |
+
CORE_28_CYCLE_TIME 312500
|
| 483 |
+
CORE_29_CYCLE_TIME 312500
|
| 484 |
+
CORE_30_CYCLE_TIME 312500
|
| 485 |
+
CORE_31_CYCLE_TIME 312500
|
| 486 |
+
CORE_32_CYCLE_TIME 312500
|
| 487 |
+
CORE_33_CYCLE_TIME 312500
|
| 488 |
+
CORE_34_CYCLE_TIME 312500
|
| 489 |
+
CORE_35_CYCLE_TIME 312500
|
| 490 |
+
CORE_36_CYCLE_TIME 312500
|
| 491 |
+
CORE_37_CYCLE_TIME 312500
|
| 492 |
+
CORE_38_CYCLE_TIME 312500
|
| 493 |
+
CORE_39_CYCLE_TIME 312500
|
| 494 |
+
CORE_40_CYCLE_TIME 312500
|
| 495 |
+
CORE_41_CYCLE_TIME 312500
|
| 496 |
+
CORE_42_CYCLE_TIME 312500
|
| 497 |
+
CORE_43_CYCLE_TIME 312500
|
| 498 |
+
CORE_44_CYCLE_TIME 312500
|
| 499 |
+
CORE_45_CYCLE_TIME 312500
|
| 500 |
+
CORE_46_CYCLE_TIME 312500
|
| 501 |
+
CORE_47_CYCLE_TIME 312500
|
| 502 |
+
CORE_48_CYCLE_TIME 312500
|
| 503 |
+
CORE_49_CYCLE_TIME 312500
|
| 504 |
+
CORE_50_CYCLE_TIME 312500
|
| 505 |
+
CORE_51_CYCLE_TIME 312500
|
| 506 |
+
CORE_52_CYCLE_TIME 312500
|
| 507 |
+
CORE_53_CYCLE_TIME 312500
|
| 508 |
+
CORE_54_CYCLE_TIME 312500
|
| 509 |
+
CORE_55_CYCLE_TIME 312500
|
| 510 |
+
CORE_56_CYCLE_TIME 312500
|
| 511 |
+
CORE_57_CYCLE_TIME 312500
|
| 512 |
+
CORE_58_CYCLE_TIME 312500
|
| 513 |
+
CORE_59_CYCLE_TIME 312500
|
| 514 |
+
CORE_60_CYCLE_TIME 312500
|
| 515 |
+
CORE_61_CYCLE_TIME 312500
|
| 516 |
+
CORE_62_CYCLE_TIME 312500
|
| 517 |
+
CORE_63_CYCLE_TIME 312500
|
| 518 |
+
TOPDOWN_FU_EXEC_FEW 0
|
| 519 |
+
ISSUE_WIDTH 4 6
|
| 520 |
+
RS_FILL_WIDTH 8 0
|
| 521 |
+
NODE_TABLE_SIZE 256 512
|
| 522 |
+
NODE_RET_WIDTH 4 8
|
| 523 |
+
NODE_RETIRE_RATE 10
|
| 524 |
+
DECODE_WIDTH 4 6
|
| 525 |
+
IDQ_SIZE 140 144
|
| 526 |
+
REG_RENAMING_SCHEME 0 1
|
| 527 |
+
REG_TABLE_INTEGER_PHYSICAL_SIZE 256 280
|
| 528 |
+
REG_TABLE_VECTOR_PHYSICAL_SIZE 256 332
|
| 529 |
+
REG_TABLE_INTEGER_VIRTUAL_SIZE 256
|
| 530 |
+
REG_TABLE_VECTOR_VIRTUAL_SIZE 256
|
| 531 |
+
REG_RENAMING_MOVE_ELIMINATE FALSE
|
| 532 |
+
NODE_ISSUE_QUEUE_DISPATCH_SCHEME 0
|
| 533 |
+
NODE_ISSUE_QUEUE_SCHEDULE_SCHEME 0
|
| 534 |
+
ISSUE_QUEUE_PARALLEL_PICK FALSE
|
| 535 |
+
RS_SIZES "256" 97 70 19
|
| 536 |
+
RS_CONNECTIONS "xF" b0100110011 b1000001100 b0011000000
|
| 537 |
+
FU_TYPES "0, 0, 0, 0" b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 538 |
+
LSQ_ENABLE TRUE
|
| 539 |
+
LOAD_QUEUE_ENTRY_NUM 128
|
| 540 |
+
STORE_QUEUE_ENTRY_NUM 72
|
| 541 |
+
DECODE_CYCLES 1 5
|
| 542 |
+
MAP_CYCLES 1 5
|
| 543 |
+
ICACHE_LATENCY 3
|
| 544 |
+
EXTRA_REDIRECT_CYCLES 0
|
| 545 |
+
EXTRA_RECOVERY_CYCLES 0
|
| 546 |
+
EXTRA_CALLSYS_CYCLES 20 const
|
| 547 |
+
DIE_ON_CALLSYS FALSE
|
| 548 |
+
DIE_ON_RET_STALL_THRESH 0
|
| 549 |
+
DIE_ON_RET_STALL_CORE 0
|
| 550 |
+
DIE_ON_MEM_BLOCK_THRESH 0
|
| 551 |
+
DIE_ON_MEM_BLOCK_CORE 0
|
| 552 |
+
ICACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 553 |
+
UOP_CACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 554 |
+
FETCH_OFF_PATH_OPS TRUE 1
|
| 555 |
+
WP_COLLECT_STATS TRUE
|
| 556 |
+
OP_INV_DELAY 1
|
| 557 |
+
OP_NOP_DELAY 1
|
| 558 |
+
OP_CF_DELAY 1
|
| 559 |
+
OP_MOV_DELAY 1
|
| 560 |
+
OP_CMOV_DELAY 1
|
| 561 |
+
OP_LDA_DELAY 1
|
| 562 |
+
OP_ILD_DELAY 1
|
| 563 |
+
OP_IST_DELAY 1
|
| 564 |
+
OP_IADD_DELAY 1
|
| 565 |
+
OP_IMUL_DELAY 3
|
| 566 |
+
OP_IDIV_DELAY -20
|
| 567 |
+
OP_ICMP_DELAY 1
|
| 568 |
+
OP_LOGIC_DELAY 1
|
| 569 |
+
OP_SHIFT_DELAY 1
|
| 570 |
+
OP_FLD_DELAY 1
|
| 571 |
+
OP_FST_DELAY 1
|
| 572 |
+
OP_FCVT_DELAY 3
|
| 573 |
+
OP_FADD_DELAY 3
|
| 574 |
+
OP_FMUL_DELAY 5
|
| 575 |
+
OP_FMA_DELAY 5
|
| 576 |
+
OP_FDIV_DELAY -20
|
| 577 |
+
OP_FCMP_DELAY 3
|
| 578 |
+
OP_FCMOV_DELAY 1
|
| 579 |
+
OP_GATHER_DELAY 12
|
| 580 |
+
OP_SCATTER_DELAY 18
|
| 581 |
+
OP_PIPELINED_FAST_DELAY 2
|
| 582 |
+
OP_PIPELINED_MEDIUM_DELAY 5
|
| 583 |
+
OP_PIPELINED_SLOW_DELAY 10
|
| 584 |
+
OP_NOTPIPELINED_MEDIUM_DELAY -5
|
| 585 |
+
OP_NOTPIPELINED_SLOW_DELAY -20
|
| 586 |
+
OP_NOTPIPELINED_VERY_SLOW_DELAY -100
|
| 587 |
+
UNIFORM_OP_DELAY 0
|
| 588 |
+
STALL_ON_WAIT_MEM TRUE
|
| 589 |
+
STORES_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 590 |
+
PREFS_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 591 |
+
OBEY_REG_DEP TRUE
|
| 592 |
+
TRACK_L1_MISS_DEPS FALSE
|
| 593 |
+
CBP_TRACE_R0 NULL /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 594 |
+
CBP_TRACE_R1 NULL
|
| 595 |
+
CBP_TRACE_R2 NULL
|
| 596 |
+
CBP_TRACE_R3 NULL
|
| 597 |
+
CBP_TRACE_R4 NULL
|
| 598 |
+
CBP_TRACE_R5 NULL
|
| 599 |
+
CBP_TRACE_R6 NULL
|
| 600 |
+
CBP_TRACE_R7 NULL
|
| 601 |
+
CBP_TRACE_R8 NULL
|
| 602 |
+
CBP_TRACE_R9 NULL
|
| 603 |
+
CBP_TRACE_R10 NULL
|
| 604 |
+
CBP_TRACE_R11 NULL
|
| 605 |
+
CBP_TRACE_R12 NULL
|
| 606 |
+
CBP_TRACE_R13 NULL
|
| 607 |
+
CBP_TRACE_R14 NULL
|
| 608 |
+
CBP_TRACE_R15 NULL
|
| 609 |
+
CBP_TRACE_R16 NULL
|
| 610 |
+
CBP_TRACE_R17 NULL
|
| 611 |
+
CBP_TRACE_R18 NULL
|
| 612 |
+
CBP_TRACE_R19 NULL
|
| 613 |
+
CBP_TRACE_R20 NULL
|
| 614 |
+
CBP_TRACE_R21 NULL
|
| 615 |
+
CBP_TRACE_R22 NULL
|
| 616 |
+
CBP_TRACE_R23 NULL
|
| 617 |
+
CBP_TRACE_R24 NULL
|
| 618 |
+
CBP_TRACE_R25 NULL
|
| 619 |
+
CBP_TRACE_R26 NULL
|
| 620 |
+
CBP_TRACE_R27 NULL
|
| 621 |
+
CBP_TRACE_R28 NULL
|
| 622 |
+
CBP_TRACE_R29 NULL
|
| 623 |
+
CBP_TRACE_R30 NULL
|
| 624 |
+
CBP_TRACE_R31 NULL
|
| 625 |
+
CBP_TRACE_R32 NULL
|
| 626 |
+
CBP_TRACE_R33 NULL
|
| 627 |
+
CBP_TRACE_R34 NULL
|
| 628 |
+
CBP_TRACE_R35 NULL
|
| 629 |
+
CBP_TRACE_R36 NULL
|
| 630 |
+
CBP_TRACE_R37 NULL
|
| 631 |
+
CBP_TRACE_R38 NULL
|
| 632 |
+
CBP_TRACE_R39 NULL
|
| 633 |
+
CBP_TRACE_R40 NULL
|
| 634 |
+
CBP_TRACE_R41 NULL
|
| 635 |
+
CBP_TRACE_R42 NULL
|
| 636 |
+
CBP_TRACE_R43 NULL
|
| 637 |
+
CBP_TRACE_R44 NULL
|
| 638 |
+
CBP_TRACE_R45 NULL
|
| 639 |
+
CBP_TRACE_R46 NULL
|
| 640 |
+
CBP_TRACE_R47 NULL
|
| 641 |
+
CBP_TRACE_R48 NULL
|
| 642 |
+
CBP_TRACE_R49 NULL
|
| 643 |
+
CBP_TRACE_R50 NULL
|
| 644 |
+
CBP_TRACE_R51 NULL
|
| 645 |
+
CBP_TRACE_R52 NULL
|
| 646 |
+
CBP_TRACE_R53 NULL
|
| 647 |
+
CBP_TRACE_R54 NULL
|
| 648 |
+
CBP_TRACE_R55 NULL
|
| 649 |
+
CBP_TRACE_R56 NULL
|
| 650 |
+
CBP_TRACE_R57 NULL
|
| 651 |
+
CBP_TRACE_R58 NULL
|
| 652 |
+
CBP_TRACE_R59 NULL
|
| 653 |
+
CBP_TRACE_R60 NULL
|
| 654 |
+
CBP_TRACE_R61 NULL
|
| 655 |
+
CBP_TRACE_R62 NULL
|
| 656 |
+
CBP_TRACE_R63 NULL
|
| 657 |
+
FE_FTQ_BLOCK_NUM 32
|
| 658 |
+
FE_FTQ_TAKEN_CFS_PER_CYCLE 2
|
| 659 |
+
FE_FTQ_FT_PER_CYCLE 1
|
| 660 |
+
DUMB_CORE_ON FALSE
|
| 661 |
+
DUMB_CORE 1
|
| 662 |
+
DCACHE_MISS_RATE 10
|
| 663 |
+
L1_MISS_RATE 10
|
| 664 |
+
TRACE_BUF_SIZE 0
|
| 665 |
+
PERFECT_CONFIDENCE FALSE
|
| 666 |
+
CONFIDENCE_ENABLE FALSE
|
| 667 |
+
CONFIDENCE_MECH 0
|
| 668 |
+
CONF_OFF_PATH_THRESHOLD 15
|
| 669 |
+
CONF_OFF_PATH_INC 5
|
| 670 |
+
CONF_BTB_MISS_BP_TAKEN FALSE
|
| 671 |
+
CONF_IPC_RATE_CONF FALSE
|
| 672 |
+
CONF_BTB_MISS_BP_TAKEN_THRESHOLD 0
|
| 673 |
+
CONF_BTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 674 |
+
CONF_IBTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 675 |
+
CONF_MISFETCH_RATE_CYCLES_THRESHOLD 1.0
|
| 676 |
+
CONF_MISPRED_RATE_CYCLES_THRESHOLD 1.0
|
| 677 |
+
CONF_BTB_MISS_SAMPLE_RATE 100000
|
| 678 |
+
CONF_IBTB_MISS_SAMPLE_RATE 100000
|
| 679 |
+
CONF_MISFETCH_SAMPLE_RATE 100000
|
| 680 |
+
CONF_MISPRED_SAMPLE_RATE 100000
|
| 681 |
+
CONF_IPC_SAMPLE_RATE 100000
|
| 682 |
+
CONF_BTB_MISS_RATE_WEIGHT 200
|
| 683 |
+
CONF_BTB_MISS_BP_TAKEN_CONF TRUE
|
| 684 |
+
CONF_IBTB_MISS_BP_TAKEN_CONF TRUE
|
| 685 |
+
CONF_BTB_MISS_RATE_CONF TRUE
|
| 686 |
+
CONF_IBTB_MISS_RATE_CONF TRUE
|
| 687 |
+
CONF_MISFETCH_RATE_CONF TRUE
|
| 688 |
+
CONF_MISPRED_RATE_CONF TRUE
|
| 689 |
+
CONF_INV_BP_CONF TRUE
|
| 690 |
+
CONF_PERFECT_BTB_MISS_CONF FALSE
|
| 691 |
+
CONF_PERFECT_IBTB_MISS_CONF FALSE
|
| 692 |
+
CONF_PERFECT_MISFETCH_CONF FALSE
|
| 693 |
+
CONF_PERFECT_MISPRED_CONF FALSE
|
| 694 |
+
CONF_LOG_DFE_TO_REC FALSE
|
| 695 |
+
CONF_LOG_PHASE_CYCLES FALSE
|
| 696 |
+
NUM_BPS 1
|
| 697 |
+
DFE0_TRIGGER_POLICY 0
|
| 698 |
+
DFE1_TRIGGER_POLICY 1
|
| 699 |
+
DFE2_TRIGGER_POLICY 1
|
| 700 |
+
DFE3_TRIGGER_POLICY 1
|
| 701 |
+
DFE4_TRIGGER_POLICY 1
|
| 702 |
+
DFE0_STOP_POLICY 0
|
| 703 |
+
DFE1_STOP_POLICY 1
|
| 704 |
+
DFE2_STOP_POLICY 1
|
| 705 |
+
DFE3_STOP_POLICY 1
|
| 706 |
+
DFE4_STOP_POLICY 1
|
| 707 |
+
LOOKAHEAD_BUF_SIZE 0
|
| 708 |
+
DEBUG_CYCLE_START 0 0
|
| 709 |
+
DEBUG_CYCLE_STOP 0 -1
|
| 710 |
+
DEBUG_TIME_START 0
|
| 711 |
+
DEBUG_TIME_STOP 0
|
| 712 |
+
DEBUG_INST_START 0 0
|
| 713 |
+
DEBUG_INST_STOP 0 -1
|
| 714 |
+
DEBUG_OP_START 0
|
| 715 |
+
DEBUG_OP_STOP 0
|
| 716 |
+
DEBUG_CACHE_LIB FALSE
|
| 717 |
+
DEBUG_HASH_LIB FALSE
|
| 718 |
+
DEBUG_LIST_LIB FALSE
|
| 719 |
+
DEBUG_PORT_LIB FALSE
|
| 720 |
+
DEBUG_BUS_LIB FALSE
|
| 721 |
+
DEBUG_OP_POOL FALSE
|
| 722 |
+
DEBUG_ORACLE FALSE
|
| 723 |
+
DEBUG_FRONTEND FALSE
|
| 724 |
+
DEBUG_ADDR_TRANS FALSE
|
| 725 |
+
DEBUG_BP FALSE
|
| 726 |
+
DEBUG_BP_DIR FALSE
|
| 727 |
+
DEBUG_BTB FALSE
|
| 728 |
+
DEBUG_CRS FALSE
|
| 729 |
+
DEBUG_MAP FALSE
|
| 730 |
+
DEBUG_MEMORY FALSE
|
| 731 |
+
DEBUG_REPLAY FALSE
|
| 732 |
+
DEBUG_FREQ FALSE
|
| 733 |
+
DEBUG_MODEL FALSE
|
| 734 |
+
DEBUG_THREAD FALSE
|
| 735 |
+
DEBUG_DECOUPLED_FE FALSE
|
| 736 |
+
DEBUG_CONF FALSE
|
| 737 |
+
DEBUG_ICACHE_STAGE FALSE
|
| 738 |
+
DEBUG_DECODE_STAGE FALSE
|
| 739 |
+
DEBUG_CPP_CACHE FALSE
|
| 740 |
+
DEBUG_UOP_CACHE FALSE
|
| 741 |
+
DEBUG_UOP_QUEUE_STAGE FALSE
|
| 742 |
+
DEBUG_IDQ_STAGE FALSE
|
| 743 |
+
DEBUG_MAP_STAGE FALSE
|
| 744 |
+
DEBUG_NODE_STAGE FALSE
|
| 745 |
+
DEBUG_EXEC_STAGE FALSE
|
| 746 |
+
DEBUG_DCACHE_STAGE FALSE
|
| 747 |
+
DEBUG_RETIRED_UOPS FALSE
|
| 748 |
+
DEBUG_EXC_INSERTS FALSE
|
| 749 |
+
DEBUG_BP_CONF FALSE
|
| 750 |
+
DEBUG_ONPATH_CONF FALSE
|
| 751 |
+
DEBUG_STREAM FALSE
|
| 752 |
+
DEBUG_STREAM_MEM FALSE
|
| 753 |
+
DEBUG_WAY FALSE
|
| 754 |
+
DEBUG_L2MARKV FALSE
|
| 755 |
+
DEBUG_L2L1PREF FALSE
|
| 756 |
+
DEBUG_PERF_PRED FALSE
|
| 757 |
+
DEBUG_POWER_UTILS FALSE
|
| 758 |
+
DEBUG_DVFS FALSE
|
| 759 |
+
DEBUG_TRACE_READ FALSE
|
| 760 |
+
DEBUG_INST_FIELDS FALSE
|
| 761 |
+
DEBUG_OP_FIELDS FALSE
|
| 762 |
+
DEBUG_PIN_EXEC_DRIVEN FALSE
|
| 763 |
+
DEBUG_CACHE_PART FALSE
|
| 764 |
+
DEBUG_OPTIMIZER2 FALSE
|
| 765 |
+
DEBUG_PREF FALSE
|
| 766 |
+
DEBUG_FDIP FALSE
|
| 767 |
+
DEBUG_EIP FALSE
|
| 768 |
+
DEBUG_DJOLT FALSE
|
| 769 |
+
DEBUG_FNLMMA FALSE
|
| 770 |
+
PERFECT_BP FALSE
|
| 771 |
+
PERFECT_BTB FALSE
|
| 772 |
+
PERFECT_IBP FALSE
|
| 773 |
+
PERFECT_CRS FALSE
|
| 774 |
+
PERFECT_CBR_BTB FALSE
|
| 775 |
+
PERFECT_NT_BTB FALSE 0 # deprecated, effectively always true.
|
| 776 |
+
CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle
|
| 777 |
+
UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 778 |
+
BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec.
|
| 779 |
+
BP_MECH TAGE64K_BP tage64k
|
| 780 |
+
BP_MECH_L0 BIMODAL_BP
|
| 781 |
+
BP_L0_LATENCY 1
|
| 782 |
+
BP_MAIN_LATENCY 3
|
| 783 |
+
BIMODAL_ENTRIES (4 * 1024)
|
| 784 |
+
HIST_LENGTH 16
|
| 785 |
+
PHT_CTR_BITS 2 const
|
| 786 |
+
BHT_ENTRIES (4 * 1024)
|
| 787 |
+
BHT_ASSOC 4
|
| 788 |
+
HYBRIDS_INDEX_LENGTH 16
|
| 789 |
+
HYBRIDG_HIST_LENGTH 16
|
| 790 |
+
HYBRIDP_HIST_LENGTH 16
|
| 791 |
+
FILTER_INDEX_LENGTH 16
|
| 792 |
+
USE_FILTER FALSE
|
| 793 |
+
INF_HYBRIDGP FALSE
|
| 794 |
+
BP_HASH_TOS FALSE
|
| 795 |
+
IBTB_HASH_TOS FALSE
|
| 796 |
+
BTB_MECH GENERIC_BTB generic
|
| 797 |
+
BTB_ENTRIES 12288 12288
|
| 798 |
+
BTB_ASSOC 4 4
|
| 799 |
+
BTB_NUM_BRSLOT 1
|
| 800 |
+
BTB_BLOCK_SIZE 64
|
| 801 |
+
BTB_OFF_PATH_WRITES TRUE 1
|
| 802 |
+
BTB_MAIN_LATENCY 3 3
|
| 803 |
+
BTB_L0_PRESENT FALSE 1
|
| 804 |
+
BTB_L0_ENTRIES 128 128
|
| 805 |
+
BTB_L0_ASSOC 4 4
|
| 806 |
+
BTB_L0_LATENCY 1 1
|
| 807 |
+
BTB_L1_PRESENT FALSE 1
|
| 808 |
+
BTB_L1_ENTRIES 6144 6144
|
| 809 |
+
BTB_L1_ASSOC 4 4
|
| 810 |
+
BTB_L1_LATENCY 2 2
|
| 811 |
+
ENABLE_CRS TRUE 1
|
| 812 |
+
CRS_ENTRIES 32 128
|
| 813 |
+
CRS_REALISTIC 0 1
|
| 814 |
+
ENABLE_IBP TRUE 1 # Enable the indirect branch predictor
|
| 815 |
+
USE_PAT_HIST TRUE
|
| 816 |
+
IBTB_MECH 1 tc_tagged
|
| 817 |
+
IBTB_HIST_LENGTH 16
|
| 818 |
+
IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb.
|
| 819 |
+
TARGETS_IN_HIST 4
|
| 820 |
+
TC_ENTRIES (4 * 1024) 4096
|
| 821 |
+
TC_ASSOC 4 4
|
| 822 |
+
NUM_CORR_BRANCHES 3
|
| 823 |
+
SEL_HIST_BP_ENTRIES 8192
|
| 824 |
+
SEL_HIST_LENGTH 16
|
| 825 |
+
SEL_HIST_DYN_CNT_TH 16
|
| 826 |
+
SEL_HIST_MISPRED_TH 4
|
| 827 |
+
ENABLE_BP_CONF FALSE
|
| 828 |
+
CONF_MECH 0
|
| 829 |
+
PERF_BP_CONF_PRED FALSE
|
| 830 |
+
BPC_BITS 16
|
| 831 |
+
BPC_MECH 1
|
| 832 |
+
BPC_CTR_RESET TRUE
|
| 833 |
+
BPC_CIT_BITS 8
|
| 834 |
+
BPC_CIT_TH 50
|
| 835 |
+
BPC_CTR_BITS 3
|
| 836 |
+
OPC_COUNT_ZEROS FALSE
|
| 837 |
+
OPC_COUNT_THRESH 10
|
| 838 |
+
INF_LOOP FALSE
|
| 839 |
+
INF_LOOP_BUCKETS 811
|
| 840 |
+
LOOP_ENTRIES (4 * 1024)
|
| 841 |
+
LOOP_ASSOC 4
|
| 842 |
+
LOOP_COUNT_MAX 127
|
| 843 |
+
LOOP_REPEAT_MAX 15
|
| 844 |
+
KNOB_PRINT_BRINFO FALSE
|
| 845 |
+
BR_MISPRED_FILE NULL
|
| 846 |
+
SPEC_LEVEL 3
|
| 847 |
+
RANDOM_DETERMINISTIC TRUE
|
| 848 |
+
TAGESCL64KB_SC TRUE
|
| 849 |
+
TAGESCL64KB_LOOP TRUE
|
| 850 |
+
TAGESCL64KB_ALT TRUE
|
| 851 |
+
CONF_PERCEPTRON_TH 0
|
| 852 |
+
CONF_PERCEPTRON_CTR_BITS 8
|
| 853 |
+
CONF_PERCEPTRON_ENTRIES 127
|
| 854 |
+
CONF_PERCEPTRON_THRESH_OVRD 0
|
| 855 |
+
CONF_HIST_LENGTH 32
|
| 856 |
+
PERCEPTRON_CONF_USE_CONF FALSE
|
| 857 |
+
PERCEPTRON_CONF_TRAIN_HIS FALSE
|
| 858 |
+
PERCEPTRON_CONF_TRAIN_CONF FALSE
|
| 859 |
+
PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE
|
| 860 |
+
PERCEPTRON_TRAIN_MISP_FACTOR 1
|
| 861 |
+
PERCEPTRON_TRAIN_CORR_FACTOR 1
|
| 862 |
+
PERCEPTRON_CONF_HIS_BOTH FALSE
|
| 863 |
+
PERCEPTRON_CONF_HIS_BOTH_LENGTH 4
|
| 864 |
+
MTAGE_REALISTIC_SC_40K FALSE
|
| 865 |
+
MTAGE_REALISTIC_SC_100K FALSE
|
| 866 |
+
H2P_TABLE_BUCKETS 16384
|
| 867 |
+
H2P_MIN_EXEC 5000
|
| 868 |
+
H2P_MIN_MISPRED 333
|
| 869 |
+
H2P_MISPRED_RATIO_PERMIL 10
|
| 870 |
+
H2P_TRACK_CBR TRUE
|
| 871 |
+
H2P_TRACK_REP TRUE
|
| 872 |
+
H2P_TRACK_CALL FALSE
|
| 873 |
+
H2P_TRACK_IBR FALSE
|
| 874 |
+
H2P_TRACK_ICALL FALSE
|
| 875 |
+
H2P_TRACK_RET FALSE
|
| 876 |
+
POWER_INTF_ON FALSE
|
| 877 |
+
POWER_INTF_ENABLE_SCALING FALSE
|
| 878 |
+
POWER_INTF_EXEC "power/power_intf.py"
|
| 879 |
+
POWER_INTF_REF_CHIP_TECH_NM 22
|
| 880 |
+
POWER_INTF_REF_CHIP_FREQ (3.2e9)
|
| 881 |
+
POWER_INTF_REF_MEMORY_FREQ (0.8e9)
|
| 882 |
+
POWER_OTHER (0.0)
|
| 883 |
+
PREF_STREAM_ON FALSE 1
|
| 884 |
+
PREF_STREAM_PER_CORE_ENABLE FALSE
|
| 885 |
+
STREAM_BUFFER_N 16
|
| 886 |
+
STREAM_PREFETCH_N 2 4
|
| 887 |
+
STREAM_START_DIS 5 1
|
| 888 |
+
STREAM_LENGTH 16 64
|
| 889 |
+
STREAM_FULL_N 1
|
| 890 |
+
STREAM_TRAIN_LENGTH 16
|
| 891 |
+
STREAM_TRAIN_NUM 1 4
|
| 892 |
+
PREF_ACC_USE_CACHE FALSE
|
| 893 |
+
STREAM_STALL_ON_QUEUE_FULL FALSE
|
| 894 |
+
PREF_SCHEDULE_NUM 4
|
| 895 |
+
TRAIN_FILTER_SIZE 32
|
| 896 |
+
PREF_REQ_Q_SIZE 64
|
| 897 |
+
STREAM_CREATE_ON_DC_MISS FALSE 0
|
| 898 |
+
STREAM_CREATE_ON_L1_MISS TRUE 1
|
| 899 |
+
STREAM_TRAIN_ON_WRONGPATH TRUE
|
| 900 |
+
STREAM_CREATE_ON_WRONGPATH TRUE
|
| 901 |
+
STREAM_PREF_INTO_DCACHE FALSE
|
| 902 |
+
REMOVE_REDUNDANT_STREAM FALSE
|
| 903 |
+
L2HIT_STREAM_SCHEDULE_NUM 4
|
| 904 |
+
PREF_REQ_QUEUE_FILTER_ON FALSE
|
| 905 |
+
HW_PREF_HIT_TRAIN_STREAM FALSE
|
| 906 |
+
L2HIT_STREAM_BUFFER_N 32
|
| 907 |
+
L2HIT_STREAM_PREFETCH_N 2
|
| 908 |
+
L2HIT_STREAM_START_DIS 2
|
| 909 |
+
L2HIT_STREAM_LENGTH 8
|
| 910 |
+
L2HIT_PREF_REQ_Q_SIZE 128
|
| 911 |
+
L2HIT_L2ACCESS_REQ_Q_SIZE 64
|
| 912 |
+
PREF_STREAM_ACCPERSTREAM FALSE
|
| 913 |
+
PREF_ACC_DISTANCE_10 128
|
| 914 |
+
PREF_FRAMEWORK_ON FALSE 1
|
| 915 |
+
PREF_TRACE_ON FALSE
|
| 916 |
+
PREF_UMLC_ON FALSE
|
| 917 |
+
PREF_UL1_ON TRUE
|
| 918 |
+
PREF_DL0REQ_QUEUE_SIZE 32
|
| 919 |
+
PREF_UMLC_REQ_QUEUE_SIZE 64
|
| 920 |
+
PREF_UL1REQ_QUEUE_SIZE 128
|
| 921 |
+
PREF_SHARED_QUEUES TRUE
|
| 922 |
+
PREF_DL0_MISS_ON TRUE
|
| 923 |
+
PREF_DL0_HIT_ON TRUE
|
| 924 |
+
PREF_DL0REQ_QUEUE_FILTER_ON TRUE
|
| 925 |
+
PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE
|
| 926 |
+
PREF_UL1REQ_QUEUE_FILTER_ON TRUE
|
| 927 |
+
PREF_DL0REQ_ADD_FILTER_ON TRUE
|
| 928 |
+
PREF_UMLC_REQ_ADD_FILTER_ON TRUE
|
| 929 |
+
PREF_UL1REQ_ADD_FILTER_ON TRUE
|
| 930 |
+
PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 931 |
+
PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 932 |
+
PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1
|
| 933 |
+
PREF_DL0SCHEDULE_NUM 4
|
| 934 |
+
PREF_UMLC_SCHEDULE_NUM 4
|
| 935 |
+
PREF_UL1SCHEDULE_NUM 4
|
| 936 |
+
PREF_L1Q_DEMAND_RESERVE 0
|
| 937 |
+
PREF_REPORT_PREF_MATCH_AS_MISS FALSE
|
| 938 |
+
PREF_REPORT_PREF_MATCH_AS_HIT TRUE
|
| 939 |
+
PREF_UPDATE_ON_WRONGPATH TRUE
|
| 940 |
+
PREF_TRAIN_ON_PREF_MISSES FALSE 0
|
| 941 |
+
PREF_ORACLE_TRAIN_ON FALSE 0
|
| 942 |
+
PREF_REQ_DROP FALSE
|
| 943 |
+
PREF_THROTTLE_ON FALSE
|
| 944 |
+
PREF_THROTTLEFB_ON FALSE 1
|
| 945 |
+
PREF_ACC_THRESH_1 0.90 0.75
|
| 946 |
+
PREF_ACC_THRESH_2 0.70 0.4
|
| 947 |
+
PREF_ACC_THRESH_3 0.60 0.4
|
| 948 |
+
PREF_ACC_THRESH_4 0.40
|
| 949 |
+
PREF_UPDATE_INTERVAL 0 8192
|
| 950 |
+
PREF_ANALYZE_LOAD FALSE
|
| 951 |
+
PREF_POL_THRESH_1 0.25
|
| 952 |
+
PREF_POL_THRESH_2 0.10
|
| 953 |
+
PREF_POLBV_ON FALSE
|
| 954 |
+
PREF_POLBV_SIZE 1024
|
| 955 |
+
PREF_TIMELY_THRESH 0.05 0.01
|
| 956 |
+
PREF_POLPF_THRESH 0.01 0.005
|
| 957 |
+
PREF_DEGFB_USEONLYACC FALSE
|
| 958 |
+
PREF_DEGFB_USEONLYPOL FALSE
|
| 959 |
+
PREF_DEGFB_USEONLYLATE FALSE
|
| 960 |
+
PREF_TIMELY_THRESH_2 0.005
|
| 961 |
+
PREF_DEGFB_STATPHASEFILE FALSE
|
| 962 |
+
PREF_MAX_DEGFB 4
|
| 963 |
+
PREF_DHAL FALSE
|
| 964 |
+
PREF_DHAL_SENTTHRESH 16
|
| 965 |
+
PREF_DHAL_USETHRESH_MAX 12
|
| 966 |
+
PREF_DHAL_USETHRESH_MIN2 8
|
| 967 |
+
PREF_DHAL_USETHRESH_MIN1 4
|
| 968 |
+
PREF_DHAL_MAXDEG 64
|
| 969 |
+
PREF_HFILTER_ON FALSE
|
| 970 |
+
PREF_HFILTER_INDEX_BITS 12
|
| 971 |
+
PREF_HFILTER_USE_PC FALSE
|
| 972 |
+
PREF_HFILTER_PRED_USELESS_THRES 2
|
| 973 |
+
PREF_HFILTER_RESET_ENABLE FALSE
|
| 974 |
+
PREF_HFILTER_RESET_INTERVAL 100000
|
| 975 |
+
EIP_ENABLE 0
|
| 976 |
+
L1I_ENTANGLED_TABLE_INDEX_BITS 9
|
| 977 |
+
L1I_ENTANGLED_TABLE_WAYS 16
|
| 978 |
+
DJOLT_ENABLE 0
|
| 979 |
+
FNLMMA_ENABLE 0
|
| 980 |
+
FDIP_ENABLE 1
|
| 981 |
+
FDIP_ALWAYS_PREFETCH FALSE
|
| 982 |
+
PERFECT_FDIP FALSE
|
| 983 |
+
IPRF_MAX_FTQ_ENTRY_CYC 2
|
| 984 |
+
FDIP_BLOOM_FILTER FALSE
|
| 985 |
+
FDIP_BLOOM_ENTRIES 4000
|
| 986 |
+
FDIP_BLOOM2_ENTRIES 1000
|
| 987 |
+
FDIP_BLOOM4_ENTRIES 1000
|
| 988 |
+
FDIP_BLOOM_SIZE 16384
|
| 989 |
+
FDIP_BLOOM_HASHES 6
|
| 990 |
+
FDIP_BLOOM_CLEAR_UNUSEFUL_RATIO 0.95
|
| 991 |
+
FDIP_BLOOM_CLEAR_CYC_PERIOD 10000
|
| 992 |
+
FDIP_UTILITY_HASH_ENABLE 0
|
| 993 |
+
FDIP_UTILITY_PREF_POLICY 0
|
| 994 |
+
FDIP_ADJUSTABLE_FTQ 0
|
| 995 |
+
FDIP_ADJUSTABLE_FTQ_CYC 100000
|
| 996 |
+
UTILITY_RATIO_THRESHOLD 0.58
|
| 997 |
+
TIMELINESS_RATIO_THRESHOLD 0.82
|
| 998 |
+
FDIP_PREF_NO_LATENCY FALSE
|
| 999 |
+
UDP_USEFUL_THRESHOLD 0
|
| 1000 |
+
UDP_WEIGHT_USEFUL 4
|
| 1001 |
+
UDP_WEIGHT_UNUSEFUL 1
|
| 1002 |
+
UDP_WEIGHT_POSITIVE_SATURATION 2147483647
|
| 1003 |
+
FDIP_GHIST_HASHING FALSE
|
| 1004 |
+
FDIP_UTILITY_ONLY_TRAIN_OFF_PATH FALSE
|
| 1005 |
+
FDIP_GHIST_BITS 8
|
| 1006 |
+
UFTQ_MIN_FTQ_BLOCK_NUM 4
|
| 1007 |
+
UFTQ_MAX_FTQ_BLOCK_NUM 64
|
| 1008 |
+
FDIP_SENIORITY_FTQ_HOLD_CYC 30000
|
| 1009 |
+
FDIP_PERFECT_PREFETCH FALSE
|
| 1010 |
+
FDIP_FREEZE_AT_MEM_BUF_LIMIT TRUE
|
| 1011 |
+
FDIP_DUAL_PATH_PREF_IC_ENABLE FALSE
|
| 1012 |
+
FDIP_DUAL_PATH_PREF_UOC_ENABLE FALSE
|
| 1013 |
+
TOP_MISPRED_BR_FILEPATH "br_resteer_coverage.csv"
|
| 1014 |
+
TOP_MISPRED_BR_RESTEER_COVERAGE 0
|
| 1015 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_ENABLE FALSE
|
| 1016 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_MISPRED_THRESHOLD 1
|
| 1017 |
+
FDIP_PRINT_CL_INFO FALSE
|
| 1018 |
+
BRANCH_MISPREDICTION_TABLE_SIZE 0
|
| 1019 |
+
UOC_PREF FALSE
|
| 1020 |
+
UOC_ORACLE_PREF FALSE
|
| 1021 |
+
UOC_ZERO_LATENCY_PREF FALSE
|
| 1022 |
+
L2L1PREF_ON FALSE
|
| 1023 |
+
L2WAY_PREF FALSE
|
| 1024 |
+
L2MARKV_PREF_ON FALSE
|
| 1025 |
+
L2NEXT_PREF_ON FALSE
|
| 1026 |
+
L2HIT_STREAM_PREF_ON FALSE
|
| 1027 |
+
L2L1_DC_HIT_TRAIN FALSE
|
| 1028 |
+
L1_HIT_DUMP_FILE_ON FALSE
|
| 1029 |
+
L1_HIT_DUMP_WO_TXT FALSE
|
| 1030 |
+
L1_HIT_DUMPFILE "l1hit_dump.out"
|
| 1031 |
+
IDEAL_L2_L1_PREFETCHER FALSE
|
| 1032 |
+
IDEAL_L2_ICACHE_PREFETCHER FALSE
|
| 1033 |
+
L1WAY_PREF_SEND_QUEUE 4
|
| 1034 |
+
L1PREF_REQ_QUEUE_SIZE 1024
|
| 1035 |
+
L1PREF_IMMEDIATE FALSE
|
| 1036 |
+
L1WAY_PREF_TIMER_DIS 1000
|
| 1037 |
+
L1MARKV_PREF_SEND_QUEUE 4
|
| 1038 |
+
L1PREF_MARKV_REQ_QUEUE_SIZE 1024
|
| 1039 |
+
MARKV_L2ACCESS_REQ_Q_SIZE 64
|
| 1040 |
+
L1MARKV_PREF_IMMEDIATE FALSE
|
| 1041 |
+
L1MARKV_PREF_TIMER_DIS 1
|
| 1042 |
+
L2L1_HIT_TRAIN TRUE
|
| 1043 |
+
L1MARKV_REQ_TH 1
|
| 1044 |
+
L2L1_IMMEDIATE_PREF_CACHE FALSE
|
| 1045 |
+
L2L1_FILL_PREF_CACHE FALSE
|
| 1046 |
+
L2L1_L2_HIT_STAT FALSE
|
| 1047 |
+
PREF_GHB_ON FALSE
|
| 1048 |
+
DEBUG_PREF_GHB FALSE
|
| 1049 |
+
PREF_GHB_BUFFER_N 1024
|
| 1050 |
+
PREF_GHB_INDEX_N 128
|
| 1051 |
+
PREF_GHB_CZONE_BITS 12
|
| 1052 |
+
PREF_GHB_DEGREE 16
|
| 1053 |
+
PREF_GHB_MAX_DEGREE 32
|
| 1054 |
+
PREF_STRIDE_ON FALSE
|
| 1055 |
+
DEBUG_PREF_STRIDE FALSE
|
| 1056 |
+
PREF_STRIDE_TABLE_N 1024
|
| 1057 |
+
PREF_STRIDE_REGION_BITS 16
|
| 1058 |
+
PREF_STRIDE_DEGREE 4
|
| 1059 |
+
PREF_STRIDE_DISTANCE 16
|
| 1060 |
+
PREF_STRIDE_STARTDISTANCE 1
|
| 1061 |
+
PREF_STRIDE_SINGLE_THRESH 6
|
| 1062 |
+
PREF_STRIDE_MULTI_THRESH 6
|
| 1063 |
+
PREF_STRIDE_SINGLE_STRIDE_MODE FALSE
|
| 1064 |
+
PREF_STRIDEPC_ON FALSE
|
| 1065 |
+
DEBUG_PREF_STRIDEPC FALSE
|
| 1066 |
+
PREF_STRIDEPC_TABLE_N 1024
|
| 1067 |
+
PREF_STRIDEPC_DEGREE 4
|
| 1068 |
+
PREF_STRIDEPC_DISTANCE 16
|
| 1069 |
+
PREF_STRIDEPC_USELOADADDR FALSE
|
| 1070 |
+
PREF_STRIDEPC_TRAINNUM 2
|
| 1071 |
+
PREF_STRIDEPC_STARTDIS 4
|
| 1072 |
+
PREF_PHASE_ON FALSE
|
| 1073 |
+
PREF_PHASE_STUDY FALSE
|
| 1074 |
+
DEBUG_PREF_PHASE FALSE
|
| 1075 |
+
PREF_PHASE_PRIME_HASH 16381
|
| 1076 |
+
PREF_PHASE_INFOSIZE 16384
|
| 1077 |
+
PREF_PHASE_LOG2REGIONSIZE 12
|
| 1078 |
+
PREF_PHASE_REGIONENTRIES 64
|
| 1079 |
+
PREF_PHASE_TRACKEDREGIONS 32
|
| 1080 |
+
PREF_PHASE_INTERVAL 100000
|
| 1081 |
+
PREF_PHASE_TABLE_SIZE 64
|
| 1082 |
+
PREF_PHASE_MAXDIFF_THRESH 64
|
| 1083 |
+
PREF_PHASE_MIN_MISSES 64
|
| 1084 |
+
PREF_PHASE_MISSPER 0.4
|
| 1085 |
+
PREF_2DC_ON FALSE
|
| 1086 |
+
DEBUG_PREF_2DC FALSE
|
| 1087 |
+
PREF_2DC_CACHE_SIZE (1 * 1024)
|
| 1088 |
+
PREF_2DC_CACHE_ASSOC 4
|
| 1089 |
+
PREF_2DC_CACHE_LINE_SIZE 1
|
| 1090 |
+
PREF_2DC_DEGREE 16
|
| 1091 |
+
PREF_2DC_ZONE_SHIFT 10
|
| 1092 |
+
PREF_2DC_TAG_SIZE 16
|
| 1093 |
+
PREF_2DC_NUM_REGIONS 64
|
| 1094 |
+
PREF_2DC_REGION_HASH 61
|
| 1095 |
+
PREF_MARKOV_ON FALSE
|
| 1096 |
+
DEBUG_PREF_MARKOV FALSE
|
| 1097 |
+
PREF_MARKOV_NUM_ENTRIES 65536
|
| 1098 |
+
PREF_MARKOV_NUM_NEXT_STATES 8
|
| 1099 |
+
PREF_MARKOV_SEND_ON_PREF_HIT TRUE
|
| 1100 |
+
PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE
|
| 1101 |
+
PREF_MARKOV_TABLE_UPDATE_POLICY 0
|
| 1102 |
+
PREF_MARKOV_SEND_THRESHOLD 0
|
sssp_facebook/fingerprint/run_7/sim.log
ADDED
|
@@ -0,0 +1,59 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
[0]: ad: 0x7ffff3d9b7b7, op: 109
|
| 2 |
+
[0]: ad: 0x7ffff3d9b7bb, op: 315
|
| 3 |
+
new bb detected: 1
|
| 4 |
+
[1]: ad: 0x7ffff3d9b7c1, op: 427
|
| 5 |
+
[1]: ad: 0x7ffff3d9b7c8, op: 427
|
| 6 |
+
[1]: ad: 0x7ffff3d9b7cc, op: 847
|
| 7 |
+
[1]: ad: 0x7ffff3d9b7cf, op: 330
|
| 8 |
+
new bb detected: 2
|
| 9 |
+
[2]: ad: 0x7ffff3d9b7b0, op: 388
|
| 10 |
+
[2]: ad: 0x7ffff3d9b7b3, op: 8
|
| 11 |
+
[2]: ad: 0x7ffff3d9b7b7, op: 109
|
| 12 |
+
[2]: ad: 0x7ffff3d9b7bb, op: 315
|
| 13 |
+
new bb detected: 3
|
| 14 |
+
Scarab gitrev: 7185dea
|
| 15 |
+
Warning: Scarab expects the trace file type to include OFFLINE_FILE_TYPE_ARCH_REGDEPS (0x20000), but got type: 0xe40
|
| 16 |
+
Scarab started at Fri Jul 17 23:07:24 2026
|
| 17 |
+
|
| 18 |
+
read from initialization: 0x7ffff3d9b7b7
|
| 19 |
+
advanceReader: ROI end reached (ordinal 80000002 > roi_end 80000000)
|
| 20 |
+
Reached end of trace (last_inst) pc=0x7ffff3d9b7b7
|
| 21 |
+
[3]: ad: 0x7ffff3d9b7b0, op: 388
|
| 22 |
+
[3]: ad: 0x7ffff3d9b7b3, op: 8
|
| 23 |
+
DUP bb detected at trace end
|
| 24 |
+
to be appened segment num 1
|
| 25 |
+
10000000
|
| 26 |
+
10000000
|
| 27 |
+
====================================
|
| 28 |
+
TRACE_INST_TAKEN_NOT_CF:0
|
| 29 |
+
TRACE_INST_TAKEN_CF_BR:0
|
| 30 |
+
TRACE_INST_TAKEN_CF_CBR:1250000
|
| 31 |
+
TRACE_INST_TAKEN_CF_REP:0
|
| 32 |
+
TRACE_INST_TAKEN_CF_CALL:0
|
| 33 |
+
TRACE_INST_TAKEN_CF_IBR:0
|
| 34 |
+
TRACE_INST_TAKEN_CF_ICALL:0
|
| 35 |
+
TRACE_INST_TAKEN_CF_ICO:0
|
| 36 |
+
TRACE_INST_TAKEN_CF_RET:0
|
| 37 |
+
TRACE_INST_TAKEN_CF_SYS:0
|
| 38 |
+
====================================
|
| 39 |
+
identity within this segment
|
| 40 |
+
2 bbs with same first pc
|
| 41 |
+
[3]: size 4, freq 1249999
|
| 42 |
+
7ffff3d9b7b0: 388, 0
|
| 43 |
+
7ffff3d9b7b3: 8, 0
|
| 44 |
+
7ffff3d9b7b7: 109, 0
|
| 45 |
+
7ffff3d9b7bb: 315, 0
|
| 46 |
+
[3]: size 2, freq 1
|
| 47 |
+
7ffff3d9b7b0: 388, 0
|
| 48 |
+
7ffff3d9b7b3: 8, 0
|
| 49 |
+
1 / 3
|
| 50 |
+
========================================================
|
| 51 |
+
Number of blocks built : 3
|
| 52 |
+
Average size : 3.33 instructions
|
| 53 |
+
Number of blocks executed : 2500001
|
| 54 |
+
Average weighted size : 4.00 instructions
|
| 55 |
+
Number of total instructions : 10000000
|
| 56 |
+
Number of fetched instruction : 10000000
|
| 57 |
+
========================================================
|
| 58 |
+
Scarab finished at Fri Jul 17 23:07:28 2026
|
| 59 |
+
|
sssp_facebook/fingerprint/run_8/PARAMS.in
ADDED
|
@@ -0,0 +1,268 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
| 1 |
+
# File : PARAMS.golden_cove
|
| 2 |
+
# Date : 02/27/25
|
| 3 |
+
# Description : Golden Cove Configuration
|
| 4 |
+
# Author : Surim Oh <[email protected]>
|
| 5 |
+
#
|
| 6 |
+
# Based on documentation found here:
|
| 7 |
+
# https://en.wikipedia.org/wiki/Golden_Cove
|
| 8 |
+
# https://en.wikichip.org/wiki/intel/microarchitectures/golden_cove
|
| 9 |
+
# https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/3
|
| 10 |
+
|
| 11 |
+
## Simulation Parameters
|
| 12 |
+
--mode full
|
| 13 |
+
--model cmp
|
| 14 |
+
--sim_limit none
|
| 15 |
+
|
| 16 |
+
## Core Parameters
|
| 17 |
+
|
| 18 |
+
# Femptoseconds, 3.2GHz, used for energy estimates.
|
| 19 |
+
--chip_cycle_time 312500
|
| 20 |
+
|
| 21 |
+
|
| 22 |
+
### Fetch Stage
|
| 23 |
+
--fetch_off_path_ops 1
|
| 24 |
+
|
| 25 |
+
#### ICache
|
| 26 |
+
--icache_size 32768
|
| 27 |
+
--icache_assoc 8
|
| 28 |
+
--icache_line_size 64
|
| 29 |
+
|
| 30 |
+
### Uop Cache
|
| 31 |
+
# inclusive w/ L1i
|
| 32 |
+
--uop_cache_enable 1
|
| 33 |
+
--uop_cache_width 8
|
| 34 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 35 |
+
--uop_cache_assoc 8
|
| 36 |
+
--iprf_on_uop_cache_hit 1
|
| 37 |
+
|
| 38 |
+
### Branch Predictor
|
| 39 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 40 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 41 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 42 |
+
--bp_mech tage64k
|
| 43 |
+
|
| 44 |
+
|
| 45 |
+
#### BTB
|
| 46 |
+
|
| 47 |
+
# TODO
|
| 48 |
+
# multi-level BTB
|
| 49 |
+
# 128 entry L0 BTB
|
| 50 |
+
# 6144 entry L1 BTB
|
| 51 |
+
# 12888 entry L2 BTB
|
| 52 |
+
# ~2 entry Return Stack
|
| 53 |
+
# roughly 2x8192 for now
|
| 54 |
+
# BTB model to use.
|
| 55 |
+
--btb_mech generic
|
| 56 |
+
--btb_entries 12288
|
| 57 |
+
--btb_assoc 4
|
| 58 |
+
--btb_main_latency 3
|
| 59 |
+
--btb_l0_present 1
|
| 60 |
+
--btb_l0_entries 128
|
| 61 |
+
--btb_l0_assoc 4
|
| 62 |
+
--btb_l0_latency 1
|
| 63 |
+
--btb_l1_present 1
|
| 64 |
+
--btb_l1_entries 6144
|
| 65 |
+
--btb_l1_assoc 4
|
| 66 |
+
--btb_l1_latency 2
|
| 67 |
+
|
| 68 |
+
# Allow the BTB to be updated by off path ops.
|
| 69 |
+
--btb_off_path_writes 1
|
| 70 |
+
|
| 71 |
+
# NT branches are not inserted in BTB, but do not trigger resteer
|
| 72 |
+
# since we continue without a control flow change
|
| 73 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 74 |
+
|
| 75 |
+
#### CRS
|
| 76 |
+
|
| 77 |
+
# Enable return stack
|
| 78 |
+
--enable_crs 1
|
| 79 |
+
--crs_entries 128
|
| 80 |
+
--crs_realistic 1
|
| 81 |
+
|
| 82 |
+
### iBP
|
| 83 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 84 |
+
--ibtb_mech tc_tagged
|
| 85 |
+
# iBTB Model. tc_tagless, tc_tagged, tc_hybrid.
|
| 86 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 87 |
+
--tc_entries 4096
|
| 88 |
+
--tc_assoc 4
|
| 89 |
+
|
| 90 |
+
### Decode Stage
|
| 91 |
+
--decode_width 6
|
| 92 |
+
--decode_cycles 5
|
| 93 |
+
|
| 94 |
+
### Instruction Decode Queue
|
| 95 |
+
--idq_size 144
|
| 96 |
+
|
| 97 |
+
### Map Stage
|
| 98 |
+
--map_cycles 5
|
| 99 |
+
|
| 100 |
+
# register renaming table
|
| 101 |
+
--reg_renaming_scheme 1
|
| 102 |
+
--reg_table_integer_physical_size 280
|
| 103 |
+
--reg_table_vector_physical_size 332
|
| 104 |
+
|
| 105 |
+
### Issue Stage
|
| 106 |
+
|
| 107 |
+
# Max number of instructions to be renamed, and issued per cycle.
|
| 108 |
+
--issue_width 6
|
| 109 |
+
|
| 110 |
+
--rs_fill_width 0
|
| 111 |
+
# rs_sizes ~205 in total, and they are split into three different reservation stations (RS1, RS2, RS3) where each has 97, 70, 38 entries respectively
|
| 112 |
+
# original architecture
|
| 113 |
+
# RS1 connected to port 0,1,5,6,10
|
| 114 |
+
# RS2 connected to port 2,3,11
|
| 115 |
+
# RS3 connected to port 7,8,4,9
|
| 116 |
+
# scarab does not split ST AGU port and ST port, merge them
|
| 117 |
+
# adjusted architecture to scarab ST AGU (port 4 and 9 removed. rs_size reduced to 186 from 205)
|
| 118 |
+
# RS1 connected to port 0,1,4,5,8
|
| 119 |
+
# RS2 connected to port 2,3,9
|
| 120 |
+
# RS3 connected to port 6,7 (port 4,9 removed, entries reduced to 19 from 38)
|
| 121 |
+
--rs_sizes 97 70 19
|
| 122 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 123 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 124 |
+
|
| 125 |
+
### Exec Stage
|
| 126 |
+
|
| 127 |
+
### DCache
|
| 128 |
+
--dcache_size 49152
|
| 129 |
+
--dcache_read_ports 1
|
| 130 |
+
--dcache_write_ports 1
|
| 131 |
+
--dcache_banks 8
|
| 132 |
+
--dcache_assoc 12
|
| 133 |
+
--dcache_line_size 64
|
| 134 |
+
--dcache_cycles 5
|
| 135 |
+
|
| 136 |
+
### Reorder/Retire Stage
|
| 137 |
+
|
| 138 |
+
# Max number of instructions to be retired per cycle.
|
| 139 |
+
--node_ret_width 8
|
| 140 |
+
--node_table_size 512
|
| 141 |
+
|
| 142 |
+
# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does
|
| 143 |
+
--stores_do_not_block_window 1
|
| 144 |
+
|
| 145 |
+
# TODO: confirm what this knob does
|
| 146 |
+
--prefs_do_not_block_window 1
|
| 147 |
+
|
| 148 |
+
|
| 149 |
+
## Uncore
|
| 150 |
+
|
| 151 |
+
### Mid-level cache
|
| 152 |
+
|
| 153 |
+
# Enable use of a midlevel cache between i/d and L1
|
| 154 |
+
# client 1.25 MiB (1310720 bytes) per core, 8-way, 15 cycles
|
| 155 |
+
# server 2 MiB (2097000 bytes) per core, 8-way, 16 cycles
|
| 156 |
+
--mlc_present 1
|
| 157 |
+
--mlc_size 2097000
|
| 158 |
+
--mlc_assoc 8
|
| 159 |
+
--mlc_cycles 16
|
| 160 |
+
|
| 161 |
+
|
| 162 |
+
### LLC
|
| 163 |
+
# 3 MiB per core, 16-way
|
| 164 |
+
--l1_size 3145728
|
| 165 |
+
--l1_banks 8
|
| 166 |
+
--l1_cycles 36 // just a guess
|
| 167 |
+
--l1_assoc 16
|
| 168 |
+
--l1_line_size 64
|
| 169 |
+
--l1_interleave_factor 64
|
| 170 |
+
|
| 171 |
+
|
| 172 |
+
### prefetcher
|
| 173 |
+
# Kept same as Kaby Lake
|
| 174 |
+
--pref_framework_on 1
|
| 175 |
+
--pref_stream_on 1
|
| 176 |
+
--pref_train_on_pref_misses 0
|
| 177 |
+
--pref_oracle_train 0
|
| 178 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 179 |
+
|
| 180 |
+
--stream_length 64
|
| 181 |
+
--stream_prefetch_n 4
|
| 182 |
+
--stream_start_dis 1
|
| 183 |
+
--stream_train_num 4
|
| 184 |
+
--stream_create_on_dc_miss 0
|
| 185 |
+
--stream_create_on_l1_miss 1
|
| 186 |
+
|
| 187 |
+
--pref_throttlefb_on=1
|
| 188 |
+
--pref_acc_thresh_1=0.75
|
| 189 |
+
--pref_acc_thresh_2=0.4
|
| 190 |
+
--pref_acc_thresh_3=0.4
|
| 191 |
+
--pref_timely_thresh=0.01
|
| 192 |
+
--pref_polpf_thresh=0.005
|
| 193 |
+
--pref_update_interval=8192
|
| 194 |
+
|
| 195 |
+
--mem_req_buffer_pref_watermark 4
|
| 196 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 197 |
+
|
| 198 |
+
### Memory
|
| 199 |
+
# Kept same as Kaby Lake
|
| 200 |
+
--addr_translation random
|
| 201 |
+
|
| 202 |
+
--mem_priority_ifetch 0
|
| 203 |
+
--mem_priority_dfetch 1
|
| 204 |
+
--mem_priority_dstore 2
|
| 205 |
+
--mem_priority_iprf 3
|
| 206 |
+
--mem_priority_dprf 4
|
| 207 |
+
--mem_priority_wb 5
|
| 208 |
+
--mem_priority_wb_nodirty 5
|
| 209 |
+
|
| 210 |
+
--mem_req_buffer_entries 32
|
| 211 |
+
--bus_width_in_bytes 8
|
| 212 |
+
|
| 213 |
+
--ramulator_standard DDR4
|
| 214 |
+
--ramulator_speed DDR4_2400R
|
| 215 |
+
--ramulator_org DDR4_8Gb_x8
|
| 216 |
+
--ramulator_channels 1
|
| 217 |
+
--ramulator_ranks 1
|
| 218 |
+
--ramulator_bankgroups 4
|
| 219 |
+
--ramulator_banks 4
|
| 220 |
+
--ramulator_chip_width 8
|
| 221 |
+
--ramulator_rows 65536
|
| 222 |
+
--ramulator_cols 1024
|
| 223 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 224 |
+
--ramulator_readq_entries 32
|
| 225 |
+
--ramulator_writeq_entries 32
|
| 226 |
+
--ramulator_record_cmd_trace FALSE
|
| 227 |
+
--ramulator_print_cmd_trace FALSE
|
| 228 |
+
--ramulator_tCK 833333
|
| 229 |
+
--ramulator_tCL 16
|
| 230 |
+
--ramulator_tCCD 6
|
| 231 |
+
--ramulator_tCCDS 4
|
| 232 |
+
--ramulator_tCCDL 6
|
| 233 |
+
--ramulator_tCWL 12
|
| 234 |
+
--ramulator_tBL 4
|
| 235 |
+
--ramulator_tWTR 9
|
| 236 |
+
--ramulator_tWTRS 3
|
| 237 |
+
--ramulator_tWTRL 9
|
| 238 |
+
--ramulator_tRP 16
|
| 239 |
+
--ramulator_tRPpb 16
|
| 240 |
+
--ramulator_tRPab 16
|
| 241 |
+
--ramulator_tRCD 16
|
| 242 |
+
--ramulator_tRCDR 16
|
| 243 |
+
--ramulator_tRCDW 16
|
| 244 |
+
--ramulator_tRAS 39
|
| 245 |
+
--dram_tech_in_nm 32
|
| 246 |
+
|
| 247 |
+
## Other
|
| 248 |
+
|
| 249 |
+
|
| 250 |
+
### Debug
|
| 251 |
+
--debug_inst_start 0
|
| 252 |
+
--debug_inst_stop -1
|
| 253 |
+
--debug_cycle_start 0
|
| 254 |
+
--debug_cycle_stop -1
|
| 255 |
+
|
| 256 |
+
|
| 257 |
+
## Stats and Params
|
| 258 |
+
--dump_params 1
|
| 259 |
+
--dump_stats 1
|
| 260 |
+
--dump_trace 0
|
| 261 |
+
|
| 262 |
+
####################################
|
| 263 |
+
--set_off_path_confirmed 1
|
| 264 |
+
|
| 265 |
+
--order_beyond_bus 1
|
| 266 |
+
|
| 267 |
+
--mem_ooo_stores 1
|
| 268 |
+
--mem_obey_store_dep 1
|
sssp_facebook/fingerprint/run_8/PARAMS.out
ADDED
|
@@ -0,0 +1,1102 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
--mode trace_bbv_distributed
|
| 2 |
+
--model cmp
|
| 3 |
+
--frontend memtrace
|
| 4 |
+
--sim_limit none
|
| 5 |
+
--memtrace_roi_begin 80000001
|
| 6 |
+
--memtrace_roi_end 90000000
|
| 7 |
+
--use_fetched_count 1
|
| 8 |
+
--dump_params 1
|
| 9 |
+
--dump_stats 1
|
| 10 |
+
--dump_trace 0
|
| 11 |
+
--trace_bbv_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.8
|
| 12 |
+
--trace_footprint_output /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.8
|
| 13 |
+
--segment_instr_count 10000000
|
| 14 |
+
--mlc_present 1
|
| 15 |
+
--mlc_size 2097000
|
| 16 |
+
--mlc_assoc 8
|
| 17 |
+
--mlc_cycles 16
|
| 18 |
+
--l1_size 3145728
|
| 19 |
+
--l1_assoc 16
|
| 20 |
+
--l1_line_size 64
|
| 21 |
+
--l1_cycles 36 // just a guess
|
| 22 |
+
--l1_banks 8
|
| 23 |
+
--l1_interleave_factor 64
|
| 24 |
+
--addr_translation random
|
| 25 |
+
--icache_size 32768
|
| 26 |
+
--icache_assoc 8
|
| 27 |
+
--icache_line_size 64
|
| 28 |
+
--uop_cache_enable 1
|
| 29 |
+
--uop_cache_width 8
|
| 30 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 31 |
+
--uop_cache_assoc 8
|
| 32 |
+
--iprf_on_uop_cache_hit 1
|
| 33 |
+
--dcache_size 49152
|
| 34 |
+
--dcache_assoc 12
|
| 35 |
+
--dcache_line_size 64
|
| 36 |
+
--dcache_cycles 5
|
| 37 |
+
--dcache_read_ports 1
|
| 38 |
+
--dcache_write_ports 1
|
| 39 |
+
--dcache_banks 8
|
| 40 |
+
--mem_ooo_stores 1
|
| 41 |
+
--mem_obey_store_dep 1
|
| 42 |
+
--mem_req_buffer_entries 32
|
| 43 |
+
--mem_priority_ifetch 0
|
| 44 |
+
--mem_priority_dfetch 1
|
| 45 |
+
--mem_priority_dstore 2
|
| 46 |
+
--mem_priority_iprf 3
|
| 47 |
+
--mem_priority_dprf 4
|
| 48 |
+
--mem_priority_wb 5
|
| 49 |
+
--mem_priority_wb_nodirty 5
|
| 50 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 51 |
+
--mem_req_buffer_pref_watermark 4
|
| 52 |
+
--order_beyond_bus 1
|
| 53 |
+
--set_off_path_confirmed 1
|
| 54 |
+
--ramulator_standard DDR4
|
| 55 |
+
--ramulator_speed DDR4_2400R
|
| 56 |
+
--ramulator_org DDR4_8Gb_x8
|
| 57 |
+
--ramulator_channels 1
|
| 58 |
+
--ramulator_ranks 1
|
| 59 |
+
--ramulator_bankgroups 4
|
| 60 |
+
--ramulator_banks 4
|
| 61 |
+
--ramulator_chip_width 8
|
| 62 |
+
--bus_width_in_bytes 8
|
| 63 |
+
--ramulator_rows 65536
|
| 64 |
+
--ramulator_cols 1024
|
| 65 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 66 |
+
--ramulator_readq_entries 32
|
| 67 |
+
--ramulator_writeq_entries 32
|
| 68 |
+
--ramulator_record_cmd_trace FALSE
|
| 69 |
+
--ramulator_print_cmd_trace FALSE
|
| 70 |
+
--ramulator_tCK 833333
|
| 71 |
+
--ramulator_tCL 16
|
| 72 |
+
--ramulator_tCCD 6
|
| 73 |
+
--ramulator_tCCDS 4
|
| 74 |
+
--ramulator_tCCDL 6
|
| 75 |
+
--ramulator_tCWL 12
|
| 76 |
+
--ramulator_tBL 4
|
| 77 |
+
--ramulator_tWTR 9
|
| 78 |
+
--ramulator_tWTRS 3
|
| 79 |
+
--ramulator_tWTRL 9
|
| 80 |
+
--ramulator_tRP 16
|
| 81 |
+
--ramulator_tRPpb 16
|
| 82 |
+
--ramulator_tRPab 16
|
| 83 |
+
--ramulator_tRCD 16
|
| 84 |
+
--ramulator_tRCDR 16
|
| 85 |
+
--ramulator_tRCDW 16
|
| 86 |
+
--ramulator_tRAS 39
|
| 87 |
+
--dram_tech_in_nm 32
|
| 88 |
+
--chip_cycle_time 312500
|
| 89 |
+
--issue_width 6
|
| 90 |
+
--rs_fill_width 0
|
| 91 |
+
--node_table_size 512
|
| 92 |
+
--node_ret_width 8
|
| 93 |
+
--decode_width 6
|
| 94 |
+
--idq_size 144
|
| 95 |
+
--reg_renaming_scheme 1
|
| 96 |
+
--reg_table_integer_physical_size 280
|
| 97 |
+
--reg_table_vector_physical_size 332
|
| 98 |
+
--rs_sizes 97 70 19
|
| 99 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 100 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 101 |
+
--decode_cycles 5
|
| 102 |
+
--map_cycles 5
|
| 103 |
+
--fetch_off_path_ops 1
|
| 104 |
+
--stores_do_not_block_window 1
|
| 105 |
+
--prefs_do_not_block_window 1
|
| 106 |
+
--cbp_trace_r0 /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 107 |
+
--debug_cycle_start 0
|
| 108 |
+
--debug_cycle_stop -1
|
| 109 |
+
--debug_inst_start 0
|
| 110 |
+
--debug_inst_stop -1
|
| 111 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 112 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 113 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 114 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 115 |
+
--bp_mech tage64k
|
| 116 |
+
--btb_mech generic
|
| 117 |
+
--btb_entries 12288
|
| 118 |
+
--btb_assoc 4
|
| 119 |
+
--btb_off_path_writes 1
|
| 120 |
+
--btb_main_latency 3
|
| 121 |
+
--btb_l0_present 1
|
| 122 |
+
--btb_l0_entries 128
|
| 123 |
+
--btb_l0_assoc 4
|
| 124 |
+
--btb_l0_latency 1
|
| 125 |
+
--btb_l1_present 1
|
| 126 |
+
--btb_l1_entries 6144
|
| 127 |
+
--btb_l1_assoc 4
|
| 128 |
+
--btb_l1_latency 2
|
| 129 |
+
--enable_crs 1
|
| 130 |
+
--crs_entries 128
|
| 131 |
+
--crs_realistic 1
|
| 132 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 133 |
+
--ibtb_mech tc_tagged
|
| 134 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 135 |
+
--tc_entries 4096
|
| 136 |
+
--tc_assoc 4
|
| 137 |
+
--pref_stream_on 1
|
| 138 |
+
--stream_prefetch_n 4
|
| 139 |
+
--stream_start_dis 1
|
| 140 |
+
--stream_length 64
|
| 141 |
+
--stream_train_num 4
|
| 142 |
+
--stream_create_on_dc_miss 0
|
| 143 |
+
--stream_create_on_l1_miss 1
|
| 144 |
+
--pref_framework_on 1
|
| 145 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 146 |
+
--pref_train_on_pref_misses 0
|
| 147 |
+
--pref_oracle_train_on 0
|
| 148 |
+
--pref_throttlefb_on 1
|
| 149 |
+
--pref_acc_thresh_1 0.75
|
| 150 |
+
--pref_acc_thresh_2 0.4
|
| 151 |
+
--pref_acc_thresh_3 0.4
|
| 152 |
+
--pref_update_interval 8192
|
| 153 |
+
--pref_timely_thresh 0.01
|
| 154 |
+
--pref_polpf_thresh 0.005
|
| 155 |
+
1 1 1 1 1 1 1
|
| 156 |
+
|
| 157 |
+
--- Cut out everything below to use this file as PARAMS.in ---
|
| 158 |
+
|
| 159 |
+
Parameter status at compile time and values supplied on the command line:
|
| 160 |
+
|
| 161 |
+
SIM_MODE 0 trace_bbv_distributed
|
| 162 |
+
SIM_MODEL 0 cmp
|
| 163 |
+
FRONTEND FE_PIN_EXEC_DRIVEN memtrace
|
| 164 |
+
INST_LIMIT NULL
|
| 165 |
+
SIM_LIMIT "none" none
|
| 166 |
+
FORWARD_PROGRESS_LIMIT 100000000
|
| 167 |
+
FORWARD_PROGRESS_INTERVAL 10000
|
| 168 |
+
FAST_FORWARD 0
|
| 169 |
+
FAST_FORWARD_TRACE_INS 0
|
| 170 |
+
FAST_FORWARD_UNTIL_ADDR 0
|
| 171 |
+
MEMTRACE_ROI_BEGIN 0 80000001
|
| 172 |
+
MEMTRACE_ROI_END 0 90000000
|
| 173 |
+
FULL_WARMUP 0
|
| 174 |
+
WARMUP 0
|
| 175 |
+
HEARTBEAT_INTERVAL 1000000
|
| 176 |
+
NUM_HEARTBEATS 0
|
| 177 |
+
USE_FETCHED_COUNT FALSE 1
|
| 178 |
+
PERIODIC_DUMP FALSE
|
| 179 |
+
FILE_TAG ""
|
| 180 |
+
OUTPUT_DIR "."
|
| 181 |
+
STATUS_FILE NULL
|
| 182 |
+
BINDIR NULL
|
| 183 |
+
DUMP_PARAMS TRUE 1
|
| 184 |
+
DUMP_STATS TRUE 1
|
| 185 |
+
DUMP_TRACE FALSE 0
|
| 186 |
+
CLEAR_STATS "never"
|
| 187 |
+
STATS_TO_TRACE NULL
|
| 188 |
+
STAT_TRACE_FILE "stats.trace"
|
| 189 |
+
STAT_TRACE_INTERVAL "i:100000"
|
| 190 |
+
PIPEVIEW FALSE
|
| 191 |
+
PIPEVIEW_FILE "pipeview"
|
| 192 |
+
MEMVIEW FALSE
|
| 193 |
+
MEMVIEW_FILE "memview.out"
|
| 194 |
+
MEMVIEW_START "never"
|
| 195 |
+
INST_HASH_TABLE_SIZE 524288 const
|
| 196 |
+
STDOUT_FILE NULL
|
| 197 |
+
STDERR_FILE NULL
|
| 198 |
+
PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp"
|
| 199 |
+
PRINT_PID FALSE
|
| 200 |
+
USE_UNSURE_FREE_LISTS FALSE
|
| 201 |
+
OPTIMIZER2_MAX_NUM_SLAVES 64
|
| 202 |
+
OPTIMIZER2_PERFECT_MEMORYLESS FALSE
|
| 203 |
+
EXIT_COND 0
|
| 204 |
+
NUM_NOPS 0
|
| 205 |
+
NOPS_BB_START 0x5000000
|
| 206 |
+
IGNORE_BAR_FETCH FALSE
|
| 207 |
+
TRACE_BBV_OUTPUT NULL /dev/shm/baseline/traces/sssp_facebook/fingerprint/pieces/segment.8
|
| 208 |
+
TRACE_FOOTPRINT_OUTPUT "" /dev/shm/baseline/traces/sssp_facebook/fingerprint/footprint_pieces/segment.8
|
| 209 |
+
SEGMENT_INSTR_COUNT 0 10000000
|
| 210 |
+
ENABLE_SWPRF FALSE
|
| 211 |
+
MLC_PRESENT FALSE 1
|
| 212 |
+
MLC_SIZE (512 * 1024) 2097000
|
| 213 |
+
MLC_ASSOC 4 8
|
| 214 |
+
MLC_LINE_SIZE 64
|
| 215 |
+
MLC_CYCLES 12 16
|
| 216 |
+
PERFECT_MLC FALSE
|
| 217 |
+
MLC_READ_PORTS 1
|
| 218 |
+
MLC_WRITE_PORTS 1
|
| 219 |
+
MLC_BANKS 8
|
| 220 |
+
MLC_INTERLEAVE_FACTOR 64
|
| 221 |
+
MLC_CACHE_REPL_POLICY 0
|
| 222 |
+
MLC_WRITE_THROUGH FALSE
|
| 223 |
+
PREFETCH_UPDATE_LRU_MLC TRUE
|
| 224 |
+
FORCE_L1_MISS FALSE
|
| 225 |
+
L1_SIZE (4 * 1024 * 1024) 3145728
|
| 226 |
+
L1_ASSOC 8 16
|
| 227 |
+
L1_LINE_SIZE 64 64
|
| 228 |
+
L1_CYCLES 24 36 // just a guess
|
| 229 |
+
PERFECT_L1 FALSE
|
| 230 |
+
PRIVATE_L1 FALSE
|
| 231 |
+
L1_READ_PORTS 1
|
| 232 |
+
L1_WRITE_PORTS 1
|
| 233 |
+
L1_BANKS 8 8
|
| 234 |
+
L1_INTERLEAVE_FACTOR 64 64
|
| 235 |
+
L1_CACHE_REPL_POLICY 0
|
| 236 |
+
L1_WRITE_THROUGH FALSE
|
| 237 |
+
L1_IGNORE_WB FALSE
|
| 238 |
+
L1_USE_CORE_FREQ FALSE
|
| 239 |
+
MARK_L1_MISSES TRUE
|
| 240 |
+
PREFETCH_UPDATE_LRU_L1 TRUE
|
| 241 |
+
MEMORY_RANDOM_ADDR FALSE
|
| 242 |
+
VA_PAGE_SIZE_BYTES 4096
|
| 243 |
+
NUM_ADDR_NON_SIGN_EXTEND_BITS 48
|
| 244 |
+
ADDR_TRANSLATION 0 random
|
| 245 |
+
CONSTANT_MEMORY_LATENCY FALSE
|
| 246 |
+
MEMORY_CYCLES 100
|
| 247 |
+
STALL_MEM_REQS_ONLY FALSE
|
| 248 |
+
ICACHE_SIZE (64 * 1024) 32768
|
| 249 |
+
ICACHE_ASSOC 4 8
|
| 250 |
+
ICACHE_LINE_SIZE 64 64
|
| 251 |
+
PERFECT_ICACHE FALSE
|
| 252 |
+
ICACHE_READ_PORTS 1
|
| 253 |
+
ICACHE_WRITE_PORTS 1
|
| 254 |
+
ICACHE_BANKS 8
|
| 255 |
+
ICACHE_REPL 0
|
| 256 |
+
UOP_CACHE_ENABLE 1 1
|
| 257 |
+
UOP_CACHE_WIDTH 6 8
|
| 258 |
+
ALWAYS_LOOKUP_ICACHE 0
|
| 259 |
+
UOP_CACHE_INSERT_ONLY_ONPATH FALSE
|
| 260 |
+
UOP_CACHE_READ_PORTS 1
|
| 261 |
+
UOP_CACHE_LINES 384 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 262 |
+
UOP_CACHE_ASSOC 8 8
|
| 263 |
+
UOP_CACHE_MAX_IMM_DISP_LINE 4
|
| 264 |
+
IPRF_ON_UOP_CACHE_HIT FALSE 1
|
| 265 |
+
UOP_CACHE_REPL 0
|
| 266 |
+
PRIORITY_LINE_STICKINESS_PERCENT 50
|
| 267 |
+
PW_PRIORITY_LIST_FILEPATH "pw_priority_list.csv"
|
| 268 |
+
NUM_PRIORITY_PWS 10
|
| 269 |
+
PRIORITIZE_PWS_AFTER_FIRST_STICKY_UNTIL_BACKEND_STALL FALSE
|
| 270 |
+
NO_REPL_AFTER_QUEUE_SIZE 0
|
| 271 |
+
FDIP_UC_SIZE 0
|
| 272 |
+
FDIP_UC_ASSOC 4
|
| 273 |
+
FDIP_UC_INSERT_REPLPOL 0
|
| 274 |
+
MAP_STAGE_CONSUME_FROM_ICACHE_AND_UOC_SAME_CYCLE TRUE
|
| 275 |
+
UOP_QUEUE_LENGTH 7
|
| 276 |
+
DCACHE_SIZE (64 * 1024) 49152
|
| 277 |
+
DCACHE_ASSOC 1 12
|
| 278 |
+
DCACHE_LINE_SIZE 64 64
|
| 279 |
+
DCACHE_CYCLES 2 5
|
| 280 |
+
PERFECT_DCACHE FALSE
|
| 281 |
+
DCACHE_READ_PORTS 8 1
|
| 282 |
+
DCACHE_WRITE_PORTS 1 1
|
| 283 |
+
DCACHE_BANKS 1 8
|
| 284 |
+
DCACHE_INTERLEAVE_FACTOR 4
|
| 285 |
+
DCACHE_REPL 0
|
| 286 |
+
DCACHE_REPL_PREF_THRESH 1
|
| 287 |
+
MEM_OOO_STORES TRUE 1
|
| 288 |
+
MEM_OBEY_STORE_DEP TRUE 1
|
| 289 |
+
PREF_INSERT_LRU FALSE
|
| 290 |
+
PREF_INSERT_MIDDLE FALSE
|
| 291 |
+
PREF_INSERT_LOWQTR FALSE
|
| 292 |
+
PREF_INSERT_DYNACC FALSE
|
| 293 |
+
MEM_REQ_BUFFER_ENTRIES 32 32
|
| 294 |
+
PRIVATE_MSHR_ON TRUE
|
| 295 |
+
MEM_PRIORITY_IFETCH 0 0
|
| 296 |
+
MEM_PRIORITY_DFETCH 0 1
|
| 297 |
+
MEM_PRIORITY_DSTORE 0 2
|
| 298 |
+
MEM_PRIORITY_IPRF 9 3
|
| 299 |
+
MEM_PRIORITY_UOCPRF 9
|
| 300 |
+
MEM_PRIORITY_FDIPPRFON 8
|
| 301 |
+
MEM_PRIORITY_FDIPPRFOFF 9
|
| 302 |
+
MEM_PRIORITY_DPRF 10 4
|
| 303 |
+
MEM_PRIORITY_WB 0 5
|
| 304 |
+
MEM_PRIORITY_WB_NODIRTY 0 5
|
| 305 |
+
PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1
|
| 306 |
+
MEM_REQ_BUFFER_PREF_WATERMARK 0 4
|
| 307 |
+
MEM_REQ_BUFFER_WB_VALVE 2
|
| 308 |
+
MEM_L1_FILL_QUEUE_ENTRIES 32
|
| 309 |
+
MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE
|
| 310 |
+
MEM_MEM_QUEUE_PARTITION_ENABLE FALSE
|
| 311 |
+
MEM_BUS_OUT_QUEUE_AS_FIFO TRUE
|
| 312 |
+
OLDEST_FIRST_TO_MEM_QUEUE TRUE
|
| 313 |
+
ROUND_ROBIN_TO_MEM_QUEUE FALSE
|
| 314 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE FALSE
|
| 315 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0
|
| 316 |
+
L1_CYCLE_TIME 312500
|
| 317 |
+
MLCQ_TO_L1Q_TRANSFER_LATENCY 1
|
| 318 |
+
L1Q_TO_FSB_TRANSFER_LATENCY 1
|
| 319 |
+
PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE
|
| 320 |
+
KICKOUT_PREFETCHES FALSE
|
| 321 |
+
KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE
|
| 322 |
+
KICKOUT_OLDEST_PREFETCH FALSE
|
| 323 |
+
KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE
|
| 324 |
+
ORDER_BEYOND_BUS FALSE 1
|
| 325 |
+
ALL_FIFO_QUEUES FALSE
|
| 326 |
+
QUEUE_MLC_SIZE 0
|
| 327 |
+
QUEUE_L1_SIZE 0
|
| 328 |
+
QUEUE_BUS_OUT_SIZE 0
|
| 329 |
+
QUEUE_CORE_FILL_SIZE 0
|
| 330 |
+
ALLOW_TYPE_MATCHES FALSE
|
| 331 |
+
STREAM_PREFETCH_ON FALSE
|
| 332 |
+
DC_PREF_CACHE_ENABLE FALSE
|
| 333 |
+
DC_PREF_CACHE_CYCLE 0
|
| 334 |
+
PREF_INSERT_DCACHE_IMM TRUE
|
| 335 |
+
DC_PREF_CACHE_SIZE (64 * 1024)
|
| 336 |
+
DC_PREF_CACHE_ASSOC 4
|
| 337 |
+
DC_PREF_ONLY_L1HIT FALSE
|
| 338 |
+
PREF_CACHE_USE_RDY_CYCLE FALSE
|
| 339 |
+
IC_PREF_CACHE_ENABLE FALSE
|
| 340 |
+
IC_PREF_CACHE_SIZE (64 * 1024)
|
| 341 |
+
IC_PREF_CACHE_ASSOC 4
|
| 342 |
+
L1_PREF_CACHE_ENABLE FALSE
|
| 343 |
+
L1_PREF_CACHE_SIZE (1024 * 1024)
|
| 344 |
+
L1_PREF_CACHE_ASSOC 8
|
| 345 |
+
SET_OFF_PATH_CONFIRMED FALSE 1
|
| 346 |
+
USE_CONFIRMED_OFF FALSE
|
| 347 |
+
PREFCACHE_MOVE_OFFPATH FALSE
|
| 348 |
+
CACHE_STAT_ENABLE FALSE
|
| 349 |
+
PREF_DCACHE_HIT_FILL_L1 TRUE
|
| 350 |
+
PREF_ICACHE_HIT_FILL_L1 TRUE
|
| 351 |
+
CRITICAL_ACCESS_PLOT_ENABLE FALSE
|
| 352 |
+
CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat"
|
| 353 |
+
ROUND_ROBIN_TO_L1 FALSE
|
| 354 |
+
PREF_I_TOGETHER FALSE
|
| 355 |
+
ONE_MORE_CACHE_LINE_ENABLE FALSE
|
| 356 |
+
L1_STATIC_PARTITION_ENABLE 0
|
| 357 |
+
L1_STATIC_PARTITION NULL
|
| 358 |
+
L1_DYNAMIC_PARTITION_ENABLE FALSE
|
| 359 |
+
L1_DYNAMIC_PARTITION_POLICY 0
|
| 360 |
+
PARTITION_UMON_DSS_PREF_ENABLE FALSE
|
| 361 |
+
L1_CACHE_HIT_POSITION_COLLECT FALSE
|
| 362 |
+
L1_PART_ON FALSE
|
| 363 |
+
L1_PART_TRIGGER "c:1000000"
|
| 364 |
+
L1_PART_START "t:0"
|
| 365 |
+
L1_PART_WARMUP FALSE
|
| 366 |
+
L1_PART_SHADOW_WARMUP FALSE
|
| 367 |
+
L1_PART_METRIC 0
|
| 368 |
+
L1_PART_SEARCH 0
|
| 369 |
+
L1_PART_USE_STALLING TRUE
|
| 370 |
+
L1_PART_FILL_DELAY 0
|
| 371 |
+
L1_SHADOW_TAGS_MODULO 1
|
| 372 |
+
HIER_MSHR_ON FALSE
|
| 373 |
+
PERF_PRED_ENABLE FALSE
|
| 374 |
+
PERF_PRED_MECH PERF_PRED_CP
|
| 375 |
+
PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY
|
| 376 |
+
PERF_PRED_COUNT_ALL FALSE
|
| 377 |
+
PERF_PRED_COUNT_INST_MISSES TRUE
|
| 378 |
+
PERF_PRED_COUNT_PREFETCHES FALSE
|
| 379 |
+
PERF_PRED_COUNT_OFFPATH_REQS FALSE
|
| 380 |
+
PERF_PRED_COUNT_BW_REQS TRUE
|
| 381 |
+
PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE
|
| 382 |
+
PERF_PRED_SLACK_PERIOD_SIZE 32
|
| 383 |
+
PERF_PRED_REQS_FINISH_AT_FILL FALSE
|
| 384 |
+
PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE
|
| 385 |
+
PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE
|
| 386 |
+
DUMB_MODEL_AVG_REQ_DISTANCE 100
|
| 387 |
+
DUMB_MODEL_RANDOMIZE_DISTANCE FALSE
|
| 388 |
+
DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL
|
| 389 |
+
DUMB_MODEL_AVG_ROW_HITS 1
|
| 390 |
+
DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL
|
| 391 |
+
DUMB_MODEL_MLP 1
|
| 392 |
+
DUMB_MODEL_MLP_PER_CORE NULL
|
| 393 |
+
RAMULATOR_STANDARD "DDR4" DDR4
|
| 394 |
+
RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R
|
| 395 |
+
RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8
|
| 396 |
+
RAMULATOR_CHANNELS 1 1
|
| 397 |
+
RAMULATOR_RANKS 1 1
|
| 398 |
+
RAMULATOR_BANKGROUPS 4 4
|
| 399 |
+
RAMULATOR_BANKS 4 4
|
| 400 |
+
RAMULATOR_CHIP_WIDTH 8 8
|
| 401 |
+
BUS_WIDTH_IN_BYTES 8 8
|
| 402 |
+
RAMULATOR_ROWS 65536 65536
|
| 403 |
+
RAMULATOR_COLS 1024 1024
|
| 404 |
+
RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap
|
| 405 |
+
RAMULATOR_READQ_ENTRIES 32 32
|
| 406 |
+
RAMULATOR_WRITEQ_ENTRIES 32 32
|
| 407 |
+
RAMULATOR_REC_CMD_TRACE "off" FALSE
|
| 408 |
+
RAMULATOR_PRINT_CMD_TRACE "off" FALSE
|
| 409 |
+
RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on"
|
| 410 |
+
RAMULATOR_TCK 833333 833333
|
| 411 |
+
RAMULATOR_TCL 16 16
|
| 412 |
+
RAMULATOR_TCCD 6 6
|
| 413 |
+
RAMULATOR_TCCDS 4 4
|
| 414 |
+
RAMULATOR_TCCDL 6 6
|
| 415 |
+
RAMULATOR_TCWL 12 12
|
| 416 |
+
RAMULATOR_TBL 4 4
|
| 417 |
+
RAMULATOR_TWTR 9 9
|
| 418 |
+
RAMULATOR_TWTRS 3 3
|
| 419 |
+
RAMULATOR_TWTRL 9 9
|
| 420 |
+
RAMULATOR_TRP 16 16
|
| 421 |
+
RAMULATOR_TRPpb 16 16
|
| 422 |
+
RAMULATOR_TRPab 16 16
|
| 423 |
+
RAMULATOR_TRCD 16 16
|
| 424 |
+
RAMULATOR_TRCDR 16 16
|
| 425 |
+
RAMULATOR_TRCDW 16 16
|
| 426 |
+
RAMULATOR_TRAS 39 39
|
| 427 |
+
DRAM_TECH_IN_NM 32 32
|
| 428 |
+
DVFS_ON FALSE
|
| 429 |
+
DVFS_METRIC DVFS_METRIC_NUM_ELEMS
|
| 430 |
+
DVFS_CONFIGS NULL
|
| 431 |
+
DVFS_CONFIG_FILE NULL
|
| 432 |
+
DVFS_START "t:0"
|
| 433 |
+
DVFS_PERIOD "t:312500000000"
|
| 434 |
+
DVFS_LOG TRUE
|
| 435 |
+
DVFS_INDIVIDUAL_CORES FALSE
|
| 436 |
+
DVFS_CHIP_LEVEL FALSE
|
| 437 |
+
DVFS_STATIC NULL
|
| 438 |
+
DVFS_FORCE_CONFIG NULL
|
| 439 |
+
DVFS_REPLAY_CONFIG_TRACE NULL
|
| 440 |
+
DVFS_USE_ORACLE FALSE
|
| 441 |
+
DVFS_USE_BW_SHARING FALSE
|
| 442 |
+
DVFS_USE_DRAM_SHARING FALSE
|
| 443 |
+
DVFS_USE_STALL_TIME FALSE
|
| 444 |
+
DVFS_DRAM_SHARING_SOLVER_BIN NULL
|
| 445 |
+
DVFS_DRAM_SHARING_SOLVER_STRICT TRUE
|
| 446 |
+
DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95
|
| 447 |
+
DVFS_BW_SHARING_MAX_REQS 28.0
|
| 448 |
+
DVFS_BW_SHARING_MAX_RW_COST 0.25
|
| 449 |
+
DVFS_BW_SHARING_NO_PREF_STALL TRUE
|
| 450 |
+
DVFS_BW_SHARING_CRIT_STATS TRUE
|
| 451 |
+
DVFS_COUNT_L1_ACCESS_STALL FALSE
|
| 452 |
+
NUM_CORES 1
|
| 453 |
+
CHIP_CYCLE_TIME 312500 312500
|
| 454 |
+
CORE_0_CYCLE_TIME 312500
|
| 455 |
+
CORE_1_CYCLE_TIME 312500
|
| 456 |
+
CORE_2_CYCLE_TIME 312500
|
| 457 |
+
CORE_3_CYCLE_TIME 312500
|
| 458 |
+
CORE_4_CYCLE_TIME 312500
|
| 459 |
+
CORE_5_CYCLE_TIME 312500
|
| 460 |
+
CORE_6_CYCLE_TIME 312500
|
| 461 |
+
CORE_7_CYCLE_TIME 312500
|
| 462 |
+
CORE_8_CYCLE_TIME 312500
|
| 463 |
+
CORE_9_CYCLE_TIME 312500
|
| 464 |
+
CORE_10_CYCLE_TIME 312500
|
| 465 |
+
CORE_11_CYCLE_TIME 312500
|
| 466 |
+
CORE_12_CYCLE_TIME 312500
|
| 467 |
+
CORE_13_CYCLE_TIME 312500
|
| 468 |
+
CORE_14_CYCLE_TIME 312500
|
| 469 |
+
CORE_15_CYCLE_TIME 312500
|
| 470 |
+
CORE_16_CYCLE_TIME 312500
|
| 471 |
+
CORE_17_CYCLE_TIME 312500
|
| 472 |
+
CORE_18_CYCLE_TIME 312500
|
| 473 |
+
CORE_19_CYCLE_TIME 312500
|
| 474 |
+
CORE_20_CYCLE_TIME 312500
|
| 475 |
+
CORE_21_CYCLE_TIME 312500
|
| 476 |
+
CORE_22_CYCLE_TIME 312500
|
| 477 |
+
CORE_23_CYCLE_TIME 312500
|
| 478 |
+
CORE_24_CYCLE_TIME 312500
|
| 479 |
+
CORE_25_CYCLE_TIME 312500
|
| 480 |
+
CORE_26_CYCLE_TIME 312500
|
| 481 |
+
CORE_27_CYCLE_TIME 312500
|
| 482 |
+
CORE_28_CYCLE_TIME 312500
|
| 483 |
+
CORE_29_CYCLE_TIME 312500
|
| 484 |
+
CORE_30_CYCLE_TIME 312500
|
| 485 |
+
CORE_31_CYCLE_TIME 312500
|
| 486 |
+
CORE_32_CYCLE_TIME 312500
|
| 487 |
+
CORE_33_CYCLE_TIME 312500
|
| 488 |
+
CORE_34_CYCLE_TIME 312500
|
| 489 |
+
CORE_35_CYCLE_TIME 312500
|
| 490 |
+
CORE_36_CYCLE_TIME 312500
|
| 491 |
+
CORE_37_CYCLE_TIME 312500
|
| 492 |
+
CORE_38_CYCLE_TIME 312500
|
| 493 |
+
CORE_39_CYCLE_TIME 312500
|
| 494 |
+
CORE_40_CYCLE_TIME 312500
|
| 495 |
+
CORE_41_CYCLE_TIME 312500
|
| 496 |
+
CORE_42_CYCLE_TIME 312500
|
| 497 |
+
CORE_43_CYCLE_TIME 312500
|
| 498 |
+
CORE_44_CYCLE_TIME 312500
|
| 499 |
+
CORE_45_CYCLE_TIME 312500
|
| 500 |
+
CORE_46_CYCLE_TIME 312500
|
| 501 |
+
CORE_47_CYCLE_TIME 312500
|
| 502 |
+
CORE_48_CYCLE_TIME 312500
|
| 503 |
+
CORE_49_CYCLE_TIME 312500
|
| 504 |
+
CORE_50_CYCLE_TIME 312500
|
| 505 |
+
CORE_51_CYCLE_TIME 312500
|
| 506 |
+
CORE_52_CYCLE_TIME 312500
|
| 507 |
+
CORE_53_CYCLE_TIME 312500
|
| 508 |
+
CORE_54_CYCLE_TIME 312500
|
| 509 |
+
CORE_55_CYCLE_TIME 312500
|
| 510 |
+
CORE_56_CYCLE_TIME 312500
|
| 511 |
+
CORE_57_CYCLE_TIME 312500
|
| 512 |
+
CORE_58_CYCLE_TIME 312500
|
| 513 |
+
CORE_59_CYCLE_TIME 312500
|
| 514 |
+
CORE_60_CYCLE_TIME 312500
|
| 515 |
+
CORE_61_CYCLE_TIME 312500
|
| 516 |
+
CORE_62_CYCLE_TIME 312500
|
| 517 |
+
CORE_63_CYCLE_TIME 312500
|
| 518 |
+
TOPDOWN_FU_EXEC_FEW 0
|
| 519 |
+
ISSUE_WIDTH 4 6
|
| 520 |
+
RS_FILL_WIDTH 8 0
|
| 521 |
+
NODE_TABLE_SIZE 256 512
|
| 522 |
+
NODE_RET_WIDTH 4 8
|
| 523 |
+
NODE_RETIRE_RATE 10
|
| 524 |
+
DECODE_WIDTH 4 6
|
| 525 |
+
IDQ_SIZE 140 144
|
| 526 |
+
REG_RENAMING_SCHEME 0 1
|
| 527 |
+
REG_TABLE_INTEGER_PHYSICAL_SIZE 256 280
|
| 528 |
+
REG_TABLE_VECTOR_PHYSICAL_SIZE 256 332
|
| 529 |
+
REG_TABLE_INTEGER_VIRTUAL_SIZE 256
|
| 530 |
+
REG_TABLE_VECTOR_VIRTUAL_SIZE 256
|
| 531 |
+
REG_RENAMING_MOVE_ELIMINATE FALSE
|
| 532 |
+
NODE_ISSUE_QUEUE_DISPATCH_SCHEME 0
|
| 533 |
+
NODE_ISSUE_QUEUE_SCHEDULE_SCHEME 0
|
| 534 |
+
ISSUE_QUEUE_PARALLEL_PICK FALSE
|
| 535 |
+
RS_SIZES "256" 97 70 19
|
| 536 |
+
RS_CONNECTIONS "xF" b0100110011 b1000001100 b0011000000
|
| 537 |
+
FU_TYPES "0, 0, 0, 0" b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 538 |
+
LSQ_ENABLE TRUE
|
| 539 |
+
LOAD_QUEUE_ENTRY_NUM 128
|
| 540 |
+
STORE_QUEUE_ENTRY_NUM 72
|
| 541 |
+
DECODE_CYCLES 1 5
|
| 542 |
+
MAP_CYCLES 1 5
|
| 543 |
+
ICACHE_LATENCY 3
|
| 544 |
+
EXTRA_REDIRECT_CYCLES 0
|
| 545 |
+
EXTRA_RECOVERY_CYCLES 0
|
| 546 |
+
EXTRA_CALLSYS_CYCLES 20 const
|
| 547 |
+
DIE_ON_CALLSYS FALSE
|
| 548 |
+
DIE_ON_RET_STALL_THRESH 0
|
| 549 |
+
DIE_ON_RET_STALL_CORE 0
|
| 550 |
+
DIE_ON_MEM_BLOCK_THRESH 0
|
| 551 |
+
DIE_ON_MEM_BLOCK_CORE 0
|
| 552 |
+
ICACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 553 |
+
UOP_CACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 554 |
+
FETCH_OFF_PATH_OPS TRUE 1
|
| 555 |
+
WP_COLLECT_STATS TRUE
|
| 556 |
+
OP_INV_DELAY 1
|
| 557 |
+
OP_NOP_DELAY 1
|
| 558 |
+
OP_CF_DELAY 1
|
| 559 |
+
OP_MOV_DELAY 1
|
| 560 |
+
OP_CMOV_DELAY 1
|
| 561 |
+
OP_LDA_DELAY 1
|
| 562 |
+
OP_ILD_DELAY 1
|
| 563 |
+
OP_IST_DELAY 1
|
| 564 |
+
OP_IADD_DELAY 1
|
| 565 |
+
OP_IMUL_DELAY 3
|
| 566 |
+
OP_IDIV_DELAY -20
|
| 567 |
+
OP_ICMP_DELAY 1
|
| 568 |
+
OP_LOGIC_DELAY 1
|
| 569 |
+
OP_SHIFT_DELAY 1
|
| 570 |
+
OP_FLD_DELAY 1
|
| 571 |
+
OP_FST_DELAY 1
|
| 572 |
+
OP_FCVT_DELAY 3
|
| 573 |
+
OP_FADD_DELAY 3
|
| 574 |
+
OP_FMUL_DELAY 5
|
| 575 |
+
OP_FMA_DELAY 5
|
| 576 |
+
OP_FDIV_DELAY -20
|
| 577 |
+
OP_FCMP_DELAY 3
|
| 578 |
+
OP_FCMOV_DELAY 1
|
| 579 |
+
OP_GATHER_DELAY 12
|
| 580 |
+
OP_SCATTER_DELAY 18
|
| 581 |
+
OP_PIPELINED_FAST_DELAY 2
|
| 582 |
+
OP_PIPELINED_MEDIUM_DELAY 5
|
| 583 |
+
OP_PIPELINED_SLOW_DELAY 10
|
| 584 |
+
OP_NOTPIPELINED_MEDIUM_DELAY -5
|
| 585 |
+
OP_NOTPIPELINED_SLOW_DELAY -20
|
| 586 |
+
OP_NOTPIPELINED_VERY_SLOW_DELAY -100
|
| 587 |
+
UNIFORM_OP_DELAY 0
|
| 588 |
+
STALL_ON_WAIT_MEM TRUE
|
| 589 |
+
STORES_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 590 |
+
PREFS_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 591 |
+
OBEY_REG_DEP TRUE
|
| 592 |
+
TRACK_L1_MISS_DEPS FALSE
|
| 593 |
+
CBP_TRACE_R0 NULL /dev/shm/baseline/traces/.staging/sssp_facebook-193424/raw_trace/drmemtrace.sssp.193437.5690.dir/trace/drmemtrace.sssp.193437.7866.trace.zip
|
| 594 |
+
CBP_TRACE_R1 NULL
|
| 595 |
+
CBP_TRACE_R2 NULL
|
| 596 |
+
CBP_TRACE_R3 NULL
|
| 597 |
+
CBP_TRACE_R4 NULL
|
| 598 |
+
CBP_TRACE_R5 NULL
|
| 599 |
+
CBP_TRACE_R6 NULL
|
| 600 |
+
CBP_TRACE_R7 NULL
|
| 601 |
+
CBP_TRACE_R8 NULL
|
| 602 |
+
CBP_TRACE_R9 NULL
|
| 603 |
+
CBP_TRACE_R10 NULL
|
| 604 |
+
CBP_TRACE_R11 NULL
|
| 605 |
+
CBP_TRACE_R12 NULL
|
| 606 |
+
CBP_TRACE_R13 NULL
|
| 607 |
+
CBP_TRACE_R14 NULL
|
| 608 |
+
CBP_TRACE_R15 NULL
|
| 609 |
+
CBP_TRACE_R16 NULL
|
| 610 |
+
CBP_TRACE_R17 NULL
|
| 611 |
+
CBP_TRACE_R18 NULL
|
| 612 |
+
CBP_TRACE_R19 NULL
|
| 613 |
+
CBP_TRACE_R20 NULL
|
| 614 |
+
CBP_TRACE_R21 NULL
|
| 615 |
+
CBP_TRACE_R22 NULL
|
| 616 |
+
CBP_TRACE_R23 NULL
|
| 617 |
+
CBP_TRACE_R24 NULL
|
| 618 |
+
CBP_TRACE_R25 NULL
|
| 619 |
+
CBP_TRACE_R26 NULL
|
| 620 |
+
CBP_TRACE_R27 NULL
|
| 621 |
+
CBP_TRACE_R28 NULL
|
| 622 |
+
CBP_TRACE_R29 NULL
|
| 623 |
+
CBP_TRACE_R30 NULL
|
| 624 |
+
CBP_TRACE_R31 NULL
|
| 625 |
+
CBP_TRACE_R32 NULL
|
| 626 |
+
CBP_TRACE_R33 NULL
|
| 627 |
+
CBP_TRACE_R34 NULL
|
| 628 |
+
CBP_TRACE_R35 NULL
|
| 629 |
+
CBP_TRACE_R36 NULL
|
| 630 |
+
CBP_TRACE_R37 NULL
|
| 631 |
+
CBP_TRACE_R38 NULL
|
| 632 |
+
CBP_TRACE_R39 NULL
|
| 633 |
+
CBP_TRACE_R40 NULL
|
| 634 |
+
CBP_TRACE_R41 NULL
|
| 635 |
+
CBP_TRACE_R42 NULL
|
| 636 |
+
CBP_TRACE_R43 NULL
|
| 637 |
+
CBP_TRACE_R44 NULL
|
| 638 |
+
CBP_TRACE_R45 NULL
|
| 639 |
+
CBP_TRACE_R46 NULL
|
| 640 |
+
CBP_TRACE_R47 NULL
|
| 641 |
+
CBP_TRACE_R48 NULL
|
| 642 |
+
CBP_TRACE_R49 NULL
|
| 643 |
+
CBP_TRACE_R50 NULL
|
| 644 |
+
CBP_TRACE_R51 NULL
|
| 645 |
+
CBP_TRACE_R52 NULL
|
| 646 |
+
CBP_TRACE_R53 NULL
|
| 647 |
+
CBP_TRACE_R54 NULL
|
| 648 |
+
CBP_TRACE_R55 NULL
|
| 649 |
+
CBP_TRACE_R56 NULL
|
| 650 |
+
CBP_TRACE_R57 NULL
|
| 651 |
+
CBP_TRACE_R58 NULL
|
| 652 |
+
CBP_TRACE_R59 NULL
|
| 653 |
+
CBP_TRACE_R60 NULL
|
| 654 |
+
CBP_TRACE_R61 NULL
|
| 655 |
+
CBP_TRACE_R62 NULL
|
| 656 |
+
CBP_TRACE_R63 NULL
|
| 657 |
+
FE_FTQ_BLOCK_NUM 32
|
| 658 |
+
FE_FTQ_TAKEN_CFS_PER_CYCLE 2
|
| 659 |
+
FE_FTQ_FT_PER_CYCLE 1
|
| 660 |
+
DUMB_CORE_ON FALSE
|
| 661 |
+
DUMB_CORE 1
|
| 662 |
+
DCACHE_MISS_RATE 10
|
| 663 |
+
L1_MISS_RATE 10
|
| 664 |
+
TRACE_BUF_SIZE 0
|
| 665 |
+
PERFECT_CONFIDENCE FALSE
|
| 666 |
+
CONFIDENCE_ENABLE FALSE
|
| 667 |
+
CONFIDENCE_MECH 0
|
| 668 |
+
CONF_OFF_PATH_THRESHOLD 15
|
| 669 |
+
CONF_OFF_PATH_INC 5
|
| 670 |
+
CONF_BTB_MISS_BP_TAKEN FALSE
|
| 671 |
+
CONF_IPC_RATE_CONF FALSE
|
| 672 |
+
CONF_BTB_MISS_BP_TAKEN_THRESHOLD 0
|
| 673 |
+
CONF_BTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 674 |
+
CONF_IBTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 675 |
+
CONF_MISFETCH_RATE_CYCLES_THRESHOLD 1.0
|
| 676 |
+
CONF_MISPRED_RATE_CYCLES_THRESHOLD 1.0
|
| 677 |
+
CONF_BTB_MISS_SAMPLE_RATE 100000
|
| 678 |
+
CONF_IBTB_MISS_SAMPLE_RATE 100000
|
| 679 |
+
CONF_MISFETCH_SAMPLE_RATE 100000
|
| 680 |
+
CONF_MISPRED_SAMPLE_RATE 100000
|
| 681 |
+
CONF_IPC_SAMPLE_RATE 100000
|
| 682 |
+
CONF_BTB_MISS_RATE_WEIGHT 200
|
| 683 |
+
CONF_BTB_MISS_BP_TAKEN_CONF TRUE
|
| 684 |
+
CONF_IBTB_MISS_BP_TAKEN_CONF TRUE
|
| 685 |
+
CONF_BTB_MISS_RATE_CONF TRUE
|
| 686 |
+
CONF_IBTB_MISS_RATE_CONF TRUE
|
| 687 |
+
CONF_MISFETCH_RATE_CONF TRUE
|
| 688 |
+
CONF_MISPRED_RATE_CONF TRUE
|
| 689 |
+
CONF_INV_BP_CONF TRUE
|
| 690 |
+
CONF_PERFECT_BTB_MISS_CONF FALSE
|
| 691 |
+
CONF_PERFECT_IBTB_MISS_CONF FALSE
|
| 692 |
+
CONF_PERFECT_MISFETCH_CONF FALSE
|
| 693 |
+
CONF_PERFECT_MISPRED_CONF FALSE
|
| 694 |
+
CONF_LOG_DFE_TO_REC FALSE
|
| 695 |
+
CONF_LOG_PHASE_CYCLES FALSE
|
| 696 |
+
NUM_BPS 1
|
| 697 |
+
DFE0_TRIGGER_POLICY 0
|
| 698 |
+
DFE1_TRIGGER_POLICY 1
|
| 699 |
+
DFE2_TRIGGER_POLICY 1
|
| 700 |
+
DFE3_TRIGGER_POLICY 1
|
| 701 |
+
DFE4_TRIGGER_POLICY 1
|
| 702 |
+
DFE0_STOP_POLICY 0
|
| 703 |
+
DFE1_STOP_POLICY 1
|
| 704 |
+
DFE2_STOP_POLICY 1
|
| 705 |
+
DFE3_STOP_POLICY 1
|
| 706 |
+
DFE4_STOP_POLICY 1
|
| 707 |
+
LOOKAHEAD_BUF_SIZE 0
|
| 708 |
+
DEBUG_CYCLE_START 0 0
|
| 709 |
+
DEBUG_CYCLE_STOP 0 -1
|
| 710 |
+
DEBUG_TIME_START 0
|
| 711 |
+
DEBUG_TIME_STOP 0
|
| 712 |
+
DEBUG_INST_START 0 0
|
| 713 |
+
DEBUG_INST_STOP 0 -1
|
| 714 |
+
DEBUG_OP_START 0
|
| 715 |
+
DEBUG_OP_STOP 0
|
| 716 |
+
DEBUG_CACHE_LIB FALSE
|
| 717 |
+
DEBUG_HASH_LIB FALSE
|
| 718 |
+
DEBUG_LIST_LIB FALSE
|
| 719 |
+
DEBUG_PORT_LIB FALSE
|
| 720 |
+
DEBUG_BUS_LIB FALSE
|
| 721 |
+
DEBUG_OP_POOL FALSE
|
| 722 |
+
DEBUG_ORACLE FALSE
|
| 723 |
+
DEBUG_FRONTEND FALSE
|
| 724 |
+
DEBUG_ADDR_TRANS FALSE
|
| 725 |
+
DEBUG_BP FALSE
|
| 726 |
+
DEBUG_BP_DIR FALSE
|
| 727 |
+
DEBUG_BTB FALSE
|
| 728 |
+
DEBUG_CRS FALSE
|
| 729 |
+
DEBUG_MAP FALSE
|
| 730 |
+
DEBUG_MEMORY FALSE
|
| 731 |
+
DEBUG_REPLAY FALSE
|
| 732 |
+
DEBUG_FREQ FALSE
|
| 733 |
+
DEBUG_MODEL FALSE
|
| 734 |
+
DEBUG_THREAD FALSE
|
| 735 |
+
DEBUG_DECOUPLED_FE FALSE
|
| 736 |
+
DEBUG_CONF FALSE
|
| 737 |
+
DEBUG_ICACHE_STAGE FALSE
|
| 738 |
+
DEBUG_DECODE_STAGE FALSE
|
| 739 |
+
DEBUG_CPP_CACHE FALSE
|
| 740 |
+
DEBUG_UOP_CACHE FALSE
|
| 741 |
+
DEBUG_UOP_QUEUE_STAGE FALSE
|
| 742 |
+
DEBUG_IDQ_STAGE FALSE
|
| 743 |
+
DEBUG_MAP_STAGE FALSE
|
| 744 |
+
DEBUG_NODE_STAGE FALSE
|
| 745 |
+
DEBUG_EXEC_STAGE FALSE
|
| 746 |
+
DEBUG_DCACHE_STAGE FALSE
|
| 747 |
+
DEBUG_RETIRED_UOPS FALSE
|
| 748 |
+
DEBUG_EXC_INSERTS FALSE
|
| 749 |
+
DEBUG_BP_CONF FALSE
|
| 750 |
+
DEBUG_ONPATH_CONF FALSE
|
| 751 |
+
DEBUG_STREAM FALSE
|
| 752 |
+
DEBUG_STREAM_MEM FALSE
|
| 753 |
+
DEBUG_WAY FALSE
|
| 754 |
+
DEBUG_L2MARKV FALSE
|
| 755 |
+
DEBUG_L2L1PREF FALSE
|
| 756 |
+
DEBUG_PERF_PRED FALSE
|
| 757 |
+
DEBUG_POWER_UTILS FALSE
|
| 758 |
+
DEBUG_DVFS FALSE
|
| 759 |
+
DEBUG_TRACE_READ FALSE
|
| 760 |
+
DEBUG_INST_FIELDS FALSE
|
| 761 |
+
DEBUG_OP_FIELDS FALSE
|
| 762 |
+
DEBUG_PIN_EXEC_DRIVEN FALSE
|
| 763 |
+
DEBUG_CACHE_PART FALSE
|
| 764 |
+
DEBUG_OPTIMIZER2 FALSE
|
| 765 |
+
DEBUG_PREF FALSE
|
| 766 |
+
DEBUG_FDIP FALSE
|
| 767 |
+
DEBUG_EIP FALSE
|
| 768 |
+
DEBUG_DJOLT FALSE
|
| 769 |
+
DEBUG_FNLMMA FALSE
|
| 770 |
+
PERFECT_BP FALSE
|
| 771 |
+
PERFECT_BTB FALSE
|
| 772 |
+
PERFECT_IBP FALSE
|
| 773 |
+
PERFECT_CRS FALSE
|
| 774 |
+
PERFECT_CBR_BTB FALSE
|
| 775 |
+
PERFECT_NT_BTB FALSE 0 # deprecated, effectively always true.
|
| 776 |
+
CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle
|
| 777 |
+
UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 778 |
+
BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec.
|
| 779 |
+
BP_MECH TAGE64K_BP tage64k
|
| 780 |
+
BP_MECH_L0 BIMODAL_BP
|
| 781 |
+
BP_L0_LATENCY 1
|
| 782 |
+
BP_MAIN_LATENCY 3
|
| 783 |
+
BIMODAL_ENTRIES (4 * 1024)
|
| 784 |
+
HIST_LENGTH 16
|
| 785 |
+
PHT_CTR_BITS 2 const
|
| 786 |
+
BHT_ENTRIES (4 * 1024)
|
| 787 |
+
BHT_ASSOC 4
|
| 788 |
+
HYBRIDS_INDEX_LENGTH 16
|
| 789 |
+
HYBRIDG_HIST_LENGTH 16
|
| 790 |
+
HYBRIDP_HIST_LENGTH 16
|
| 791 |
+
FILTER_INDEX_LENGTH 16
|
| 792 |
+
USE_FILTER FALSE
|
| 793 |
+
INF_HYBRIDGP FALSE
|
| 794 |
+
BP_HASH_TOS FALSE
|
| 795 |
+
IBTB_HASH_TOS FALSE
|
| 796 |
+
BTB_MECH GENERIC_BTB generic
|
| 797 |
+
BTB_ENTRIES 12288 12288
|
| 798 |
+
BTB_ASSOC 4 4
|
| 799 |
+
BTB_NUM_BRSLOT 1
|
| 800 |
+
BTB_BLOCK_SIZE 64
|
| 801 |
+
BTB_OFF_PATH_WRITES TRUE 1
|
| 802 |
+
BTB_MAIN_LATENCY 3 3
|
| 803 |
+
BTB_L0_PRESENT FALSE 1
|
| 804 |
+
BTB_L0_ENTRIES 128 128
|
| 805 |
+
BTB_L0_ASSOC 4 4
|
| 806 |
+
BTB_L0_LATENCY 1 1
|
| 807 |
+
BTB_L1_PRESENT FALSE 1
|
| 808 |
+
BTB_L1_ENTRIES 6144 6144
|
| 809 |
+
BTB_L1_ASSOC 4 4
|
| 810 |
+
BTB_L1_LATENCY 2 2
|
| 811 |
+
ENABLE_CRS TRUE 1
|
| 812 |
+
CRS_ENTRIES 32 128
|
| 813 |
+
CRS_REALISTIC 0 1
|
| 814 |
+
ENABLE_IBP TRUE 1 # Enable the indirect branch predictor
|
| 815 |
+
USE_PAT_HIST TRUE
|
| 816 |
+
IBTB_MECH 1 tc_tagged
|
| 817 |
+
IBTB_HIST_LENGTH 16
|
| 818 |
+
IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb.
|
| 819 |
+
TARGETS_IN_HIST 4
|
| 820 |
+
TC_ENTRIES (4 * 1024) 4096
|
| 821 |
+
TC_ASSOC 4 4
|
| 822 |
+
NUM_CORR_BRANCHES 3
|
| 823 |
+
SEL_HIST_BP_ENTRIES 8192
|
| 824 |
+
SEL_HIST_LENGTH 16
|
| 825 |
+
SEL_HIST_DYN_CNT_TH 16
|
| 826 |
+
SEL_HIST_MISPRED_TH 4
|
| 827 |
+
ENABLE_BP_CONF FALSE
|
| 828 |
+
CONF_MECH 0
|
| 829 |
+
PERF_BP_CONF_PRED FALSE
|
| 830 |
+
BPC_BITS 16
|
| 831 |
+
BPC_MECH 1
|
| 832 |
+
BPC_CTR_RESET TRUE
|
| 833 |
+
BPC_CIT_BITS 8
|
| 834 |
+
BPC_CIT_TH 50
|
| 835 |
+
BPC_CTR_BITS 3
|
| 836 |
+
OPC_COUNT_ZEROS FALSE
|
| 837 |
+
OPC_COUNT_THRESH 10
|
| 838 |
+
INF_LOOP FALSE
|
| 839 |
+
INF_LOOP_BUCKETS 811
|
| 840 |
+
LOOP_ENTRIES (4 * 1024)
|
| 841 |
+
LOOP_ASSOC 4
|
| 842 |
+
LOOP_COUNT_MAX 127
|
| 843 |
+
LOOP_REPEAT_MAX 15
|
| 844 |
+
KNOB_PRINT_BRINFO FALSE
|
| 845 |
+
BR_MISPRED_FILE NULL
|
| 846 |
+
SPEC_LEVEL 3
|
| 847 |
+
RANDOM_DETERMINISTIC TRUE
|
| 848 |
+
TAGESCL64KB_SC TRUE
|
| 849 |
+
TAGESCL64KB_LOOP TRUE
|
| 850 |
+
TAGESCL64KB_ALT TRUE
|
| 851 |
+
CONF_PERCEPTRON_TH 0
|
| 852 |
+
CONF_PERCEPTRON_CTR_BITS 8
|
| 853 |
+
CONF_PERCEPTRON_ENTRIES 127
|
| 854 |
+
CONF_PERCEPTRON_THRESH_OVRD 0
|
| 855 |
+
CONF_HIST_LENGTH 32
|
| 856 |
+
PERCEPTRON_CONF_USE_CONF FALSE
|
| 857 |
+
PERCEPTRON_CONF_TRAIN_HIS FALSE
|
| 858 |
+
PERCEPTRON_CONF_TRAIN_CONF FALSE
|
| 859 |
+
PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE
|
| 860 |
+
PERCEPTRON_TRAIN_MISP_FACTOR 1
|
| 861 |
+
PERCEPTRON_TRAIN_CORR_FACTOR 1
|
| 862 |
+
PERCEPTRON_CONF_HIS_BOTH FALSE
|
| 863 |
+
PERCEPTRON_CONF_HIS_BOTH_LENGTH 4
|
| 864 |
+
MTAGE_REALISTIC_SC_40K FALSE
|
| 865 |
+
MTAGE_REALISTIC_SC_100K FALSE
|
| 866 |
+
H2P_TABLE_BUCKETS 16384
|
| 867 |
+
H2P_MIN_EXEC 5000
|
| 868 |
+
H2P_MIN_MISPRED 333
|
| 869 |
+
H2P_MISPRED_RATIO_PERMIL 10
|
| 870 |
+
H2P_TRACK_CBR TRUE
|
| 871 |
+
H2P_TRACK_REP TRUE
|
| 872 |
+
H2P_TRACK_CALL FALSE
|
| 873 |
+
H2P_TRACK_IBR FALSE
|
| 874 |
+
H2P_TRACK_ICALL FALSE
|
| 875 |
+
H2P_TRACK_RET FALSE
|
| 876 |
+
POWER_INTF_ON FALSE
|
| 877 |
+
POWER_INTF_ENABLE_SCALING FALSE
|
| 878 |
+
POWER_INTF_EXEC "power/power_intf.py"
|
| 879 |
+
POWER_INTF_REF_CHIP_TECH_NM 22
|
| 880 |
+
POWER_INTF_REF_CHIP_FREQ (3.2e9)
|
| 881 |
+
POWER_INTF_REF_MEMORY_FREQ (0.8e9)
|
| 882 |
+
POWER_OTHER (0.0)
|
| 883 |
+
PREF_STREAM_ON FALSE 1
|
| 884 |
+
PREF_STREAM_PER_CORE_ENABLE FALSE
|
| 885 |
+
STREAM_BUFFER_N 16
|
| 886 |
+
STREAM_PREFETCH_N 2 4
|
| 887 |
+
STREAM_START_DIS 5 1
|
| 888 |
+
STREAM_LENGTH 16 64
|
| 889 |
+
STREAM_FULL_N 1
|
| 890 |
+
STREAM_TRAIN_LENGTH 16
|
| 891 |
+
STREAM_TRAIN_NUM 1 4
|
| 892 |
+
PREF_ACC_USE_CACHE FALSE
|
| 893 |
+
STREAM_STALL_ON_QUEUE_FULL FALSE
|
| 894 |
+
PREF_SCHEDULE_NUM 4
|
| 895 |
+
TRAIN_FILTER_SIZE 32
|
| 896 |
+
PREF_REQ_Q_SIZE 64
|
| 897 |
+
STREAM_CREATE_ON_DC_MISS FALSE 0
|
| 898 |
+
STREAM_CREATE_ON_L1_MISS TRUE 1
|
| 899 |
+
STREAM_TRAIN_ON_WRONGPATH TRUE
|
| 900 |
+
STREAM_CREATE_ON_WRONGPATH TRUE
|
| 901 |
+
STREAM_PREF_INTO_DCACHE FALSE
|
| 902 |
+
REMOVE_REDUNDANT_STREAM FALSE
|
| 903 |
+
L2HIT_STREAM_SCHEDULE_NUM 4
|
| 904 |
+
PREF_REQ_QUEUE_FILTER_ON FALSE
|
| 905 |
+
HW_PREF_HIT_TRAIN_STREAM FALSE
|
| 906 |
+
L2HIT_STREAM_BUFFER_N 32
|
| 907 |
+
L2HIT_STREAM_PREFETCH_N 2
|
| 908 |
+
L2HIT_STREAM_START_DIS 2
|
| 909 |
+
L2HIT_STREAM_LENGTH 8
|
| 910 |
+
L2HIT_PREF_REQ_Q_SIZE 128
|
| 911 |
+
L2HIT_L2ACCESS_REQ_Q_SIZE 64
|
| 912 |
+
PREF_STREAM_ACCPERSTREAM FALSE
|
| 913 |
+
PREF_ACC_DISTANCE_10 128
|
| 914 |
+
PREF_FRAMEWORK_ON FALSE 1
|
| 915 |
+
PREF_TRACE_ON FALSE
|
| 916 |
+
PREF_UMLC_ON FALSE
|
| 917 |
+
PREF_UL1_ON TRUE
|
| 918 |
+
PREF_DL0REQ_QUEUE_SIZE 32
|
| 919 |
+
PREF_UMLC_REQ_QUEUE_SIZE 64
|
| 920 |
+
PREF_UL1REQ_QUEUE_SIZE 128
|
| 921 |
+
PREF_SHARED_QUEUES TRUE
|
| 922 |
+
PREF_DL0_MISS_ON TRUE
|
| 923 |
+
PREF_DL0_HIT_ON TRUE
|
| 924 |
+
PREF_DL0REQ_QUEUE_FILTER_ON TRUE
|
| 925 |
+
PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE
|
| 926 |
+
PREF_UL1REQ_QUEUE_FILTER_ON TRUE
|
| 927 |
+
PREF_DL0REQ_ADD_FILTER_ON TRUE
|
| 928 |
+
PREF_UMLC_REQ_ADD_FILTER_ON TRUE
|
| 929 |
+
PREF_UL1REQ_ADD_FILTER_ON TRUE
|
| 930 |
+
PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 931 |
+
PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 932 |
+
PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1
|
| 933 |
+
PREF_DL0SCHEDULE_NUM 4
|
| 934 |
+
PREF_UMLC_SCHEDULE_NUM 4
|
| 935 |
+
PREF_UL1SCHEDULE_NUM 4
|
| 936 |
+
PREF_L1Q_DEMAND_RESERVE 0
|
| 937 |
+
PREF_REPORT_PREF_MATCH_AS_MISS FALSE
|
| 938 |
+
PREF_REPORT_PREF_MATCH_AS_HIT TRUE
|
| 939 |
+
PREF_UPDATE_ON_WRONGPATH TRUE
|
| 940 |
+
PREF_TRAIN_ON_PREF_MISSES FALSE 0
|
| 941 |
+
PREF_ORACLE_TRAIN_ON FALSE 0
|
| 942 |
+
PREF_REQ_DROP FALSE
|
| 943 |
+
PREF_THROTTLE_ON FALSE
|
| 944 |
+
PREF_THROTTLEFB_ON FALSE 1
|
| 945 |
+
PREF_ACC_THRESH_1 0.90 0.75
|
| 946 |
+
PREF_ACC_THRESH_2 0.70 0.4
|
| 947 |
+
PREF_ACC_THRESH_3 0.60 0.4
|
| 948 |
+
PREF_ACC_THRESH_4 0.40
|
| 949 |
+
PREF_UPDATE_INTERVAL 0 8192
|
| 950 |
+
PREF_ANALYZE_LOAD FALSE
|
| 951 |
+
PREF_POL_THRESH_1 0.25
|
| 952 |
+
PREF_POL_THRESH_2 0.10
|
| 953 |
+
PREF_POLBV_ON FALSE
|
| 954 |
+
PREF_POLBV_SIZE 1024
|
| 955 |
+
PREF_TIMELY_THRESH 0.05 0.01
|
| 956 |
+
PREF_POLPF_THRESH 0.01 0.005
|
| 957 |
+
PREF_DEGFB_USEONLYACC FALSE
|
| 958 |
+
PREF_DEGFB_USEONLYPOL FALSE
|
| 959 |
+
PREF_DEGFB_USEONLYLATE FALSE
|
| 960 |
+
PREF_TIMELY_THRESH_2 0.005
|
| 961 |
+
PREF_DEGFB_STATPHASEFILE FALSE
|
| 962 |
+
PREF_MAX_DEGFB 4
|
| 963 |
+
PREF_DHAL FALSE
|
| 964 |
+
PREF_DHAL_SENTTHRESH 16
|
| 965 |
+
PREF_DHAL_USETHRESH_MAX 12
|
| 966 |
+
PREF_DHAL_USETHRESH_MIN2 8
|
| 967 |
+
PREF_DHAL_USETHRESH_MIN1 4
|
| 968 |
+
PREF_DHAL_MAXDEG 64
|
| 969 |
+
PREF_HFILTER_ON FALSE
|
| 970 |
+
PREF_HFILTER_INDEX_BITS 12
|
| 971 |
+
PREF_HFILTER_USE_PC FALSE
|
| 972 |
+
PREF_HFILTER_PRED_USELESS_THRES 2
|
| 973 |
+
PREF_HFILTER_RESET_ENABLE FALSE
|
| 974 |
+
PREF_HFILTER_RESET_INTERVAL 100000
|
| 975 |
+
EIP_ENABLE 0
|
| 976 |
+
L1I_ENTANGLED_TABLE_INDEX_BITS 9
|
| 977 |
+
L1I_ENTANGLED_TABLE_WAYS 16
|
| 978 |
+
DJOLT_ENABLE 0
|
| 979 |
+
FNLMMA_ENABLE 0
|
| 980 |
+
FDIP_ENABLE 1
|
| 981 |
+
FDIP_ALWAYS_PREFETCH FALSE
|
| 982 |
+
PERFECT_FDIP FALSE
|
| 983 |
+
IPRF_MAX_FTQ_ENTRY_CYC 2
|
| 984 |
+
FDIP_BLOOM_FILTER FALSE
|
| 985 |
+
FDIP_BLOOM_ENTRIES 4000
|
| 986 |
+
FDIP_BLOOM2_ENTRIES 1000
|
| 987 |
+
FDIP_BLOOM4_ENTRIES 1000
|
| 988 |
+
FDIP_BLOOM_SIZE 16384
|
| 989 |
+
FDIP_BLOOM_HASHES 6
|
| 990 |
+
FDIP_BLOOM_CLEAR_UNUSEFUL_RATIO 0.95
|
| 991 |
+
FDIP_BLOOM_CLEAR_CYC_PERIOD 10000
|
| 992 |
+
FDIP_UTILITY_HASH_ENABLE 0
|
| 993 |
+
FDIP_UTILITY_PREF_POLICY 0
|
| 994 |
+
FDIP_ADJUSTABLE_FTQ 0
|
| 995 |
+
FDIP_ADJUSTABLE_FTQ_CYC 100000
|
| 996 |
+
UTILITY_RATIO_THRESHOLD 0.58
|
| 997 |
+
TIMELINESS_RATIO_THRESHOLD 0.82
|
| 998 |
+
FDIP_PREF_NO_LATENCY FALSE
|
| 999 |
+
UDP_USEFUL_THRESHOLD 0
|
| 1000 |
+
UDP_WEIGHT_USEFUL 4
|
| 1001 |
+
UDP_WEIGHT_UNUSEFUL 1
|
| 1002 |
+
UDP_WEIGHT_POSITIVE_SATURATION 2147483647
|
| 1003 |
+
FDIP_GHIST_HASHING FALSE
|
| 1004 |
+
FDIP_UTILITY_ONLY_TRAIN_OFF_PATH FALSE
|
| 1005 |
+
FDIP_GHIST_BITS 8
|
| 1006 |
+
UFTQ_MIN_FTQ_BLOCK_NUM 4
|
| 1007 |
+
UFTQ_MAX_FTQ_BLOCK_NUM 64
|
| 1008 |
+
FDIP_SENIORITY_FTQ_HOLD_CYC 30000
|
| 1009 |
+
FDIP_PERFECT_PREFETCH FALSE
|
| 1010 |
+
FDIP_FREEZE_AT_MEM_BUF_LIMIT TRUE
|
| 1011 |
+
FDIP_DUAL_PATH_PREF_IC_ENABLE FALSE
|
| 1012 |
+
FDIP_DUAL_PATH_PREF_UOC_ENABLE FALSE
|
| 1013 |
+
TOP_MISPRED_BR_FILEPATH "br_resteer_coverage.csv"
|
| 1014 |
+
TOP_MISPRED_BR_RESTEER_COVERAGE 0
|
| 1015 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_ENABLE FALSE
|
| 1016 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_MISPRED_THRESHOLD 1
|
| 1017 |
+
FDIP_PRINT_CL_INFO FALSE
|
| 1018 |
+
BRANCH_MISPREDICTION_TABLE_SIZE 0
|
| 1019 |
+
UOC_PREF FALSE
|
| 1020 |
+
UOC_ORACLE_PREF FALSE
|
| 1021 |
+
UOC_ZERO_LATENCY_PREF FALSE
|
| 1022 |
+
L2L1PREF_ON FALSE
|
| 1023 |
+
L2WAY_PREF FALSE
|
| 1024 |
+
L2MARKV_PREF_ON FALSE
|
| 1025 |
+
L2NEXT_PREF_ON FALSE
|
| 1026 |
+
L2HIT_STREAM_PREF_ON FALSE
|
| 1027 |
+
L2L1_DC_HIT_TRAIN FALSE
|
| 1028 |
+
L1_HIT_DUMP_FILE_ON FALSE
|
| 1029 |
+
L1_HIT_DUMP_WO_TXT FALSE
|
| 1030 |
+
L1_HIT_DUMPFILE "l1hit_dump.out"
|
| 1031 |
+
IDEAL_L2_L1_PREFETCHER FALSE
|
| 1032 |
+
IDEAL_L2_ICACHE_PREFETCHER FALSE
|
| 1033 |
+
L1WAY_PREF_SEND_QUEUE 4
|
| 1034 |
+
L1PREF_REQ_QUEUE_SIZE 1024
|
| 1035 |
+
L1PREF_IMMEDIATE FALSE
|
| 1036 |
+
L1WAY_PREF_TIMER_DIS 1000
|
| 1037 |
+
L1MARKV_PREF_SEND_QUEUE 4
|
| 1038 |
+
L1PREF_MARKV_REQ_QUEUE_SIZE 1024
|
| 1039 |
+
MARKV_L2ACCESS_REQ_Q_SIZE 64
|
| 1040 |
+
L1MARKV_PREF_IMMEDIATE FALSE
|
| 1041 |
+
L1MARKV_PREF_TIMER_DIS 1
|
| 1042 |
+
L2L1_HIT_TRAIN TRUE
|
| 1043 |
+
L1MARKV_REQ_TH 1
|
| 1044 |
+
L2L1_IMMEDIATE_PREF_CACHE FALSE
|
| 1045 |
+
L2L1_FILL_PREF_CACHE FALSE
|
| 1046 |
+
L2L1_L2_HIT_STAT FALSE
|
| 1047 |
+
PREF_GHB_ON FALSE
|
| 1048 |
+
DEBUG_PREF_GHB FALSE
|
| 1049 |
+
PREF_GHB_BUFFER_N 1024
|
| 1050 |
+
PREF_GHB_INDEX_N 128
|
| 1051 |
+
PREF_GHB_CZONE_BITS 12
|
| 1052 |
+
PREF_GHB_DEGREE 16
|
| 1053 |
+
PREF_GHB_MAX_DEGREE 32
|
| 1054 |
+
PREF_STRIDE_ON FALSE
|
| 1055 |
+
DEBUG_PREF_STRIDE FALSE
|
| 1056 |
+
PREF_STRIDE_TABLE_N 1024
|
| 1057 |
+
PREF_STRIDE_REGION_BITS 16
|
| 1058 |
+
PREF_STRIDE_DEGREE 4
|
| 1059 |
+
PREF_STRIDE_DISTANCE 16
|
| 1060 |
+
PREF_STRIDE_STARTDISTANCE 1
|
| 1061 |
+
PREF_STRIDE_SINGLE_THRESH 6
|
| 1062 |
+
PREF_STRIDE_MULTI_THRESH 6
|
| 1063 |
+
PREF_STRIDE_SINGLE_STRIDE_MODE FALSE
|
| 1064 |
+
PREF_STRIDEPC_ON FALSE
|
| 1065 |
+
DEBUG_PREF_STRIDEPC FALSE
|
| 1066 |
+
PREF_STRIDEPC_TABLE_N 1024
|
| 1067 |
+
PREF_STRIDEPC_DEGREE 4
|
| 1068 |
+
PREF_STRIDEPC_DISTANCE 16
|
| 1069 |
+
PREF_STRIDEPC_USELOADADDR FALSE
|
| 1070 |
+
PREF_STRIDEPC_TRAINNUM 2
|
| 1071 |
+
PREF_STRIDEPC_STARTDIS 4
|
| 1072 |
+
PREF_PHASE_ON FALSE
|
| 1073 |
+
PREF_PHASE_STUDY FALSE
|
| 1074 |
+
DEBUG_PREF_PHASE FALSE
|
| 1075 |
+
PREF_PHASE_PRIME_HASH 16381
|
| 1076 |
+
PREF_PHASE_INFOSIZE 16384
|
| 1077 |
+
PREF_PHASE_LOG2REGIONSIZE 12
|
| 1078 |
+
PREF_PHASE_REGIONENTRIES 64
|
| 1079 |
+
PREF_PHASE_TRACKEDREGIONS 32
|
| 1080 |
+
PREF_PHASE_INTERVAL 100000
|
| 1081 |
+
PREF_PHASE_TABLE_SIZE 64
|
| 1082 |
+
PREF_PHASE_MAXDIFF_THRESH 64
|
| 1083 |
+
PREF_PHASE_MIN_MISSES 64
|
| 1084 |
+
PREF_PHASE_MISSPER 0.4
|
| 1085 |
+
PREF_2DC_ON FALSE
|
| 1086 |
+
DEBUG_PREF_2DC FALSE
|
| 1087 |
+
PREF_2DC_CACHE_SIZE (1 * 1024)
|
| 1088 |
+
PREF_2DC_CACHE_ASSOC 4
|
| 1089 |
+
PREF_2DC_CACHE_LINE_SIZE 1
|
| 1090 |
+
PREF_2DC_DEGREE 16
|
| 1091 |
+
PREF_2DC_ZONE_SHIFT 10
|
| 1092 |
+
PREF_2DC_TAG_SIZE 16
|
| 1093 |
+
PREF_2DC_NUM_REGIONS 64
|
| 1094 |
+
PREF_2DC_REGION_HASH 61
|
| 1095 |
+
PREF_MARKOV_ON FALSE
|
| 1096 |
+
DEBUG_PREF_MARKOV FALSE
|
| 1097 |
+
PREF_MARKOV_NUM_ENTRIES 65536
|
| 1098 |
+
PREF_MARKOV_NUM_NEXT_STATES 8
|
| 1099 |
+
PREF_MARKOV_SEND_ON_PREF_HIT TRUE
|
| 1100 |
+
PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE
|
| 1101 |
+
PREF_MARKOV_TABLE_UPDATE_POLICY 0
|
| 1102 |
+
PREF_MARKOV_SEND_THRESHOLD 0
|