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- .gitattributes +1 -0
- tsp/command.txt +1 -0
- tsp/events.txt +9 -0
- tsp/fingerprint/bbfp +18 -0
- tsp/fingerprint/footprint_pieces/segment.0 +1 -0
- tsp/fingerprint/footprint_pieces/segment.1 +1 -0
- tsp/fingerprint/footprint_pieces/segment.10 +1 -0
- tsp/fingerprint/footprint_pieces/segment.11 +1 -0
- tsp/fingerprint/footprint_pieces/segment.12 +1 -0
- tsp/fingerprint/footprint_pieces/segment.13 +1 -0
- tsp/fingerprint/footprint_pieces/segment.14 +1 -0
- tsp/fingerprint/footprint_pieces/segment.15 +1 -0
- tsp/fingerprint/footprint_pieces/segment.16 +1 -0
- tsp/fingerprint/footprint_pieces/segment.17 +1 -0
- tsp/fingerprint/footprint_pieces/segment.2 +1 -0
- tsp/fingerprint/footprint_pieces/segment.3 +1 -0
- tsp/fingerprint/footprint_pieces/segment.4 +1 -0
- tsp/fingerprint/footprint_pieces/segment.5 +1 -0
- tsp/fingerprint/footprint_pieces/segment.6 +1 -0
- tsp/fingerprint/footprint_pieces/segment.7 +1 -0
- tsp/fingerprint/footprint_pieces/segment.8 +1 -0
- tsp/fingerprint/footprint_pieces/segment.9 +1 -0
- tsp/fingerprint/pieces/bbfp +18 -0
- tsp/fingerprint/pieces/segment.0 +1 -0
- tsp/fingerprint/pieces/segment.1 +1 -0
- tsp/fingerprint/pieces/segment.10 +1 -0
- tsp/fingerprint/pieces/segment.11 +1 -0
- tsp/fingerprint/pieces/segment.12 +1 -0
- tsp/fingerprint/pieces/segment.13 +1 -0
- tsp/fingerprint/pieces/segment.14 +1 -0
- tsp/fingerprint/pieces/segment.15 +1 -0
- tsp/fingerprint/pieces/segment.16 +1 -0
- tsp/fingerprint/pieces/segment.17 +1 -0
- tsp/fingerprint/pieces/segment.2 +1 -0
- tsp/fingerprint/pieces/segment.3 +1 -0
- tsp/fingerprint/pieces/segment.4 +1 -0
- tsp/fingerprint/pieces/segment.5 +1 -0
- tsp/fingerprint/pieces/segment.6 +1 -0
- tsp/fingerprint/pieces/segment.7 +1 -0
- tsp/fingerprint/pieces/segment.8 +1 -0
- tsp/fingerprint/pieces/segment.9 +1 -0
- tsp/fingerprint/run_0/PARAMS.in +268 -0
- tsp/fingerprint/run_0/PARAMS.out +1102 -0
- tsp/fingerprint/run_0/sim.log +830 -0
- tsp/fingerprint/run_1/PARAMS.in +268 -0
- tsp/fingerprint/run_1/PARAMS.out +1102 -0
- tsp/fingerprint/run_1/sim.log +847 -0
- tsp/fingerprint/run_10/PARAMS.in +268 -0
- tsp/fingerprint/run_10/PARAMS.out +1102 -0
- tsp/fingerprint/run_10/sim.log +857 -0
.gitattributes
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@@ -65,3 +65,4 @@ memcached/traces_simp/bin/memcached filter=lfs diff=lfs merge=lfs -text
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redis/traces_simp/bin/redis-server filter=lfs diff=lfs merge=lfs -text
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masstree/traces_simp/bin/masstree_mttest filter=lfs diff=lfs merge=lfs -text
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clickhouse/traces_simp/bin/clickhouse filter=lfs diff=lfs merge=lfs -text
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redis/traces_simp/bin/redis-server filter=lfs diff=lfs merge=lfs -text
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masstree/traces_simp/bin/masstree_mttest filter=lfs diff=lfs merge=lfs -text
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clickhouse/traces_simp/bin/clickhouse filter=lfs diff=lfs merge=lfs -text
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tsp/traces_simp/bin/tsp filter=lfs diff=lfs merge=lfs -text
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tsp/command.txt
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/users/deepmish/CRONO/apps/tsp/tsp 1 22
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tsp/events.txt
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workload=tsp
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start_utc=2026-07-18T03:05:25,596759033+00:00
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exit_after_refs=100000000
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target_fetched_instructions=200000000
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skip_instructions=52070000000
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chunk_instructions=10000000
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trace_exit_status=0
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end_utc=2026-07-18T03:06:07,718803842+00:00
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validated_fetched_instructions=179155372
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tsp/fingerprint/bbfp
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T:1:16450 :2:82306 :3:82244 :4:49346 :5:16464 :6:98688 :7:32896 :8:16448 :9:98688 :10:24672 :11:74016 :12:32896 :13:16448 :14:98688 :15:24672 :16:74016 :17:82240 :18:164480 :19:65800 :20:32900 :21:32896 :22:24675 :23:115248 :24:24695 :25:41155 :26:16462 :27:171276 :28:456680 :29:57617 :30:16448 :31:32896 :32:49344 :33:32900 :34:32900 :35:32900 :36:65856 :37:32928 :38:16464 :39:49392 :40:16464 :41:24696 :42:8232 :43:24696 :44:8232 :45:16464 :46:24696 :47:139808 :48:98688 :49:16448 :50:90475 :51:90475 :52:16450 :53:16450 :54:16450 :55:8225 :56:24675 :57:32900 :58:41125 :59:740754 :60:123459 :61:82306 :62:82306 :63:205765 :64:164612 :65:205765 :66:164612 :67:7792 :68:15584 :69:11688 :70:11688 :71:31168 :72:7792 :73:27272 :74:7792 :75:123459 :76:329224 :77:372570 :78:968 :79:5808 :80:1936 :81:1936 :82:968 :83:2420 :84:4356 :85:2904 :86:968 :87:1936 :88:57596 :89:10164 :90:6776 :91:13552 :92:2904 :93:1452 :94:4356 :95:328976 :96:82244 :97:164488 :98:164488 :99:82244 :100:1452 :101:2420 :102:164488 :103:123366 :104:162552 :105:487656 :106:1936 :107:968 :108:1452 :109:968 :110:123459 :111:370377 :112:123459 :113:123459 :114:82306 :115:205765 :116:98692 :117:67980 :118:110600 :119:4026 :120:10 :121:10040 :122:25 :123:4320 :124:1080 :125:1620 :126:82244 :127:82306 :128:82306 :129:328976 :130:82244 :131:82244 :132:74025 :133:49392
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T:1:16394 :2:81946 :3:81978 :4:49186 :5:16388 :6:98376 :7:32792 :8:16396 :9:98376 :10:24594 :11:73782 :12:32792 :13:16396 :14:98376 :15:24594 :16:73782 :17:81980 :18:163960 :19:65576 :20:32788 :21:32792 :22:24591 :23:114716 :24:24582 :134:1 :25:40975 :26:16390 :27:174543 :28:465472 :29:57365 :30:16396 :31:32792 :32:49188 :33:32788 :34:32788 :35:32788 :36:65552 :37:32776 :38:16388 :39:49164 :40:16388 :41:24582 :42:8194 :43:24582 :44:8194 :45:16388 :46:24582 :47:139366 :48:98376 :49:16396 :50:90167 :51:90167 :52:16394 :53:16394 :54:16394 :55:8197 :56:24594 :57:32788 :58:40990 :59:737514 :60:122919 :61:81946 :62:81946 :63:204865 :64:163892 :65:204865 :66:163892 :67:8636 :68:17272 :69:12954 :70:12954 :71:34544 :72:8636 :73:30226 :74:8634 :75:122919 :76:327784 :77:366550 :78:1080 :79:6480 :80:2160 :81:2160 :82:1080 :83:2700 :84:4860 :85:3240 :86:1080 :87:2160 :88:64260 :89:11340 :90:7560 :91:15120 :92:3240 :93:1620 :94:4860 :95:327911 :96:81976 :97:163952 :98:163952 :99:81976 :100:1620 :101:2700 :102:163952 :103:122964 :104:161792 :105:485376 :106:2160 :107:1080 :108:1620 :109:1080 :110:122919 :111:368757 :112:122919 :113:122919 :114:81946 :115:204865 :116:98372 :117:67884 :118:110545 :119:3930 :120:10 :121:9800 :122:25 :123:4152 :124:1038 :125:1557 :126:81978 :127:81946 :128:81946 :129:327912 :130:81976 :131:81976 :132:73773 :133:49164
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T:1:16444 :2:82028 :3:82212 :4:49328 :5:16396 :6:98652 :7:32884 :8:16442 :9:98652 :10:24663 :11:73989 :12:32884 :13:16442 :14:98652 :15:24663 :16:73989 :17:82210 :18:164420 :19:65776 :20:32888 :21:32884 :22:24666 :23:114758 :24:24591 :25:40985 :26:16394 :27:166272 :28:443584 :29:57379 :30:16442 :31:32884 :32:49326 :33:32888 :34:32888 :35:32888 :36:65584 :37:32792 :38:16396 :39:49182 :40:16396 :41:24594 :42:8198 :43:24594 :44:8198 :45:16396 :46:24594 :47:139757 :48:98652 :49:16442 :50:90442 :51:90442 :52:16444 :53:16444 :54:16444 :55:8222 :56:24663 :57:32888 :58:41105 :59:738252 :60:123042 :61:82028 :62:82028 :63:205070 :64:164056 :65:205070 :66:164056 :67:8940 :68:17880 :69:13410 :70:13410 :71:35760 :72:8940 :73:31290 :74:8936 :75:123042 :76:328110 :77:365440 :78:1144 :79:6864 :80:2288 :81:2288 :82:1144 :83:2860 :84:5148 :85:3432 :86:1144 :87:2288 :88:68068 :89:12012 :90:8008 :91:16016 :92:3432 :93:1716 :94:5148 :95:328848 :135:1 :96:82214 :97:164428 :98:164428 :99:82214 :100:1716 :101:2860 :102:164424 :103:123321 :104:162140 :105:486420 :106:2288 :107:1144 :108:1716 :109:1144 :110:123042 :111:369126 :112:123042 :113:123042 :114:82028 :115:205065 :116:98656 :117:66669 :118:107370 :119:4882 :120:28 :121:12135 :122:70 :123:5992 :124:1498 :125:2247 :126:82212 :127:82028 :128:82028 :129:328848 :130:82214 :131:82214 :132:73998 :133:49188
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T:1:16662 :2:83246 :3:83314 :4:49986 :5:16646 :6:99984 :7:33328 :8:16664 :9:99972 :10:24993 :11:74979 :12:33324 :13:16662 :14:99972 :15:24993 :16:74979 :17:83310 :18:166620 :19:66648 :20:33324 :21:33324 :22:24993 :23:116536 :24:24969 :25:41615 :26:16646 :27:136782 :28:364824 :29:58261 :30:16664 :31:33328 :32:49986 :33:33324 :34:33324 :35:33324 :36:66584 :136:7 :37:33292 :38:16646 :39:49944 :40:16646 :41:24969 :42:8323 :43:24969 :44:8323 :45:16646 :46:24969 :47:141627 :48:99972 :49:16662 :50:91641 :51:91641 :52:16662 :53:16662 :54:16662 :55:8331 :56:24993 :57:33324 :58:41655 :59:749214 :60:124869 :61:83246 :62:83246 :63:208115 :64:166492 :65:208115 :66:166492 :67:7746 :68:15492 :69:11619 :70:11619 :71:30984 :72:7746 :73:27111 :74:7708 :75:124869 :76:332984 :137:2 :77:377500 :78:974 :79:5844 :80:1948 :81:1948 :82:974 :83:2435 :84:4383 :85:2922 :86:974 :87:1948 :88:57953 :89:10227 :90:6818 :91:13636 :92:2922 :93:1461 :94:4383 :95:333256 :96:83314 :97:166627 :98:166624 :99:83312 :100:1461 :101:2435 :102:166556 :103:124968 :104:164676 :105:494028 :106:1948 :107:974 :108:1461 :109:974 :110:124869 :111:374607 :112:124869 :113:124869 :114:83246 :115:208120 :116:99972 :117:62235 :118:90795 :119:8496 :120:270 :138:2 :139:5 :121:20565 :122:670 :123:20688 :124:5172 :125:7758 :126:83314 :127:83246 :128:83246 :129:333256 :130:83312 :131:83312 :132:74979 :133:49938
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T:1:16638 :2:83238 :3:83186 :4:49914 :5:16650 :6:99816 :7:33272 :8:16636 :9:99828 :10:24957 :11:74871 :12:33276 :13:16638 :14:99828 :15:24957 :16:74871 :17:83190 :18:166380 :19:66552 :20:33276 :21:33276 :22:24957 :23:116550 :24:24975 :25:41625 :26:16650 :27:134679 :28:359089 :29:58275 :30:16636 :31:33272 :32:49914 :33:33276 :34:33276 :35:33276 :36:66600 :37:33300 :38:16650 :39:49950 :40:16650 :41:24975 :42:8325 :43:24975 :44:8325 :45:16650 :46:24975 :47:141423 :48:99828 :49:16638 :50:91509 :51:91509 :52:16638 :53:16638 :54:16638 :55:8319 :56:24957 :57:33276 :58:41595 :59:749142 :60:124857 :61:83238 :62:83238 :63:208095 :64:166476 :65:208095 :66:166476 :67:8368 :68:16736 :69:12552 :70:12552 :71:33472 :72:8368 :73:29288 :74:8346 :75:124857 :76:332952 :77:374350 :78:1042 :79:6252 :80:2084 :81:2084 :82:1042 :83:2605 :84:4689 :85:3126 :86:1042 :87:2084 :88:61999 :89:10941 :90:7294 :91:14588 :92:3126 :93:1563 :94:4689 :95:332744 :96:83186 :97:166372 :140:1 :98:166376 :99:83188 :100:1563 :101:2605 :102:166340 :103:124782 :104:164292 :105:492876 :106:2084 :107:1042 :108:1563 :109:1042 :110:124857 :111:374571 :112:124857 :113:124857 :114:83238 :115:208095 :116:99828 :117:61242 :118:88960 :119:9086 :120:198 :121:22220 :122:495 :123:20976 :124:5244 :125:7866 :126:83186 :127:83238 :128:83238 :129:332744 :130:83188 :131:83188 :132:74871 :133:49950
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| 6 |
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T:1:16758 :2:83768 :3:83790 :4:50274 :5:16752 :6:100548 :7:33516 :8:16758 :9:100548 :10:25137 :11:75411 :12:33516 :13:16758 :14:100548 :15:25137 :16:75411 :17:83790 :18:167580 :19:67032 :20:33516 :21:33516 :22:25137 :23:117264 :24:25128 :25:41880 :26:16752 :27:118680 :28:316496 :29:58639 :30:16758 :31:33516 :32:50274 :33:33516 :34:33516 :35:33516 :36:67016 :37:33504 :38:16752 :39:50256 :40:16754 :41:25131 :42:8377 :43:25128 :44:8376 :45:16752 :46:25128 :47:142443 :48:100548 :49:16758 :50:92169 :51:92169 :52:16758 :53:16758 :54:16758 :55:8379 :56:25137 :57:33516 :58:41895 :59:753908 :60:125649 :61:83766 :62:83766 :63:209415 :64:167532 :65:209415 :66:167532 :67:7736 :68:15472 :69:11604 :70:11604 :71:30944 :72:7736 :73:27076 :74:7708 :75:125649 :76:335064 :77:380150 :78:966 :79:5796 :80:1932 :81:1932 :82:966 :83:2415 :84:4347 :85:2898 :86:966 :87:1932 :88:57477 :89:10143 :90:6762 :91:13524 :92:2898 :93:1449 :94:4347 :95:335160 :96:83790 :97:167580 :98:167580 :99:83790 :100:1449 :101:2415 :102:167504 :103:125685 :104:165648 :105:496944 :106:1932 :107:966 :108:1449 :109:966 :110:125652 :111:376956 :112:125652 :113:125652 :114:83768 :115:209415 :116:100548 :117:58317 :118:75995 :119:11396 :120:374 :121:27555 :122:935 :123:33920 :124:8480 :125:12720 :126:83790 :127:83768 :128:83768 :129:335160 :130:83790 :131:83790 :132:75411 :133:50256
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| 7 |
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| 8 |
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T:1:16484 :2:82398 :3:82426 :4:49456 :5:16480 :6:98916 :7:32972 :8:16486 :9:98916 :10:24729 :11:74187 :12:32972 :13:16486 :14:98916 :15:24729 :16:74178 :17:82420 :18:164840 :19:65936 :20:32968 :21:32968 :22:24726 :23:115360 :24:24720 :25:41200 :26:16480 :27:154557 :28:412176 :29:57680 :30:16486 :31:32972 :32:49452 :33:32968 :34:32968 :35:32968 :36:65912 :37:32960 :38:16480 :39:49440 :40:16478 :41:24717 :42:8239 :43:24717 :44:8239 :45:16478 :46:24720 :47:140114 :48:98904 :49:16484 :50:90662 :51:90662 :52:16484 :53:16484 :54:16484 :55:8242 :56:24726 :57:32968 :58:41210 :59:741582 :60:123597 :61:82398 :62:82398 :63:205995 :64:164796 :65:205995 :66:164796 :67:9360 :68:18720 :69:14040 :70:14040 :71:37440 :72:9360 :73:32760 :74:9330 :75:123597 :76:329592 :77:365190 :78:1174 :79:7044 :80:2348 :81:2348 :82:1174 :83:2935 :84:5283 :85:3522 :86:1174 :87:2348 :88:69853 :89:12327 :90:8218 :91:16436 :92:3522 :93:1761 :94:5283 :95:329704 :96:82426 :97:164852 :98:164852 :99:82426 :100:1761 :101:2935 :102:164844 :103:123639 :104:162504 :105:487512 :106:2348 :107:1174 :108:1761 :109:1174 :110:123597 :111:370791 :112:123597 :113:123597 :114:82398 :115:205995 :142:3 :116:98912 :117:65184 :118:103128 :119:6000 :120:48 :121:14880 :122:120 :123:8816 :124:2204 :125:3306 :126:82426 :127:82398 :128:82398 :129:329704 :130:82426 :131:82426 :132:74178 :133:49440
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| 9 |
+
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|
| 10 |
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T:1:16542 :2:82648 :3:82710 :4:49626 :5:16528 :6:99252 :7:33084 :8:16542 :9:99252 :10:24813 :11:74439 :12:33084 :13:16542 :14:99252 :15:24813 :16:74439 :17:82710 :18:165420 :19:66168 :20:33084 :21:33084 :22:24813 :23:115682 :24:24789 :25:41315 :26:16526 :27:149181 :28:397880 :29:57841 :30:16542 :31:33084 :32:49626 :33:33084 :34:33084 :35:33084 :36:66104 :37:33056 :38:16528 :39:49578 :40:16526 :41:24789 :42:8263 :43:24789 :44:8263 :45:16526 :46:24792 :47:140607 :48:99252 :49:16542 :50:90981 :51:90981 :52:16542 :53:16542 :54:16542 :55:8271 :56:24813 :57:33084 :58:41355 :59:743814 :144:11 :60:123972 :61:82648 :62:82648 :63:206620 :64:165296 :65:206620 :66:165296 :67:8910 :68:17816 :69:13362 :70:13362 :71:35632 :72:8908 :73:31178 :74:8876 :75:123972 :76:330592 :145:2 :146:3 :147:5 :148:2 :149:3 :150:4 :151:2 :152:3 :153:2 :154:2 :155:2 :156:8 :157:3 :158:8 :159:3 :77:368690 :160:5 :78:1120 :79:6720 :161:5 :80:2240 :81:2240 :162:2 :82:1118 :83:2795 :84:5031 :85:3354 :86:1118 :87:2236 :88:66521 :89:11739 :90:7826 :91:15652 :92:3354 :163:24 :164:12 :165:21 :166:3 :167:3 :168:2 :169:4 :170:3 :171:2 :172:2 :173:2 :174:2 :175:4 :176:2 :93:1677 :94:5040 :177:5 :178:3 :179:4 :180:12 :181:2 :182:3 :183:5 :184:7 :95:330840 :96:82710 :97:165420 :98:165420 :99:82710 :100:1680 :101:2800 :102:165420 :103:124065 :104:163180 :105:489540 :106:2240 :107:1120 :108:1680 :109:1120 :110:123972 :111:371916 :112:123969 :113:123969 :114:82646 :115:206620 :116:99252 :117:64293 :118:100415 :119:6764 :120:32 :121:16830 :122:80 :123:10784 :124:2696 :125:4044 :126:82710 :127:82648 :128:82648 :129:330840 :130:82710 :131:82710 :132:74439 :133:49584
|
| 11 |
+
T:1:16462 :2:82310 :3:82314 :4:49386 :5:16462 :6:98784 :7:32928 :8:16464 :9:98783 :10:24693 :11:74079 :12:32924 :13:16462 :14:98772 :15:24693 :16:74079 :17:82310 :18:164620 :19:65848 :20:32924 :21:32924 :22:24693 :23:115248 :24:24696 :25:41160 :26:16464 :27:145017 :28:386712 :29:57624 :30:16464 :31:32928 :32:49386 :33:32924 :34:32924 :35:32924 :36:65848 :37:32924 :38:16462 :39:49392 :40:16462 :41:24693 :42:8231 :43:24693 :44:8231 :45:16462 :46:24693 :47:139927 :48:98772 :49:16462 :50:90541 :51:90541 :52:16462 :53:16462 :54:16462 :55:8231 :56:24693 :57:32924 :58:41155 :59:740808 :60:123468 :61:82312 :62:82312 :63:205780 :64:164624 :65:205780 :66:164624 :67:10892 :68:21784 :69:16338 :70:16338 :71:43568 :72:10892 :73:38122 :74:10824 :75:123468 :76:329248 :77:357100 :78:1364 :79:8184 :80:2728 :81:2728 :82:1364 :83:3410 :84:6138 :85:4092 :86:1364 :87:2728 :88:81158 :89:14322 :90:9548 :91:19096 :92:4092 :93:2046 :94:6138 :95:329256 :96:82314 :97:164628 :98:164628 :99:82314 :100:2046 :101:3410 :102:164604 :103:123471 :104:161900 :105:485700 :106:2728 :107:1364 :108:2046 :109:1364 :110:123465 :111:370395 :112:123468 :113:123468 :114:82312 :115:205780 :116:98772 :117:63189 :118:95725 :119:7260 :120:136 :121:17810 :122:340 :123:15344 :124:3836 :125:5754 :126:82314 :127:82310 :128:82310 :129:329256 :130:82314 :131:82314 :132:74079 :133:49386
|
| 12 |
+
T:1:16504 :2:82612 :3:82516 :4:49512 :5:16526 :6:99012 :7:33004 :8:16502 :9:99012 :185:1 :10:24756 :11:74268 :12:33008 :13:16504 :14:99024 :15:24756 :16:74268 :17:82520 :18:165040 :19:66016 :20:33008 :21:33008 :22:24756 :23:115682 :24:24789 :25:41315 :26:16526 :27:146832 :28:391456 :29:57841 :30:16502 :31:33004 :32:49512 :33:33008 :34:33008 :35:33008 :36:66112 :37:33052 :38:16526 :39:49578 :40:16528 :41:24792 :42:8264 :43:24792 :44:8264 :45:16526 :46:24789 :47:140284 :48:99024 :49:16504 :50:90772 :51:90772 :52:16504 :53:16504 :54:16504 :55:8252 :56:24756 :57:33008 :58:41260 :59:743508 :60:123918 :61:82612 :62:82612 :63:206530 :64:165224 :65:206530 :66:165224 :67:9740 :68:19476 :69:14607 :70:14607 :71:38952 :72:9738 :73:34083 :74:9684 :75:123918 :76:330446 :145:2 :146:3 :147:5 :148:2 :149:3 :150:4 :151:2 :152:3 :153:2 :154:2 :155:2 :156:8 :157:3 :158:8 :159:3 :77:364360 :160:5 :78:1208 :79:7248 :161:5 :80:2416 :81:2416 :162:2 :82:1206 :83:3015 :84:5427 :85:3618 :86:1206 :87:2412 :88:71757 :89:12663 :90:8442 :91:16884 :92:3618 :163:24 :164:12 :165:21 :166:3 :167:3 :168:2 :169:4 :170:3 :171:2 :172:2 :173:2 :174:2 :175:4 :176:2 :93:1809 :94:5436 :177:5 :178:3 :179:4 :180:12 :181:2 :182:3 :183:5 :184:7 :95:330064 :96:82516 :97:165032 :98:165032 :99:82516 :100:1812 :101:3020 :102:165028 :103:123774 :104:162616 :105:487848 :106:2416 :107:1208 :108:1812 :109:1208 :110:123918 :111:371754 :112:123918 :113:123918 :114:82612 :115:206525 :116:99024 :117:63909 :118:98775 :119:6906 :120:44 :121:17155 :122:110 :123:12384 :124:3096 :125:4644 :126:82516 :127:82612 :128:82612 :129:330064 :130:82516 :131:82516 :132:74268 :133:49578
|
| 13 |
+
T:1:16546 :2:82694 :3:82734 :4:49638 :5:16538 :6:99288 :7:33096 :8:16548 :9:99276 :10:24819 :11:74457 :12:33092 :13:16546 :14:99276 :15:24819 :16:74457 :17:82730 :18:165460 :19:66184 :20:33092 :21:33092 :22:24819 :23:115766 :24:24807 :25:41345 :26:16538 :27:143148 :28:381768 :29:57883 :30:16548 :31:33096 :32:49638 :33:33092 :34:33092 :35:33092 :36:66144 :37:33076 :38:16538 :39:49614 :40:16536 :41:24804 :42:8268 :43:24804 :44:8268 :45:16538 :46:24807 :47:140641 :48:99276 :49:16546 :50:91003 :51:91003 :52:16546 :53:16546 :54:16546 :55:8273 :56:24819 :57:33092 :58:41365 :59:744246 :60:124041 :61:82694 :62:82694 :63:206735 :64:165388 :65:206735 :66:165388 :67:9528 :68:19056 :69:14292 :70:14292 :71:38112 :72:9528 :73:33348 :74:9482 :75:124041 :76:330776 :137:2 :77:365830 :78:1196 :79:7176 :80:2392 :81:2392 :82:1196 :83:2990 :84:5382 :85:3588 :86:1196 :87:2392 :88:71162 :89:12558 :90:8372 :91:16744 :92:3588 :93:1794 :94:5382 :95:330932 :96:82732 :97:165464 :98:165464 :99:82732 :100:1794 :101:2990 :102:165456 :103:124098 :104:163072 :105:489216 :106:2392 :107:1196 :108:1794 :109:1196 :110:124041 :111:372123 :112:124041 :113:124041 :114:82694 :115:206740 :116:99276 :117:63045 :118:96735 :119:7608 :120:56 :121:18880 :122:140 :123:13344 :124:3336 :125:5004 :126:82734 :127:82694 :128:82694 :129:330936 :130:82732 :131:82732 :132:74457 :133:49614
|
| 14 |
+
T:1:16510 :2:82638 :3:82552 :4:49534 :5:16532 :6:99060 :7:33020 :8:16510 :9:99072 :10:24768 :11:74304 :12:33024 :13:16512 :14:99072 :15:24768 :16:74304 :17:82560 :18:165120 :19:66040 :20:33020 :21:33024 :22:24765 :23:115724 :24:24798 :25:41330 :26:16532 :27:138786 :28:370008 :29:57862 :30:16510 :31:33020 :32:49536 :33:33020 :34:33020 :35:33020 :36:66128 :37:33064 :38:16532 :39:49596 :40:16532 :41:24798 :42:8266 :43:24798 :44:8266 :45:16532 :46:24798 :47:140352 :48:99072 :49:16512 :50:90805 :51:90805 :52:16510 :53:16510 :54:16510 :55:8255 :56:24765 :57:33020 :58:41277 :59:743742 :60:123957 :61:82638 :62:82638 :63:206595 :64:165276 :65:206595 :66:165276 :67:10612 :68:21224 :69:15918 :70:15918 :71:42448 :72:10612 :73:37142 :74:10538 :75:123957 :76:330552 :77:360130 :78:1316 :79:7896 :80:2632 :81:2632 :82:1316 :83:3290 :84:5922 :85:3948 :86:1316 :87:2632 :88:78302 :89:13818 :90:9212 :91:18424 :92:3948 :93:1974 :94:5922 :95:330208 :186:4 :96:82554 :97:165108 :98:165108 :99:82554 :100:1974 :101:3290 :102:165080 :103:123831 :104:162476 :105:487428 :106:2632 :107:1316 :108:1974 :109:1316 :110:123957 :111:371871 :112:123957 :113:123957 :114:82638 :115:206595 :116:99068 :117:62142 :118:93560 :119:8106 :120:124 :121:19955 :122:310 :123:16016 :124:4004 :125:6006 :126:82552 :127:82638 :128:82638 :129:330208 :130:82554 :131:82554 :132:74295 :133:49596
|
| 15 |
+
T:1:16502 :2:82448 :3:82504 :4:49502 :5:16486 :6:99000 :7:33000 :8:16500 :9:99000 :10:24750 :11:74250 :12:33000 :13:16500 :14:99000 :15:24750 :16:74250 :17:82500 :18:165000 :19:66008 :20:33004 :21:33000 :22:24753 :23:115402 :24:24729 :25:41215 :26:16486 :27:146694 :28:391240 :29:57701 :30:16500 :31:33000 :32:49500 :33:33004 :34:33004 :35:33004 :36:65952 :37:32972 :38:16486 :39:49458 :40:16488 :41:24732 :42:8244 :43:24729 :44:8243 :45:16486 :46:24729 :47:140250 :48:99000 :49:16500 :50:90761 :51:90761 :52:16502 :53:16502 :54:16502 :55:8251 :56:24753 :57:33004 :58:41250 :187:3 :59:742032 :60:123672 :61:82448 :62:82448 :63:206120 :64:164896 :65:206120 :66:164896 :67:10084 :68:20168 :69:15126 :70:15126 :71:40336 :72:10084 :73:35294 :74:10050 :75:123670 :76:329784 :77:361820 :78:1266 :79:7596 :80:2532 :81:2532 :82:1266 :83:3165 :84:5697 :85:3798 :86:1266 :87:2532 :88:75327 :89:13293 :90:8862 :91:17724 :92:3798 :93:1899 :94:5697 :95:330016 :96:82504 :97:165008 :98:165008 :99:82504 :100:1899 :101:3165 :102:165004 :103:123756 :104:162476 :105:487428 :106:2532 :107:1266 :108:1899 :109:1266 :110:123672 :111:371016 :112:123672 :113:123672 :114:82448 :115:206115 :116:99004 :117:63564 :118:98530 :119:7126 :120:60 :121:17665 :122:150 :123:11856 :124:2964 :125:4446 :126:82504 :127:82448 :128:82448 :129:330016 :130:82504 :131:82504 :132:74259 :133:49458
|
| 16 |
+
T:1:16370 :2:81832 :3:81850 :4:49110 :5:16366 :6:98220 :7:32740 :8:16370 :9:98220 :10:24555 :11:73665 :12:32740 :13:16370 :14:98220 :15:24555 :16:73665 :17:81850 :18:163700 :19:65480 :20:32740 :21:32740 :22:24555 :23:114548 :24:24546 :25:40910 :26:16364 :27:167295 :28:446144 :29:57274 :30:16370 :31:32740 :32:49110 :33:32740 :34:32740 :35:32740 :36:65456 :37:32732 :38:16366 :39:49092 :40:16364 :41:24546 :42:8182 :43:24549 :44:8183 :45:16366 :46:24549 :47:139145 :48:98220 :49:16370 :50:90035 :51:90035 :52:16370 :53:16370 :54:16370 :55:8185 :56:24555 :57:32740 :58:40925 :59:736476 :60:122745 :61:81830 :62:81830 :63:204575 :64:163660 :65:204575 :66:163660 :67:10132 :68:20264 :69:15198 :70:15198 :71:40528 :72:10132 :73:35462 :74:10106 :75:122745 :188:2 :76:327328 :77:358490 :78:1270 :79:7620 :80:2540 :81:2540 :82:1270 :83:3175 :84:5715 :85:3810 :86:1270 :87:2540 :88:75565 :89:13335 :90:8890 :91:17780 :92:3810 :93:1905 :94:5715 :95:327400 :96:81850 :97:163700 :98:163700 :99:81850 :100:1905 :101:3175 :102:163696 :103:122775 :104:161160 :105:483480 :106:2540 :107:1270 :108:1905 :109:1270 :110:122748 :111:368244 :112:122748 :113:122748 :114:81832 :115:204580 :116:98220 :117:67347 :118:109335 :119:4212 :120:12 :121:10500 :122:30 :123:4656 :124:1164 :125:1746 :126:81850 :127:81832 :128:81832 :129:327400 :130:81850 :131:81850 :132:73665 :133:49098
|
| 17 |
+
T:1:16590 :2:82974 :3:82952 :4:49770 :5:16596 :6:99540 :7:33180 :8:16590 :9:99540 :10:24885 :11:74655 :12:33180 :13:16590 :14:99540 :15:24885 :16:74655 :17:82950 :18:165900 :19:66360 :20:33180 :21:33180 :22:24885 :23:116186 :24:24897 :25:41495 :26:16598 :27:158736 :28:423272 :29:58093 :30:16592 :31:33180 :32:49770 :33:33180 :34:33180 :35:33180 :36:66384 :37:33192 :38:16596 :39:49794 :40:16596 :41:24894 :42:8298 :43:24894 :44:8298 :45:16596 :46:24894 :47:141015 :48:99540 :49:16590 :50:91245 :51:91245 :52:16590 :53:16590 :54:16590 :55:8295 :56:24885 :57:33180 :58:41475 :59:746766 :189:12 :60:124464 :61:82976 :62:82976 :63:207440 :64:165952 :65:207440 :66:165952 :67:6612 :68:13224 :69:9918 :70:9918 :71:26448 :72:6612 :73:23142 :74:6610 :75:124464 :76:331904 :77:381820 :78:820 :79:4920 :80:1640 :81:1640 :82:820 :83:2050 :84:3690 :85:2460 :86:820 :87:1640 :88:48790 :89:8610 :90:5740 :91:11480 :92:2460 :93:1230 :94:3690 :95:331802 :96:82950 :97:165900 :98:165900 :99:82950 :100:1230 :101:2050 :102:165900 :103:124425 :104:164260 :105:492780 :106:1640 :107:820 :108:1230 :109:820 :110:124461 :111:373383 :112:124461 :113:124461 :114:82974 :115:207440 :116:99540 :117:66681 :118:107775 :119:5316 :120:12 :121:13260 :122:30 :123:5376 :124:1344 :125:2016 :126:82952 :127:82974 :128:82974 :129:331808 :130:82950 :131:82950 :132:74655 :133:49788
|
| 18 |
+
T:1:15360 :2:76826 :3:76798 :4:46080 :5:15366 :6:92160 :7:30720 :8:15360 :9:92160 :10:23040 :11:69120 :12:30720 :13:15360 :14:92160 :15:23040 :16:69120 :17:76800 :18:153600 :19:61440 :20:30720 :21:30720 :22:23040 :23:107562 :24:23049 :25:38415 :26:15366 :27:115395 :28:307688 :29:53781 :30:15358 :31:30720 :32:46080 :33:30720 :34:30720 :35:30720 :36:61472 :37:30732 :38:15366 :39:46098 :40:15368 :41:23052 :42:7684 :43:23049 :44:7683 :45:15366 :46:23049 :47:130560 :48:92160 :49:15360 :50:84480 :51:84480 :52:15360 :53:15360 :54:15360 :55:7680 :56:23040 :57:30720 :58:38400 :59:691434 :60:115239 :61:76826 :62:76826 :63:192065 :64:153652 :65:192065 :66:153652 :67:5934 :68:11868 :69:8901 :70:8901 :71:23736 :72:5934 :73:20769 :74:5930 :75:115239 :76:307304 :77:354460 :78:740 :79:4440 :80:1480 :81:1480 :82:740 :83:1850 :84:3330 :85:2220 :86:740 :87:1480 :88:44030 :89:7770 :90:5180 :91:10360 :92:2220 :93:1110 :94:3330 :95:307192 :190:6 :96:76800 :97:153600 :98:153600 :99:76800 :100:1110 :101:1850 :102:153548 :103:115200 :104:152120 :105:456360 :106:1480 :107:740 :108:1110 :109:740 :110:115239 :111:345717 :112:115239 :113:115239 :114:76826 :115:192063 :116:92160 :117:54726 :118:76200 :119:9596 :120:236 :121:23400 :122:590 :123:24016 :124:6004 :125:9006 :126:76798 :127:76826 :128:76826 :129:307192 :130:76800 :131:76800 :132:69120 :133:46098
|
tsp/fingerprint/footprint_pieces/segment.0
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
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tsp/fingerprint/footprint_pieces/segment.1
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tsp/fingerprint/footprint_pieces/segment.10
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tsp/fingerprint/footprint_pieces/segment.11
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tsp/fingerprint/footprint_pieces/segment.2
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tsp/fingerprint/footprint_pieces/segment.3
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tsp/fingerprint/footprint_pieces/segment.7
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tsp/fingerprint/footprint_pieces/segment.9
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:140737340816827:8264 :140737340816830:8264 :140737340816834:8264
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tsp/fingerprint/pieces/bbfp
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| 1 |
+
T:1:16450 :2:82306 :3:82244 :4:49346 :5:16464 :6:98688 :7:32896 :8:16448 :9:98688 :10:24672 :11:74016 :12:32896 :13:16448 :14:98688 :15:24672 :16:74016 :17:82240 :18:164480 :19:65800 :20:32900 :21:32896 :22:24675 :23:115248 :24:24695 :25:41155 :26:16462 :27:171276 :28:456680 :29:57617 :30:16448 :31:32896 :32:49344 :33:32900 :34:32900 :35:32900 :36:65856 :37:32928 :38:16464 :39:49392 :40:16464 :41:24696 :42:8232 :43:24696 :44:8232 :45:16464 :46:24696 :47:139808 :48:98688 :49:16448 :50:90475 :51:90475 :52:16450 :53:16450 :54:16450 :55:8225 :56:24675 :57:32900 :58:41125 :59:740754 :60:123459 :61:82306 :62:82306 :63:205765 :64:164612 :65:205765 :66:164612 :67:7792 :68:15584 :69:11688 :70:11688 :71:31168 :72:7792 :73:27272 :74:7792 :75:123459 :76:329224 :77:372570 :78:968 :79:5808 :80:1936 :81:1936 :82:968 :83:2420 :84:4356 :85:2904 :86:968 :87:1936 :88:57596 :89:10164 :90:6776 :91:13552 :92:2904 :93:1452 :94:4356 :95:328976 :96:82244 :97:164488 :98:164488 :99:82244 :100:1452 :101:2420 :102:164488 :103:123366 :104:162552 :105:487656 :106:1936 :107:968 :108:1452 :109:968 :110:123459 :111:370377 :112:123459 :113:123459 :114:82306 :115:205765 :116:98692 :117:67980 :118:110600 :119:4026 :120:10 :121:10040 :122:25 :123:4320 :124:1080 :125:1620 :126:82244 :127:82306 :128:82306 :129:328976 :130:82244 :131:82244 :132:74025 :133:49392
|
| 2 |
+
T:1:16394 :2:81946 :3:81978 :4:49186 :5:16388 :6:98376 :7:32792 :8:16396 :9:98376 :10:24594 :11:73782 :12:32792 :13:16396 :14:98376 :15:24594 :16:73782 :17:81980 :18:163960 :19:65576 :20:32788 :21:32792 :22:24591 :23:114716 :24:24582 :134:1 :25:40975 :26:16390 :27:174543 :28:465472 :29:57365 :30:16396 :31:32792 :32:49188 :33:32788 :34:32788 :35:32788 :36:65552 :37:32776 :38:16388 :39:49164 :40:16388 :41:24582 :42:8194 :43:24582 :44:8194 :45:16388 :46:24582 :47:139366 :48:98376 :49:16396 :50:90167 :51:90167 :52:16394 :53:16394 :54:16394 :55:8197 :56:24594 :57:32788 :58:40990 :59:737514 :60:122919 :61:81946 :62:81946 :63:204865 :64:163892 :65:204865 :66:163892 :67:8636 :68:17272 :69:12954 :70:12954 :71:34544 :72:8636 :73:30226 :74:8634 :75:122919 :76:327784 :77:366550 :78:1080 :79:6480 :80:2160 :81:2160 :82:1080 :83:2700 :84:4860 :85:3240 :86:1080 :87:2160 :88:64260 :89:11340 :90:7560 :91:15120 :92:3240 :93:1620 :94:4860 :95:327911 :96:81976 :97:163952 :98:163952 :99:81976 :100:1620 :101:2700 :102:163952 :103:122964 :104:161792 :105:485376 :106:2160 :107:1080 :108:1620 :109:1080 :110:122919 :111:368757 :112:122919 :113:122919 :114:81946 :115:204865 :116:98372 :117:67884 :118:110545 :119:3930 :120:10 :121:9800 :122:25 :123:4152 :124:1038 :125:1557 :126:81978 :127:81946 :128:81946 :129:327912 :130:81976 :131:81976 :132:73773 :133:49164
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| 3 |
+
T:1:16444 :2:82028 :3:82212 :4:49328 :5:16396 :6:98652 :7:32884 :8:16442 :9:98652 :10:24663 :11:73989 :12:32884 :13:16442 :14:98652 :15:24663 :16:73989 :17:82210 :18:164420 :19:65776 :20:32888 :21:32884 :22:24666 :23:114758 :24:24591 :25:40985 :26:16394 :27:166272 :28:443584 :29:57379 :30:16442 :31:32884 :32:49326 :33:32888 :34:32888 :35:32888 :36:65584 :37:32792 :38:16396 :39:49182 :40:16396 :41:24594 :42:8198 :43:24594 :44:8198 :45:16396 :46:24594 :47:139757 :48:98652 :49:16442 :50:90442 :51:90442 :52:16444 :53:16444 :54:16444 :55:8222 :56:24663 :57:32888 :58:41105 :59:738252 :60:123042 :61:82028 :62:82028 :63:205070 :64:164056 :65:205070 :66:164056 :67:8940 :68:17880 :69:13410 :70:13410 :71:35760 :72:8940 :73:31290 :74:8936 :75:123042 :76:328110 :77:365440 :78:1144 :79:6864 :80:2288 :81:2288 :82:1144 :83:2860 :84:5148 :85:3432 :86:1144 :87:2288 :88:68068 :89:12012 :90:8008 :91:16016 :92:3432 :93:1716 :94:5148 :95:328848 :135:1 :96:82214 :97:164428 :98:164428 :99:82214 :100:1716 :101:2860 :102:164424 :103:123321 :104:162140 :105:486420 :106:2288 :107:1144 :108:1716 :109:1144 :110:123042 :111:369126 :112:123042 :113:123042 :114:82028 :115:205065 :116:98656 :117:66669 :118:107370 :119:4882 :120:28 :121:12135 :122:70 :123:5992 :124:1498 :125:2247 :126:82212 :127:82028 :128:82028 :129:328848 :130:82214 :131:82214 :132:73998 :133:49188
|
| 4 |
+
T:1:16662 :2:83246 :3:83314 :4:49986 :5:16646 :6:99984 :7:33328 :8:16664 :9:99972 :10:24993 :11:74979 :12:33324 :13:16662 :14:99972 :15:24993 :16:74979 :17:83310 :18:166620 :19:66648 :20:33324 :21:33324 :22:24993 :23:116536 :24:24969 :25:41615 :26:16646 :27:136782 :28:364824 :29:58261 :30:16664 :31:33328 :32:49986 :33:33324 :34:33324 :35:33324 :36:66584 :136:7 :37:33292 :38:16646 :39:49944 :40:16646 :41:24969 :42:8323 :43:24969 :44:8323 :45:16646 :46:24969 :47:141627 :48:99972 :49:16662 :50:91641 :51:91641 :52:16662 :53:16662 :54:16662 :55:8331 :56:24993 :57:33324 :58:41655 :59:749214 :60:124869 :61:83246 :62:83246 :63:208115 :64:166492 :65:208115 :66:166492 :67:7746 :68:15492 :69:11619 :70:11619 :71:30984 :72:7746 :73:27111 :74:7708 :75:124869 :76:332984 :137:2 :77:377500 :78:974 :79:5844 :80:1948 :81:1948 :82:974 :83:2435 :84:4383 :85:2922 :86:974 :87:1948 :88:57953 :89:10227 :90:6818 :91:13636 :92:2922 :93:1461 :94:4383 :95:333256 :96:83314 :97:166627 :98:166624 :99:83312 :100:1461 :101:2435 :102:166556 :103:124968 :104:164676 :105:494028 :106:1948 :107:974 :108:1461 :109:974 :110:124869 :111:374607 :112:124869 :113:124869 :114:83246 :115:208120 :116:99972 :117:62235 :118:90795 :119:8496 :120:270 :138:2 :139:5 :121:20565 :122:670 :123:20688 :124:5172 :125:7758 :126:83314 :127:83246 :128:83246 :129:333256 :130:83312 :131:83312 :132:74979 :133:49938
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| 5 |
+
T:1:16638 :2:83238 :3:83186 :4:49914 :5:16650 :6:99816 :7:33272 :8:16636 :9:99828 :10:24957 :11:74871 :12:33276 :13:16638 :14:99828 :15:24957 :16:74871 :17:83190 :18:166380 :19:66552 :20:33276 :21:33276 :22:24957 :23:116550 :24:24975 :25:41625 :26:16650 :27:134679 :28:359089 :29:58275 :30:16636 :31:33272 :32:49914 :33:33276 :34:33276 :35:33276 :36:66600 :37:33300 :38:16650 :39:49950 :40:16650 :41:24975 :42:8325 :43:24975 :44:8325 :45:16650 :46:24975 :47:141423 :48:99828 :49:16638 :50:91509 :51:91509 :52:16638 :53:16638 :54:16638 :55:8319 :56:24957 :57:33276 :58:41595 :59:749142 :60:124857 :61:83238 :62:83238 :63:208095 :64:166476 :65:208095 :66:166476 :67:8368 :68:16736 :69:12552 :70:12552 :71:33472 :72:8368 :73:29288 :74:8346 :75:124857 :76:332952 :77:374350 :78:1042 :79:6252 :80:2084 :81:2084 :82:1042 :83:2605 :84:4689 :85:3126 :86:1042 :87:2084 :88:61999 :89:10941 :90:7294 :91:14588 :92:3126 :93:1563 :94:4689 :95:332744 :96:83186 :97:166372 :140:1 :98:166376 :99:83188 :100:1563 :101:2605 :102:166340 :103:124782 :104:164292 :105:492876 :106:2084 :107:1042 :108:1563 :109:1042 :110:124857 :111:374571 :112:124857 :113:124857 :114:83238 :115:208095 :116:99828 :117:61242 :118:88960 :119:9086 :120:198 :121:22220 :122:495 :123:20976 :124:5244 :125:7866 :126:83186 :127:83238 :128:83238 :129:332744 :130:83188 :131:83188 :132:74871 :133:49950
|
| 6 |
+
T:1:16758 :2:83768 :3:83790 :4:50274 :5:16752 :6:100548 :7:33516 :8:16758 :9:100548 :10:25137 :11:75411 :12:33516 :13:16758 :14:100548 :15:25137 :16:75411 :17:83790 :18:167580 :19:67032 :20:33516 :21:33516 :22:25137 :23:117264 :24:25128 :25:41880 :26:16752 :27:118680 :28:316496 :29:58639 :30:16758 :31:33516 :32:50274 :33:33516 :34:33516 :35:33516 :36:67016 :37:33504 :38:16752 :39:50256 :40:16754 :41:25131 :42:8377 :43:25128 :44:8376 :45:16752 :46:25128 :47:142443 :48:100548 :49:16758 :50:92169 :51:92169 :52:16758 :53:16758 :54:16758 :55:8379 :56:25137 :57:33516 :58:41895 :59:753908 :60:125649 :61:83766 :62:83766 :63:209415 :64:167532 :65:209415 :66:167532 :67:7736 :68:15472 :69:11604 :70:11604 :71:30944 :72:7736 :73:27076 :74:7708 :75:125649 :76:335064 :77:380150 :78:966 :79:5796 :80:1932 :81:1932 :82:966 :83:2415 :84:4347 :85:2898 :86:966 :87:1932 :88:57477 :89:10143 :90:6762 :91:13524 :92:2898 :93:1449 :94:4347 :95:335160 :96:83790 :97:167580 :98:167580 :99:83790 :100:1449 :101:2415 :102:167504 :103:125685 :104:165648 :105:496944 :106:1932 :107:966 :108:1449 :109:966 :110:125652 :111:376956 :112:125652 :113:125652 :114:83768 :115:209415 :116:100548 :117:58317 :118:75995 :119:11396 :120:374 :121:27555 :122:935 :123:33920 :124:8480 :125:12720 :126:83790 :127:83768 :128:83768 :129:335160 :130:83790 :131:83790 :132:75411 :133:50256
|
| 7 |
+
T:1:16708 :2:83576 :3:83540 :4:50124 :5:16716 :6:100248 :7:33416 :8:16708 :9:100248 :10:25062 :11:75186 :12:33416 :13:16708 :14:100248 :15:25062 :16:75186 :17:83540 :18:167080 :19:66832 :20:33416 :21:33416 :22:25062 :23:117012 :24:25074 :25:41790 :26:16716 :27:127533 :28:340056 :29:58506 :30:16708 :31:33416 :32:50124 :33:33416 :34:33416 :35:33416 :36:66864 :37:33432 :38:16716 :39:50148 :40:16716 :41:25074 :42:8358 :43:25077 :44:8359 :45:16718 :46:25074 :47:142018 :48:100248 :49:16708 :50:91894 :51:91894 :52:16708 :53:16708 :54:16708 :55:8354 :56:25062 :57:33416 :58:41770 :59:752184 :141:4 :60:125367 :61:83578 :62:83578 :63:208945 :64:167156 :65:208945 :66:167156 :67:7802 :68:15604 :69:11703 :70:11703 :71:31208 :72:7802 :73:27307 :74:7782 :75:125367 :76:334312 :77:378880 :78:974 :79:5844 :80:1948 :81:1948 :82:974 :83:2435 :84:4383 :85:2922 :86:974 :87:1948 :88:57953 :89:10227 :90:6818 :91:13636 :92:2922 :93:1461 :94:4383 :95:334160 :96:83540 :97:167080 :98:167080 :99:83540 :100:1461 :101:2435 :102:167060 :103:125310 :104:165132 :105:495396 :106:1948 :107:974 :108:1461 :109:974 :110:125364 :111:376092 :112:125364 :113:125364 :114:83576 :115:208942 :116:100248 :117:59769 :118:84695 :119:10278 :120:166 :121:25280 :122:415 :123:23872 :124:5968 :125:8952 :126:83540 :127:83576 :128:83576 :129:334160 :130:83540 :131:83540 :132:75186 :133:50148
|
| 8 |
+
T:1:16484 :2:82398 :3:82426 :4:49456 :5:16480 :6:98916 :7:32972 :8:16486 :9:98916 :10:24729 :11:74187 :12:32972 :13:16486 :14:98916 :15:24729 :16:74178 :17:82420 :18:164840 :19:65936 :20:32968 :21:32968 :22:24726 :23:115360 :24:24720 :25:41200 :26:16480 :27:154557 :28:412176 :29:57680 :30:16486 :31:32972 :32:49452 :33:32968 :34:32968 :35:32968 :36:65912 :37:32960 :38:16480 :39:49440 :40:16478 :41:24717 :42:8239 :43:24717 :44:8239 :45:16478 :46:24720 :47:140114 :48:98904 :49:16484 :50:90662 :51:90662 :52:16484 :53:16484 :54:16484 :55:8242 :56:24726 :57:32968 :58:41210 :59:741582 :60:123597 :61:82398 :62:82398 :63:205995 :64:164796 :65:205995 :66:164796 :67:9360 :68:18720 :69:14040 :70:14040 :71:37440 :72:9360 :73:32760 :74:9330 :75:123597 :76:329592 :77:365190 :78:1174 :79:7044 :80:2348 :81:2348 :82:1174 :83:2935 :84:5283 :85:3522 :86:1174 :87:2348 :88:69853 :89:12327 :90:8218 :91:16436 :92:3522 :93:1761 :94:5283 :95:329704 :96:82426 :97:164852 :98:164852 :99:82426 :100:1761 :101:2935 :102:164844 :103:123639 :104:162504 :105:487512 :106:2348 :107:1174 :108:1761 :109:1174 :110:123597 :111:370791 :112:123597 :113:123597 :114:82398 :115:205995 :142:3 :116:98912 :117:65184 :118:103128 :119:6000 :120:48 :121:14880 :122:120 :123:8816 :124:2204 :125:3306 :126:82426 :127:82398 :128:82398 :129:329704 :130:82426 :131:82426 :132:74178 :133:49440
|
| 9 |
+
T:1:16488 :2:82494 :3:82434 :4:49460 :5:16500 :6:98916 :7:32972 :8:16486 :9:98916 :10:24729 :11:74187 :12:32972 :13:16486 :14:98916 :15:24729 :16:74196 :17:82440 :18:164880 :19:65952 :20:32976 :21:32976 :22:24732 :23:115500 :24:24750 :25:41250 :26:16500 :27:152427 :28:406416 :29:57750 :30:16486 :31:32972 :32:49464 :33:32976 :34:32976 :35:32976 :36:66008 :37:33000 :38:16500 :39:49500 :40:16502 :41:24753 :42:8251 :43:24753 :44:8251 :45:16502 :46:24750 :47:140148 :48:98928 :49:16488 :50:90684 :51:90684 :52:16488 :53:16488 :54:16488 :55:8244 :56:24732 :57:32976 :58:41220 :59:742435 :60:123738 :61:82492 :62:82492 :63:206230 :64:164984 :65:206230 :66:164984 :67:9446 :68:18892 :69:14169 :70:14169 :71:37784 :72:9446 :73:33061 :74:9402 :75:123738 :76:329968 :77:365230 :78:1174 :79:7044 :80:2348 :81:2348 :82:1174 :83:2935 :84:5283 :85:3522 :86:1174 :87:2348 :88:69853 :89:12327 :90:8218 :91:16436 :92:3522 :93:1761 :94:5283 :95:329736 :96:82434 :97:164868 :98:164868 :99:82434 :100:1761 :101:2935 :102:164860 :103:123651 :104:162520 :105:487560 :106:2348 :107:1174 :108:1761 :109:1174 :110:123741 :111:371223 :112:123741 :113:123741 :114:82494 :115:206230 :116:98920 :117:64866 :118:101820 :143:2 :119:6216 :120:48 :121:15420 :122:120 :123:10064 :124:2516 :125:3774 :126:82434 :127:82494 :128:82494 :129:329736 :130:82434 :131:82434 :132:74196 :133:49500
|
| 10 |
+
T:1:16542 :2:82648 :3:82710 :4:49626 :5:16528 :6:99252 :7:33084 :8:16542 :9:99252 :10:24813 :11:74439 :12:33084 :13:16542 :14:99252 :15:24813 :16:74439 :17:82710 :18:165420 :19:66168 :20:33084 :21:33084 :22:24813 :23:115682 :24:24789 :25:41315 :26:16526 :27:149181 :28:397880 :29:57841 :30:16542 :31:33084 :32:49626 :33:33084 :34:33084 :35:33084 :36:66104 :37:33056 :38:16528 :39:49578 :40:16526 :41:24789 :42:8263 :43:24789 :44:8263 :45:16526 :46:24792 :47:140607 :48:99252 :49:16542 :50:90981 :51:90981 :52:16542 :53:16542 :54:16542 :55:8271 :56:24813 :57:33084 :58:41355 :59:743814 :144:11 :60:123972 :61:82648 :62:82648 :63:206620 :64:165296 :65:206620 :66:165296 :67:8910 :68:17816 :69:13362 :70:13362 :71:35632 :72:8908 :73:31178 :74:8876 :75:123972 :76:330592 :145:2 :146:3 :147:5 :148:2 :149:3 :150:4 :151:2 :152:3 :153:2 :154:2 :155:2 :156:8 :157:3 :158:8 :159:3 :77:368690 :160:5 :78:1120 :79:6720 :161:5 :80:2240 :81:2240 :162:2 :82:1118 :83:2795 :84:5031 :85:3354 :86:1118 :87:2236 :88:66521 :89:11739 :90:7826 :91:15652 :92:3354 :163:24 :164:12 :165:21 :166:3 :167:3 :168:2 :169:4 :170:3 :171:2 :172:2 :173:2 :174:2 :175:4 :176:2 :93:1677 :94:5040 :177:5 :178:3 :179:4 :180:12 :181:2 :182:3 :183:5 :184:7 :95:330840 :96:82710 :97:165420 :98:165420 :99:82710 :100:1680 :101:2800 :102:165420 :103:124065 :104:163180 :105:489540 :106:2240 :107:1120 :108:1680 :109:1120 :110:123972 :111:371916 :112:123969 :113:123969 :114:82646 :115:206620 :116:99252 :117:64293 :118:100415 :119:6764 :120:32 :121:16830 :122:80 :123:10784 :124:2696 :125:4044 :126:82710 :127:82648 :128:82648 :129:330840 :130:82710 :131:82710 :132:74439 :133:49584
|
| 11 |
+
T:1:16462 :2:82310 :3:82314 :4:49386 :5:16462 :6:98784 :7:32928 :8:16464 :9:98783 :10:24693 :11:74079 :12:32924 :13:16462 :14:98772 :15:24693 :16:74079 :17:82310 :18:164620 :19:65848 :20:32924 :21:32924 :22:24693 :23:115248 :24:24696 :25:41160 :26:16464 :27:145017 :28:386712 :29:57624 :30:16464 :31:32928 :32:49386 :33:32924 :34:32924 :35:32924 :36:65848 :37:32924 :38:16462 :39:49392 :40:16462 :41:24693 :42:8231 :43:24693 :44:8231 :45:16462 :46:24693 :47:139927 :48:98772 :49:16462 :50:90541 :51:90541 :52:16462 :53:16462 :54:16462 :55:8231 :56:24693 :57:32924 :58:41155 :59:740808 :60:123468 :61:82312 :62:82312 :63:205780 :64:164624 :65:205780 :66:164624 :67:10892 :68:21784 :69:16338 :70:16338 :71:43568 :72:10892 :73:38122 :74:10824 :75:123468 :76:329248 :77:357100 :78:1364 :79:8184 :80:2728 :81:2728 :82:1364 :83:3410 :84:6138 :85:4092 :86:1364 :87:2728 :88:81158 :89:14322 :90:9548 :91:19096 :92:4092 :93:2046 :94:6138 :95:329256 :96:82314 :97:164628 :98:164628 :99:82314 :100:2046 :101:3410 :102:164604 :103:123471 :104:161900 :105:485700 :106:2728 :107:1364 :108:2046 :109:1364 :110:123465 :111:370395 :112:123468 :113:123468 :114:82312 :115:205780 :116:98772 :117:63189 :118:95725 :119:7260 :120:136 :121:17810 :122:340 :123:15344 :124:3836 :125:5754 :126:82314 :127:82310 :128:82310 :129:329256 :130:82314 :131:82314 :132:74079 :133:49386
|
| 12 |
+
T:1:16504 :2:82612 :3:82516 :4:49512 :5:16526 :6:99012 :7:33004 :8:16502 :9:99012 :185:1 :10:24756 :11:74268 :12:33008 :13:16504 :14:99024 :15:24756 :16:74268 :17:82520 :18:165040 :19:66016 :20:33008 :21:33008 :22:24756 :23:115682 :24:24789 :25:41315 :26:16526 :27:146832 :28:391456 :29:57841 :30:16502 :31:33004 :32:49512 :33:33008 :34:33008 :35:33008 :36:66112 :37:33052 :38:16526 :39:49578 :40:16528 :41:24792 :42:8264 :43:24792 :44:8264 :45:16526 :46:24789 :47:140284 :48:99024 :49:16504 :50:90772 :51:90772 :52:16504 :53:16504 :54:16504 :55:8252 :56:24756 :57:33008 :58:41260 :59:743508 :60:123918 :61:82612 :62:82612 :63:206530 :64:165224 :65:206530 :66:165224 :67:9740 :68:19476 :69:14607 :70:14607 :71:38952 :72:9738 :73:34083 :74:9684 :75:123918 :76:330446 :145:2 :146:3 :147:5 :148:2 :149:3 :150:4 :151:2 :152:3 :153:2 :154:2 :155:2 :156:8 :157:3 :158:8 :159:3 :77:364360 :160:5 :78:1208 :79:7248 :161:5 :80:2416 :81:2416 :162:2 :82:1206 :83:3015 :84:5427 :85:3618 :86:1206 :87:2412 :88:71757 :89:12663 :90:8442 :91:16884 :92:3618 :163:24 :164:12 :165:21 :166:3 :167:3 :168:2 :169:4 :170:3 :171:2 :172:2 :173:2 :174:2 :175:4 :176:2 :93:1809 :94:5436 :177:5 :178:3 :179:4 :180:12 :181:2 :182:3 :183:5 :184:7 :95:330064 :96:82516 :97:165032 :98:165032 :99:82516 :100:1812 :101:3020 :102:165028 :103:123774 :104:162616 :105:487848 :106:2416 :107:1208 :108:1812 :109:1208 :110:123918 :111:371754 :112:123918 :113:123918 :114:82612 :115:206525 :116:99024 :117:63909 :118:98775 :119:6906 :120:44 :121:17155 :122:110 :123:12384 :124:3096 :125:4644 :126:82516 :127:82612 :128:82612 :129:330064 :130:82516 :131:82516 :132:74268 :133:49578
|
| 13 |
+
T:1:16546 :2:82694 :3:82734 :4:49638 :5:16538 :6:99288 :7:33096 :8:16548 :9:99276 :10:24819 :11:74457 :12:33092 :13:16546 :14:99276 :15:24819 :16:74457 :17:82730 :18:165460 :19:66184 :20:33092 :21:33092 :22:24819 :23:115766 :24:24807 :25:41345 :26:16538 :27:143148 :28:381768 :29:57883 :30:16548 :31:33096 :32:49638 :33:33092 :34:33092 :35:33092 :36:66144 :37:33076 :38:16538 :39:49614 :40:16536 :41:24804 :42:8268 :43:24804 :44:8268 :45:16538 :46:24807 :47:140641 :48:99276 :49:16546 :50:91003 :51:91003 :52:16546 :53:16546 :54:16546 :55:8273 :56:24819 :57:33092 :58:41365 :59:744246 :60:124041 :61:82694 :62:82694 :63:206735 :64:165388 :65:206735 :66:165388 :67:9528 :68:19056 :69:14292 :70:14292 :71:38112 :72:9528 :73:33348 :74:9482 :75:124041 :76:330776 :137:2 :77:365830 :78:1196 :79:7176 :80:2392 :81:2392 :82:1196 :83:2990 :84:5382 :85:3588 :86:1196 :87:2392 :88:71162 :89:12558 :90:8372 :91:16744 :92:3588 :93:1794 :94:5382 :95:330932 :96:82732 :97:165464 :98:165464 :99:82732 :100:1794 :101:2990 :102:165456 :103:124098 :104:163072 :105:489216 :106:2392 :107:1196 :108:1794 :109:1196 :110:124041 :111:372123 :112:124041 :113:124041 :114:82694 :115:206740 :116:99276 :117:63045 :118:96735 :119:7608 :120:56 :121:18880 :122:140 :123:13344 :124:3336 :125:5004 :126:82734 :127:82694 :128:82694 :129:330936 :130:82732 :131:82732 :132:74457 :133:49614
|
| 14 |
+
T:1:16510 :2:82638 :3:82552 :4:49534 :5:16532 :6:99060 :7:33020 :8:16510 :9:99072 :10:24768 :11:74304 :12:33024 :13:16512 :14:99072 :15:24768 :16:74304 :17:82560 :18:165120 :19:66040 :20:33020 :21:33024 :22:24765 :23:115724 :24:24798 :25:41330 :26:16532 :27:138786 :28:370008 :29:57862 :30:16510 :31:33020 :32:49536 :33:33020 :34:33020 :35:33020 :36:66128 :37:33064 :38:16532 :39:49596 :40:16532 :41:24798 :42:8266 :43:24798 :44:8266 :45:16532 :46:24798 :47:140352 :48:99072 :49:16512 :50:90805 :51:90805 :52:16510 :53:16510 :54:16510 :55:8255 :56:24765 :57:33020 :58:41277 :59:743742 :60:123957 :61:82638 :62:82638 :63:206595 :64:165276 :65:206595 :66:165276 :67:10612 :68:21224 :69:15918 :70:15918 :71:42448 :72:10612 :73:37142 :74:10538 :75:123957 :76:330552 :77:360130 :78:1316 :79:7896 :80:2632 :81:2632 :82:1316 :83:3290 :84:5922 :85:3948 :86:1316 :87:2632 :88:78302 :89:13818 :90:9212 :91:18424 :92:3948 :93:1974 :94:5922 :95:330208 :186:4 :96:82554 :97:165108 :98:165108 :99:82554 :100:1974 :101:3290 :102:165080 :103:123831 :104:162476 :105:487428 :106:2632 :107:1316 :108:1974 :109:1316 :110:123957 :111:371871 :112:123957 :113:123957 :114:82638 :115:206595 :116:99068 :117:62142 :118:93560 :119:8106 :120:124 :121:19955 :122:310 :123:16016 :124:4004 :125:6006 :126:82552 :127:82638 :128:82638 :129:330208 :130:82554 :131:82554 :132:74295 :133:49596
|
| 15 |
+
T:1:16502 :2:82448 :3:82504 :4:49502 :5:16486 :6:99000 :7:33000 :8:16500 :9:99000 :10:24750 :11:74250 :12:33000 :13:16500 :14:99000 :15:24750 :16:74250 :17:82500 :18:165000 :19:66008 :20:33004 :21:33000 :22:24753 :23:115402 :24:24729 :25:41215 :26:16486 :27:146694 :28:391240 :29:57701 :30:16500 :31:33000 :32:49500 :33:33004 :34:33004 :35:33004 :36:65952 :37:32972 :38:16486 :39:49458 :40:16488 :41:24732 :42:8244 :43:24729 :44:8243 :45:16486 :46:24729 :47:140250 :48:99000 :49:16500 :50:90761 :51:90761 :52:16502 :53:16502 :54:16502 :55:8251 :56:24753 :57:33004 :58:41250 :187:3 :59:742032 :60:123672 :61:82448 :62:82448 :63:206120 :64:164896 :65:206120 :66:164896 :67:10084 :68:20168 :69:15126 :70:15126 :71:40336 :72:10084 :73:35294 :74:10050 :75:123670 :76:329784 :77:361820 :78:1266 :79:7596 :80:2532 :81:2532 :82:1266 :83:3165 :84:5697 :85:3798 :86:1266 :87:2532 :88:75327 :89:13293 :90:8862 :91:17724 :92:3798 :93:1899 :94:5697 :95:330016 :96:82504 :97:165008 :98:165008 :99:82504 :100:1899 :101:3165 :102:165004 :103:123756 :104:162476 :105:487428 :106:2532 :107:1266 :108:1899 :109:1266 :110:123672 :111:371016 :112:123672 :113:123672 :114:82448 :115:206115 :116:99004 :117:63564 :118:98530 :119:7126 :120:60 :121:17665 :122:150 :123:11856 :124:2964 :125:4446 :126:82504 :127:82448 :128:82448 :129:330016 :130:82504 :131:82504 :132:74259 :133:49458
|
| 16 |
+
T:1:16370 :2:81832 :3:81850 :4:49110 :5:16366 :6:98220 :7:32740 :8:16370 :9:98220 :10:24555 :11:73665 :12:32740 :13:16370 :14:98220 :15:24555 :16:73665 :17:81850 :18:163700 :19:65480 :20:32740 :21:32740 :22:24555 :23:114548 :24:24546 :25:40910 :26:16364 :27:167295 :28:446144 :29:57274 :30:16370 :31:32740 :32:49110 :33:32740 :34:32740 :35:32740 :36:65456 :37:32732 :38:16366 :39:49092 :40:16364 :41:24546 :42:8182 :43:24549 :44:8183 :45:16366 :46:24549 :47:139145 :48:98220 :49:16370 :50:90035 :51:90035 :52:16370 :53:16370 :54:16370 :55:8185 :56:24555 :57:32740 :58:40925 :59:736476 :60:122745 :61:81830 :62:81830 :63:204575 :64:163660 :65:204575 :66:163660 :67:10132 :68:20264 :69:15198 :70:15198 :71:40528 :72:10132 :73:35462 :74:10106 :75:122745 :188:2 :76:327328 :77:358490 :78:1270 :79:7620 :80:2540 :81:2540 :82:1270 :83:3175 :84:5715 :85:3810 :86:1270 :87:2540 :88:75565 :89:13335 :90:8890 :91:17780 :92:3810 :93:1905 :94:5715 :95:327400 :96:81850 :97:163700 :98:163700 :99:81850 :100:1905 :101:3175 :102:163696 :103:122775 :104:161160 :105:483480 :106:2540 :107:1270 :108:1905 :109:1270 :110:122748 :111:368244 :112:122748 :113:122748 :114:81832 :115:204580 :116:98220 :117:67347 :118:109335 :119:4212 :120:12 :121:10500 :122:30 :123:4656 :124:1164 :125:1746 :126:81850 :127:81832 :128:81832 :129:327400 :130:81850 :131:81850 :132:73665 :133:49098
|
| 17 |
+
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|
| 18 |
+
T:1:15360 :2:76826 :3:76798 :4:46080 :5:15366 :6:92160 :7:30720 :8:15360 :9:92160 :10:23040 :11:69120 :12:30720 :13:15360 :14:92160 :15:23040 :16:69120 :17:76800 :18:153600 :19:61440 :20:30720 :21:30720 :22:23040 :23:107562 :24:23049 :25:38415 :26:15366 :27:115395 :28:307688 :29:53781 :30:15358 :31:30720 :32:46080 :33:30720 :34:30720 :35:30720 :36:61472 :37:30732 :38:15366 :39:46098 :40:15368 :41:23052 :42:7684 :43:23049 :44:7683 :45:15366 :46:23049 :47:130560 :48:92160 :49:15360 :50:84480 :51:84480 :52:15360 :53:15360 :54:15360 :55:7680 :56:23040 :57:30720 :58:38400 :59:691434 :60:115239 :61:76826 :62:76826 :63:192065 :64:153652 :65:192065 :66:153652 :67:5934 :68:11868 :69:8901 :70:8901 :71:23736 :72:5934 :73:20769 :74:5930 :75:115239 :76:307304 :77:354460 :78:740 :79:4440 :80:1480 :81:1480 :82:740 :83:1850 :84:3330 :85:2220 :86:740 :87:1480 :88:44030 :89:7770 :90:5180 :91:10360 :92:2220 :93:1110 :94:3330 :95:307192 :190:6 :96:76800 :97:153600 :98:153600 :99:76800 :100:1110 :101:1850 :102:153548 :103:115200 :104:152120 :105:456360 :106:1480 :107:740 :108:1110 :109:740 :110:115239 :111:345717 :112:115239 :113:115239 :114:76826 :115:192063 :116:92160 :117:54726 :118:76200 :119:9596 :120:236 :121:23400 :122:590 :123:24016 :124:6004 :125:9006 :126:76798 :127:76826 :128:76826 :129:307192 :130:76800 :131:76800 :132:69120 :133:46098
|
tsp/fingerprint/pieces/segment.0
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
+
T:140737284461024:16450 :140737284461168:82306 :140737284461184:82244 :140737284461296:49346 :140737284461312:16464 :140737284464176:98688 :140737284464218:32896 :140737284464240:16448 :140737284464248:98688 :140737284464289:24672 :140737284464300:74016 :140737284464340:32896 :140737284464362:16448 :140737284464370:98688 :140737284464412:24672 :140737284464423:74016 :140737284465360:82240 :140737284465397:164480 :140737284465489:65800 :140737284465522:32900 :140737284465536:32896 :140737284465552:24675 :140737284465600:115248 :140737284465643:24695 :140737284465658:41155 :140737284465678:16462 :140737284465688:171276 :140737284465697:456680 :140737284465703:57617 :140737284465727:16448 :140737284465737:32896 :140737284465751:49344 :140737284465774:32900 :140737284465792:32900 :140737284465809:32900 :140737284465823:65856 :140737284466025:32928 :140737284466042:16464 :140737284466050:49392 :140737284466070:16464 :140737284466075:24696 :140737284466085:8232 :140737284466090:24696 :140737284466099:8232 :140737284466104:16464 :140737284466112:24696 :140737284466512:139808 :140737284466569:98688 :140737284466610:16448 :140737284466623:90475 :140737284466674:90475 :140737284466704:16450 :140737284466712:16450 :140737284466717:16450 :140737284466725:8225 :140737284466770:24675 :140737284466782:32900 :140737284466800:41125 :140737338431136:740754 :140737338431195:123459 :140737338431208:82306 :140737338431218:82306 :140737338431227:205765 :140737338431246:164612 :140737338431263:205765 :140737338431291:164612 :140737338431307:7792 :140737338431320:15584 :140737338431339:11688 :140737338431357:11688 :140737338431371:31168 :140737338431410:7792 :140737338431419:27272 :140737338431443:7792 :140737338431464:123459 :140737338431484:329224 :140737338432000:372570 :140737338436016:968 :140737338436025:5808 :140737338436344:1936 :140737338436360:1936 :140737338436612:968 :140737338436621:2420 :140737338436644:4356 :140737338436678:2904 :140737338436707:968 :140737338436720:1936 :140737338436752:57596 :140737338436827:10164 :140737338436840:6776 :140737338436849:13552 :140737338436960:2904 :140737338437740:1452 :140737338437750:4356 :140737338441888:328976 :140737338441916:82244 :140737338441925:164488 :140737338441942:164488 :140737338441962:82244 :140737338441975:1452 :140737338442146:2420 :140737338442160:164488 :140737338442240:123366 :140737338442254:162552 :140737338442271:487656 :140737338442320:1936 :140737338442338:968 :140737338442347:1452 :140737338442360:968 :140737338442720:123459 :140737338442733:370377 :140737338442761:123459 :140737338442779:123459 :140737338442828:82306 :140737338442835:205765 :140737339471856:98692 :140737339471873:67980 :140737339471887:110600 :140737339472048:4026 :140737339472053:10 :140737339472098:10040 :140737339472128:25 :140737339472145:4320 :140737339472205:1080 :140737339472214:1620 :140737340682448:82244 :140737340685104:82306 :140737340738576:82306 :140737340746096:328976 :140737340746124:82244 :140737340746129:82244 :140737340816768:74025 :140737340816816:49392
|
tsp/fingerprint/pieces/segment.1
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
+
T:140737284461024:16394 :140737284461168:81946 :140737284461184:81978 :140737284461296:49186 :140737284461312:16388 :140737284464176:98376 :140737284464218:32792 :140737284464240:16396 :140737284464248:98376 :140737284464289:24594 :140737284464300:73782 :140737284464340:32792 :140737284464362:16396 :140737284464370:98376 :140737284464412:24594 :140737284464423:73782 :140737284465360:81980 :140737284465397:163960 :140737284465489:65576 :140737284465522:32788 :140737284465536:32792 :140737284465552:24591 :140737284465600:114716 :140737284465643:24582 :140737284465652:1 :140737284465658:40975 :140737284465678:16390 :140737284465688:174543 :140737284465697:465472 :140737284465703:57365 :140737284465727:16396 :140737284465737:32792 :140737284465751:49188 :140737284465774:32788 :140737284465792:32788 :140737284465809:32788 :140737284465823:65552 :140737284466025:32776 :140737284466042:16388 :140737284466050:49164 :140737284466070:16388 :140737284466075:24582 :140737284466085:8194 :140737284466090:24582 :140737284466099:8194 :140737284466104:16388 :140737284466112:24582 :140737284466512:139366 :140737284466569:98376 :140737284466610:16396 :140737284466623:90167 :140737284466674:90167 :140737284466704:16394 :140737284466712:16394 :140737284466717:16394 :140737284466725:8197 :140737284466770:24594 :140737284466782:32788 :140737284466800:40990 :140737338431136:737514 :140737338431195:122919 :140737338431208:81946 :140737338431218:81946 :140737338431227:204865 :140737338431246:163892 :140737338431263:204865 :140737338431291:163892 :140737338431307:8636 :140737338431320:17272 :140737338431339:12954 :140737338431357:12954 :140737338431371:34544 :140737338431410:8636 :140737338431419:30226 :140737338431443:8634 :140737338431464:122919 :140737338431484:327784 :140737338432000:366550 :140737338436016:1080 :140737338436025:6480 :140737338436344:2160 :140737338436360:2160 :140737338436612:1080 :140737338436621:2700 :140737338436644:4860 :140737338436678:3240 :140737338436707:1080 :140737338436720:2160 :140737338436752:64260 :140737338436827:11340 :140737338436840:7560 :140737338436849:15120 :140737338436960:3240 :140737338437740:1620 :140737338437750:4860 :140737338441888:327911 :140737338441916:81976 :140737338441925:163952 :140737338441942:163952 :140737338441962:81976 :140737338441975:1620 :140737338442146:2700 :140737338442160:163952 :140737338442240:122964 :140737338442254:161792 :140737338442271:485376 :140737338442320:2160 :140737338442338:1080 :140737338442347:1620 :140737338442360:1080 :140737338442720:122919 :140737338442733:368757 :140737338442761:122919 :140737338442779:122919 :140737338442828:81946 :140737338442835:204865 :140737339471856:98372 :140737339471873:67884 :140737339471887:110545 :140737339472048:3930 :140737339472053:10 :140737339472098:9800 :140737339472128:25 :140737339472145:4152 :140737339472205:1038 :140737339472214:1557 :140737340682448:81978 :140737340685104:81946 :140737340738576:81946 :140737340746096:327912 :140737340746124:81976 :140737340746129:81976 :140737340816768:73773 :140737340816816:49164
|
tsp/fingerprint/pieces/segment.10
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
+
T:140737284461024:16462 :140737284461168:82310 :140737284461184:82314 :140737284461296:49386 :140737284461312:16462 :140737284464176:98784 :140737284464218:32928 :140737284464240:16464 :140737284464248:98783 :140737284464289:24693 :140737284464300:74079 :140737284464340:32924 :140737284464362:16462 :140737284464370:98772 :140737284464412:24693 :140737284464423:74079 :140737284465360:82310 :140737284465397:164620 :140737284465489:65848 :140737284465522:32924 :140737284465536:32924 :140737284465552:24693 :140737284465600:115248 :140737284465643:24696 :140737284465658:41160 :140737284465678:16464 :140737284465688:145017 :140737284465697:386712 :140737284465703:57624 :140737284465727:16464 :140737284465737:32928 :140737284465751:49386 :140737284465774:32924 :140737284465792:32924 :140737284465809:32924 :140737284465823:65848 :140737284466025:32924 :140737284466042:16462 :140737284466050:49392 :140737284466070:16462 :140737284466075:24693 :140737284466085:8231 :140737284466090:24693 :140737284466099:8231 :140737284466104:16462 :140737284466112:24693 :140737284466512:139927 :140737284466569:98772 :140737284466610:16462 :140737284466623:90541 :140737284466674:90541 :140737284466704:16462 :140737284466712:16462 :140737284466717:16462 :140737284466725:8231 :140737284466770:24693 :140737284466782:32924 :140737284466800:41155 :140737338431136:740808 :140737338431195:123468 :140737338431208:82312 :140737338431218:82312 :140737338431227:205780 :140737338431246:164624 :140737338431263:205780 :140737338431291:164624 :140737338431307:10892 :140737338431320:21784 :140737338431339:16338 :140737338431357:16338 :140737338431371:43568 :140737338431410:10892 :140737338431419:38122 :140737338431443:10824 :140737338431464:123468 :140737338431484:329248 :140737338432000:357100 :140737338436016:1364 :140737338436025:8184 :140737338436344:2728 :140737338436360:2728 :140737338436612:1364 :140737338436621:3410 :140737338436644:6138 :140737338436678:4092 :140737338436707:1364 :140737338436720:2728 :140737338436752:81158 :140737338436827:14322 :140737338436840:9548 :140737338436849:19096 :140737338436960:4092 :140737338437740:2046 :140737338437750:6138 :140737338441888:329256 :140737338441916:82314 :140737338441925:164628 :140737338441942:164628 :140737338441962:82314 :140737338441975:2046 :140737338442146:3410 :140737338442160:164604 :140737338442240:123471 :140737338442254:161900 :140737338442271:485700 :140737338442320:2728 :140737338442338:1364 :140737338442347:2046 :140737338442360:1364 :140737338442720:123465 :140737338442733:370395 :140737338442761:123468 :140737338442779:123468 :140737338442828:82312 :140737338442835:205780 :140737339471856:98772 :140737339471873:63189 :140737339471887:95725 :140737339472048:7260 :140737339472053:136 :140737339472098:17810 :140737339472128:340 :140737339472145:15344 :140737339472205:3836 :140737339472214:5754 :140737340682448:82314 :140737340685104:82310 :140737340738576:82310 :140737340746096:329256 :140737340746124:82314 :140737340746129:82314 :140737340816768:74079 :140737340816816:49386
|
tsp/fingerprint/pieces/segment.11
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
+
T:140737284461024:16504 :140737284461168:82612 :140737284461184:82516 :140737284461296:49512 :140737284461312:16526 :140737284464176:99012 :140737284464218:33004 :140737284464240:16502 :140737284464248:99012 :140737284464287:1 :140737284464289:24756 :140737284464300:74268 :140737284464340:33008 :140737284464362:16504 :140737284464370:99024 :140737284464412:24756 :140737284464423:74268 :140737284465360:82520 :140737284465397:165040 :140737284465489:66016 :140737284465522:33008 :140737284465536:33008 :140737284465552:24756 :140737284465600:115682 :140737284465643:24789 :140737284465658:41315 :140737284465678:16526 :140737284465688:146832 :140737284465697:391456 :140737284465703:57841 :140737284465727:16502 :140737284465737:33004 :140737284465751:49512 :140737284465774:33008 :140737284465792:33008 :140737284465809:33008 :140737284465823:66112 :140737284466025:33052 :140737284466042:16526 :140737284466050:49578 :140737284466070:16528 :140737284466075:24792 :140737284466085:8264 :140737284466090:24792 :140737284466099:8264 :140737284466104:16526 :140737284466112:24789 :140737284466512:140284 :140737284466569:99024 :140737284466610:16504 :140737284466623:90772 :140737284466674:90772 :140737284466704:16504 :140737284466712:16504 :140737284466717:16504 :140737284466725:8252 :140737284466770:24756 :140737284466782:33008 :140737284466800:41260 :140737338431136:743508 :140737338431195:123918 :140737338431208:82612 :140737338431218:82612 :140737338431227:206530 :140737338431246:165224 :140737338431263:206530 :140737338431291:165224 :140737338431307:9740 :140737338431320:19476 :140737338431339:14607 :140737338431357:14607 :140737338431371:38952 :140737338431410:9738 :140737338431419:34083 :140737338431443:9684 :140737338431464:123918 :140737338431484:330446 :140737338431504:2 :140737338431514:3 :140737338431536:5 :140737338431563:2 :140737338431575:3 :140737338431587:4 :140737338431604:2 :140737338431618:3 :140737338431632:2 :140737338431673:2 :140737338431684:2 :140737338431696:8 :140737338431735:3 :140737338431752:8 :140737338431790:3 :140737338432000:364360 :140737338433104:5 :140737338436016:1208 :140737338436025:7248 :140737338436102:5 :140737338436344:2416 :140737338436360:2416 :140737338436380:2 :140737338436612:1206 :140737338436621:3015 :140737338436644:5427 :140737338436678:3618 :140737338436707:1206 :140737338436720:2412 :140737338436752:71757 :140737338436827:12663 :140737338436840:8442 :140737338436849:16884 :140737338436960:3618 :140737338437096:24 :140737338437220:12 :140737338437280:21 :140737338437378:3 :140737338437394:3 :140737338437408:2 :140737338437417:4 :140737338437433:3 :140737338437447:2 :140737338437457:2 :140737338437466:2 :140737338437475:2 :140737338437484:4 :140737338437683:2 :140737338437740:1809 :140737338437750:5436 :140737338437872:5 :140737338437897:3 :140737338437909:4 :140737338438368:12 :140737338438528:2 :140737338439000:3 :140737338439485:5 :140737338439508:7 :140737338441888:330064 :140737338441916:82516 :140737338441925:165032 :140737338441942:165032 :140737338441962:82516 :140737338441975:1812 :140737338442146:3020 :140737338442160:165028 :140737338442240:123774 :140737338442254:162616 :140737338442271:487848 :140737338442320:2416 :140737338442338:1208 :140737338442347:1812 :140737338442360:1208 :140737338442720:123918 :140737338442733:371754 :140737338442761:123918 :140737338442779:123918 :140737338442828:82612 :140737338442835:206525 :140737339471856:99024 :140737339471873:63909 :140737339471887:98775 :140737339472048:6906 :140737339472053:44 :140737339472098:17155 :140737339472128:110 :140737339472145:12384 :140737339472205:3096 :140737339472214:4644 :140737340682448:82516 :140737340685104:82612 :140737340738576:82612 :140737340746096:330064 :140737340746124:82516 :140737340746129:82516 :140737340816768:74268 :140737340816816:49578
|
tsp/fingerprint/pieces/segment.12
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
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|
tsp/fingerprint/pieces/segment.13
ADDED
|
@@ -0,0 +1 @@
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|
|
|
|
|
|
| 1 |
+
T:140737284461024:16510 :140737284461168:82638 :140737284461184:82552 :140737284461296:49534 :140737284461312:16532 :140737284464176:99060 :140737284464218:33020 :140737284464240:16510 :140737284464248:99072 :140737284464289:24768 :140737284464300:74304 :140737284464340:33024 :140737284464362:16512 :140737284464370:99072 :140737284464412:24768 :140737284464423:74304 :140737284465360:82560 :140737284465397:165120 :140737284465489:66040 :140737284465522:33020 :140737284465536:33024 :140737284465552:24765 :140737284465600:115724 :140737284465643:24798 :140737284465658:41330 :140737284465678:16532 :140737284465688:138786 :140737284465697:370008 :140737284465703:57862 :140737284465727:16510 :140737284465737:33020 :140737284465751:49536 :140737284465774:33020 :140737284465792:33020 :140737284465809:33020 :140737284465823:66128 :140737284466025:33064 :140737284466042:16532 :140737284466050:49596 :140737284466070:16532 :140737284466075:24798 :140737284466085:8266 :140737284466090:24798 :140737284466099:8266 :140737284466104:16532 :140737284466112:24798 :140737284466512:140352 :140737284466569:99072 :140737284466610:16512 :140737284466623:90805 :140737284466674:90805 :140737284466704:16510 :140737284466712:16510 :140737284466717:16510 :140737284466725:8255 :140737284466770:24765 :140737284466782:33020 :140737284466800:41277 :140737338431136:743742 :140737338431195:123957 :140737338431208:82638 :140737338431218:82638 :140737338431227:206595 :140737338431246:165276 :140737338431263:206595 :140737338431291:165276 :140737338431307:10612 :140737338431320:21224 :140737338431339:15918 :140737338431357:15918 :140737338431371:42448 :140737338431410:10612 :140737338431419:37142 :140737338431443:10538 :140737338431464:123957 :140737338431484:330552 :140737338432000:360130 :140737338436016:1316 :140737338436025:7896 :140737338436344:2632 :140737338436360:2632 :140737338436612:1316 :140737338436621:3290 :140737338436644:5922 :140737338436678:3948 :140737338436707:1316 :140737338436720:2632 :140737338436752:78302 :140737338436827:13818 :140737338436840:9212 :140737338436849:18424 :140737338436960:3948 :140737338437740:1974 :140737338437750:5922 :140737338441888:330208 :140737338441898:4 :140737338441916:82554 :140737338441925:165108 :140737338441942:165108 :140737338441962:82554 :140737338441975:1974 :140737338442146:3290 :140737338442160:165080 :140737338442240:123831 :140737338442254:162476 :140737338442271:487428 :140737338442320:2632 :140737338442338:1316 :140737338442347:1974 :140737338442360:1316 :140737338442720:123957 :140737338442733:371871 :140737338442761:123957 :140737338442779:123957 :140737338442828:82638 :140737338442835:206595 :140737339471856:99068 :140737339471873:62142 :140737339471887:93560 :140737339472048:8106 :140737339472053:124 :140737339472098:19955 :140737339472128:310 :140737339472145:16016 :140737339472205:4004 :140737339472214:6006 :140737340682448:82552 :140737340685104:82638 :140737340738576:82638 :140737340746096:330208 :140737340746124:82554 :140737340746129:82554 :140737340816768:74295 :140737340816816:49596
|
tsp/fingerprint/pieces/segment.14
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
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|
tsp/fingerprint/pieces/segment.15
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
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T:140737284461024:16370 :140737284461168:81832 :140737284461184:81850 :140737284461296:49110 :140737284461312:16366 :140737284464176:98220 :140737284464218:32740 :140737284464240:16370 :140737284464248:98220 :140737284464289:24555 :140737284464300:73665 :140737284464340:32740 :140737284464362:16370 :140737284464370:98220 :140737284464412:24555 :140737284464423:73665 :140737284465360:81850 :140737284465397:163700 :140737284465489:65480 :140737284465522:32740 :140737284465536:32740 :140737284465552:24555 :140737284465600:114548 :140737284465643:24546 :140737284465658:40910 :140737284465678:16364 :140737284465688:167295 :140737284465697:446144 :140737284465703:57274 :140737284465727:16370 :140737284465737:32740 :140737284465751:49110 :140737284465774:32740 :140737284465792:32740 :140737284465809:32740 :140737284465823:65456 :140737284466025:32732 :140737284466042:16366 :140737284466050:49092 :140737284466070:16364 :140737284466075:24546 :140737284466085:8182 :140737284466090:24549 :140737284466099:8183 :140737284466104:16366 :140737284466112:24549 :140737284466512:139145 :140737284466569:98220 :140737284466610:16370 :140737284466623:90035 :140737284466674:90035 :140737284466704:16370 :140737284466712:16370 :140737284466717:16370 :140737284466725:8185 :140737284466770:24555 :140737284466782:32740 :140737284466800:40925 :140737338431136:736476 :140737338431195:122745 :140737338431208:81830 :140737338431218:81830 :140737338431227:204575 :140737338431246:163660 :140737338431263:204575 :140737338431291:163660 :140737338431307:10132 :140737338431320:20264 :140737338431339:15198 :140737338431357:15198 :140737338431371:40528 :140737338431410:10132 :140737338431419:35462 :140737338431443:10106 :140737338431464:122745 :140737338431469:2 :140737338431484:327328 :140737338432000:358490 :140737338436016:1270 :140737338436025:7620 :140737338436344:2540 :140737338436360:2540 :140737338436612:1270 :140737338436621:3175 :140737338436644:5715 :140737338436678:3810 :140737338436707:1270 :140737338436720:2540 :140737338436752:75565 :140737338436827:13335 :140737338436840:8890 :140737338436849:17780 :140737338436960:3810 :140737338437740:1905 :140737338437750:5715 :140737338441888:327400 :140737338441916:81850 :140737338441925:163700 :140737338441942:163700 :140737338441962:81850 :140737338441975:1905 :140737338442146:3175 :140737338442160:163696 :140737338442240:122775 :140737338442254:161160 :140737338442271:483480 :140737338442320:2540 :140737338442338:1270 :140737338442347:1905 :140737338442360:1270 :140737338442720:122748 :140737338442733:368244 :140737338442761:122748 :140737338442779:122748 :140737338442828:81832 :140737338442835:204580 :140737339471856:98220 :140737339471873:67347 :140737339471887:109335 :140737339472048:4212 :140737339472053:12 :140737339472098:10500 :140737339472128:30 :140737339472145:4656 :140737339472205:1164 :140737339472214:1746 :140737340682448:81850 :140737340685104:81832 :140737340738576:81832 :140737340746096:327400 :140737340746124:81850 :140737340746129:81850 :140737340816768:73665 :140737340816816:49098
|
tsp/fingerprint/pieces/segment.16
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
+
T:140737284461024:16590 :140737284461168:82974 :140737284461184:82952 :140737284461296:49770 :140737284461312:16596 :140737284464176:99540 :140737284464218:33180 :140737284464240:16590 :140737284464248:99540 :140737284464289:24885 :140737284464300:74655 :140737284464340:33180 :140737284464362:16590 :140737284464370:99540 :140737284464412:24885 :140737284464423:74655 :140737284465360:82950 :140737284465397:165900 :140737284465489:66360 :140737284465522:33180 :140737284465536:33180 :140737284465552:24885 :140737284465600:116186 :140737284465643:24897 :140737284465658:41495 :140737284465678:16598 :140737284465688:158736 :140737284465697:423272 :140737284465703:58093 :140737284465727:16592 :140737284465737:33180 :140737284465751:49770 :140737284465774:33180 :140737284465792:33180 :140737284465809:33180 :140737284465823:66384 :140737284466025:33192 :140737284466042:16596 :140737284466050:49794 :140737284466070:16596 :140737284466075:24894 :140737284466085:8298 :140737284466090:24894 :140737284466099:8298 :140737284466104:16596 :140737284466112:24894 :140737284466512:141015 :140737284466569:99540 :140737284466610:16590 :140737284466623:91245 :140737284466674:91245 :140737284466704:16590 :140737284466712:16590 :140737284466717:16590 :140737284466725:8295 :140737284466770:24885 :140737284466782:33180 :140737284466800:41475 :140737338431136:746766 :140737338431148:12 :140737338431195:124464 :140737338431208:82976 :140737338431218:82976 :140737338431227:207440 :140737338431246:165952 :140737338431263:207440 :140737338431291:165952 :140737338431307:6612 :140737338431320:13224 :140737338431339:9918 :140737338431357:9918 :140737338431371:26448 :140737338431410:6612 :140737338431419:23142 :140737338431443:6610 :140737338431464:124464 :140737338431484:331904 :140737338432000:381820 :140737338436016:820 :140737338436025:4920 :140737338436344:1640 :140737338436360:1640 :140737338436612:820 :140737338436621:2050 :140737338436644:3690 :140737338436678:2460 :140737338436707:820 :140737338436720:1640 :140737338436752:48790 :140737338436827:8610 :140737338436840:5740 :140737338436849:11480 :140737338436960:2460 :140737338437740:1230 :140737338437750:3690 :140737338441888:331802 :140737338441916:82950 :140737338441925:165900 :140737338441942:165900 :140737338441962:82950 :140737338441975:1230 :140737338442146:2050 :140737338442160:165900 :140737338442240:124425 :140737338442254:164260 :140737338442271:492780 :140737338442320:1640 :140737338442338:820 :140737338442347:1230 :140737338442360:820 :140737338442720:124461 :140737338442733:373383 :140737338442761:124461 :140737338442779:124461 :140737338442828:82974 :140737338442835:207440 :140737339471856:99540 :140737339471873:66681 :140737339471887:107775 :140737339472048:5316 :140737339472053:12 :140737339472098:13260 :140737339472128:30 :140737339472145:5376 :140737339472205:1344 :140737339472214:2016 :140737340682448:82952 :140737340685104:82974 :140737340738576:82974 :140737340746096:331808 :140737340746124:82950 :140737340746129:82950 :140737340816768:74655 :140737340816816:49788
|
tsp/fingerprint/pieces/segment.17
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
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|
tsp/fingerprint/pieces/segment.2
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
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T:140737284461024:16444 :140737284461168:82028 :140737284461184:82212 :140737284461296:49328 :140737284461312:16396 :140737284464176:98652 :140737284464218:32884 :140737284464240:16442 :140737284464248:98652 :140737284464289:24663 :140737284464300:73989 :140737284464340:32884 :140737284464362:16442 :140737284464370:98652 :140737284464412:24663 :140737284464423:73989 :140737284465360:82210 :140737284465397:164420 :140737284465489:65776 :140737284465522:32888 :140737284465536:32884 :140737284465552:24666 :140737284465600:114758 :140737284465643:24591 :140737284465658:40985 :140737284465678:16394 :140737284465688:166272 :140737284465697:443584 :140737284465703:57379 :140737284465727:16442 :140737284465737:32884 :140737284465751:49326 :140737284465774:32888 :140737284465792:32888 :140737284465809:32888 :140737284465823:65584 :140737284466025:32792 :140737284466042:16396 :140737284466050:49182 :140737284466070:16396 :140737284466075:24594 :140737284466085:8198 :140737284466090:24594 :140737284466099:8198 :140737284466104:16396 :140737284466112:24594 :140737284466512:139757 :140737284466569:98652 :140737284466610:16442 :140737284466623:90442 :140737284466674:90442 :140737284466704:16444 :140737284466712:16444 :140737284466717:16444 :140737284466725:8222 :140737284466770:24663 :140737284466782:32888 :140737284466800:41105 :140737338431136:738252 :140737338431195:123042 :140737338431208:82028 :140737338431218:82028 :140737338431227:205070 :140737338431246:164056 :140737338431263:205070 :140737338431291:164056 :140737338431307:8940 :140737338431320:17880 :140737338431339:13410 :140737338431357:13410 :140737338431371:35760 :140737338431410:8940 :140737338431419:31290 :140737338431443:8936 :140737338431464:123042 :140737338431484:328110 :140737338432000:365440 :140737338436016:1144 :140737338436025:6864 :140737338436344:2288 :140737338436360:2288 :140737338436612:1144 :140737338436621:2860 :140737338436644:5148 :140737338436678:3432 :140737338436707:1144 :140737338436720:2288 :140737338436752:68068 :140737338436827:12012 :140737338436840:8008 :140737338436849:16016 :140737338436960:3432 :140737338437740:1716 :140737338437750:5148 :140737338441888:328848 :140737338441910:1 :140737338441916:82214 :140737338441925:164428 :140737338441942:164428 :140737338441962:82214 :140737338441975:1716 :140737338442146:2860 :140737338442160:164424 :140737338442240:123321 :140737338442254:162140 :140737338442271:486420 :140737338442320:2288 :140737338442338:1144 :140737338442347:1716 :140737338442360:1144 :140737338442720:123042 :140737338442733:369126 :140737338442761:123042 :140737338442779:123042 :140737338442828:82028 :140737338442835:205065 :140737339471856:98656 :140737339471873:66669 :140737339471887:107370 :140737339472048:4882 :140737339472053:28 :140737339472098:12135 :140737339472128:70 :140737339472145:5992 :140737339472205:1498 :140737339472214:2247 :140737340682448:82212 :140737340685104:82028 :140737340738576:82028 :140737340746096:328848 :140737340746124:82214 :140737340746129:82214 :140737340816768:73998 :140737340816816:49188
|
tsp/fingerprint/pieces/segment.3
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
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T:140737284461024:16662 :140737284461168:83246 :140737284461184:83314 :140737284461296:49986 :140737284461312:16646 :140737284464176:99984 :140737284464218:33328 :140737284464240:16664 :140737284464248:99972 :140737284464289:24993 :140737284464300:74979 :140737284464340:33324 :140737284464362:16662 :140737284464370:99972 :140737284464412:24993 :140737284464423:74979 :140737284465360:83310 :140737284465397:166620 :140737284465489:66648 :140737284465522:33324 :140737284465536:33324 :140737284465552:24993 :140737284465600:116536 :140737284465643:24969 :140737284465658:41615 :140737284465678:16646 :140737284465688:136782 :140737284465697:364824 :140737284465703:58261 :140737284465727:16664 :140737284465737:33328 :140737284465751:49986 :140737284465774:33324 :140737284465792:33324 :140737284465809:33324 :140737284465823:66584 :140737284465840:7 :140737284466025:33292 :140737284466042:16646 :140737284466050:49944 :140737284466070:16646 :140737284466075:24969 :140737284466085:8323 :140737284466090:24969 :140737284466099:8323 :140737284466104:16646 :140737284466112:24969 :140737284466512:141627 :140737284466569:99972 :140737284466610:16662 :140737284466623:91641 :140737284466674:91641 :140737284466704:16662 :140737284466712:16662 :140737284466717:16662 :140737284466725:8331 :140737284466770:24993 :140737284466782:33324 :140737284466800:41655 :140737338431136:749214 :140737338431195:124869 :140737338431208:83246 :140737338431218:83246 :140737338431227:208115 :140737338431246:166492 :140737338431263:208115 :140737338431291:166492 :140737338431307:7746 :140737338431320:15492 :140737338431339:11619 :140737338431357:11619 :140737338431371:30984 :140737338431410:7746 :140737338431419:27111 :140737338431443:7708 :140737338431464:124869 :140737338431484:332984 :140737338431496:2 :140737338432000:377500 :140737338436016:974 :140737338436025:5844 :140737338436344:1948 :140737338436360:1948 :140737338436612:974 :140737338436621:2435 :140737338436644:4383 :140737338436678:2922 :140737338436707:974 :140737338436720:1948 :140737338436752:57953 :140737338436827:10227 :140737338436840:6818 :140737338436849:13636 :140737338436960:2922 :140737338437740:1461 :140737338437750:4383 :140737338441888:333256 :140737338441916:83314 :140737338441925:166627 :140737338441942:166624 :140737338441962:83312 :140737338441975:1461 :140737338442146:2435 :140737338442160:166556 :140737338442240:124968 :140737338442254:164676 :140737338442271:494028 :140737338442320:1948 :140737338442338:974 :140737338442347:1461 :140737338442360:974 :140737338442720:124869 :140737338442733:374607 :140737338442761:124869 :140737338442779:124869 :140737338442828:83246 :140737338442835:208120 :140737339471856:99972 :140737339471873:62235 :140737339471887:90795 :140737339472048:8496 :140737339472053:270 :140737339472058:2 :140737339472085:5 :140737339472098:20565 :140737339472128:670 :140737339472145:20688 :140737339472205:5172 :140737339472214:7758 :140737340682448:83314 :140737340685104:83246 :140737340738576:83246 :140737340746096:333256 :140737340746124:83312 :140737340746129:83312 :140737340816768:74979 :140737340816816:49938
|
tsp/fingerprint/pieces/segment.4
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
+
T:140737284461024:16638 :140737284461168:83238 :140737284461184:83186 :140737284461296:49914 :140737284461312:16650 :140737284464176:99816 :140737284464218:33272 :140737284464240:16636 :140737284464248:99828 :140737284464289:24957 :140737284464300:74871 :140737284464340:33276 :140737284464362:16638 :140737284464370:99828 :140737284464412:24957 :140737284464423:74871 :140737284465360:83190 :140737284465397:166380 :140737284465489:66552 :140737284465522:33276 :140737284465536:33276 :140737284465552:24957 :140737284465600:116550 :140737284465643:24975 :140737284465658:41625 :140737284465678:16650 :140737284465688:134679 :140737284465697:359089 :140737284465703:58275 :140737284465727:16636 :140737284465737:33272 :140737284465751:49914 :140737284465774:33276 :140737284465792:33276 :140737284465809:33276 :140737284465823:66600 :140737284466025:33300 :140737284466042:16650 :140737284466050:49950 :140737284466070:16650 :140737284466075:24975 :140737284466085:8325 :140737284466090:24975 :140737284466099:8325 :140737284466104:16650 :140737284466112:24975 :140737284466512:141423 :140737284466569:99828 :140737284466610:16638 :140737284466623:91509 :140737284466674:91509 :140737284466704:16638 :140737284466712:16638 :140737284466717:16638 :140737284466725:8319 :140737284466770:24957 :140737284466782:33276 :140737284466800:41595 :140737338431136:749142 :140737338431195:124857 :140737338431208:83238 :140737338431218:83238 :140737338431227:208095 :140737338431246:166476 :140737338431263:208095 :140737338431291:166476 :140737338431307:8368 :140737338431320:16736 :140737338431339:12552 :140737338431357:12552 :140737338431371:33472 :140737338431410:8368 :140737338431419:29288 :140737338431443:8346 :140737338431464:124857 :140737338431484:332952 :140737338432000:374350 :140737338436016:1042 :140737338436025:6252 :140737338436344:2084 :140737338436360:2084 :140737338436612:1042 :140737338436621:2605 :140737338436644:4689 :140737338436678:3126 :140737338436707:1042 :140737338436720:2084 :140737338436752:61999 :140737338436827:10941 :140737338436840:7294 :140737338436849:14588 :140737338436960:3126 :140737338437740:1563 :140737338437750:4689 :140737338441888:332744 :140737338441916:83186 :140737338441925:166372 :140737338441936:1 :140737338441942:166376 :140737338441962:83188 :140737338441975:1563 :140737338442146:2605 :140737338442160:166340 :140737338442240:124782 :140737338442254:164292 :140737338442271:492876 :140737338442320:2084 :140737338442338:1042 :140737338442347:1563 :140737338442360:1042 :140737338442720:124857 :140737338442733:374571 :140737338442761:124857 :140737338442779:124857 :140737338442828:83238 :140737338442835:208095 :140737339471856:99828 :140737339471873:61242 :140737339471887:88960 :140737339472048:9086 :140737339472053:198 :140737339472098:22220 :140737339472128:495 :140737339472145:20976 :140737339472205:5244 :140737339472214:7866 :140737340682448:83186 :140737340685104:83238 :140737340738576:83238 :140737340746096:332744 :140737340746124:83188 :140737340746129:83188 :140737340816768:74871 :140737340816816:49950
|
tsp/fingerprint/pieces/segment.5
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
+
T:140737284461024:16758 :140737284461168:83768 :140737284461184:83790 :140737284461296:50274 :140737284461312:16752 :140737284464176:100548 :140737284464218:33516 :140737284464240:16758 :140737284464248:100548 :140737284464289:25137 :140737284464300:75411 :140737284464340:33516 :140737284464362:16758 :140737284464370:100548 :140737284464412:25137 :140737284464423:75411 :140737284465360:83790 :140737284465397:167580 :140737284465489:67032 :140737284465522:33516 :140737284465536:33516 :140737284465552:25137 :140737284465600:117264 :140737284465643:25128 :140737284465658:41880 :140737284465678:16752 :140737284465688:118680 :140737284465697:316496 :140737284465703:58639 :140737284465727:16758 :140737284465737:33516 :140737284465751:50274 :140737284465774:33516 :140737284465792:33516 :140737284465809:33516 :140737284465823:67016 :140737284466025:33504 :140737284466042:16752 :140737284466050:50256 :140737284466070:16754 :140737284466075:25131 :140737284466085:8377 :140737284466090:25128 :140737284466099:8376 :140737284466104:16752 :140737284466112:25128 :140737284466512:142443 :140737284466569:100548 :140737284466610:16758 :140737284466623:92169 :140737284466674:92169 :140737284466704:16758 :140737284466712:16758 :140737284466717:16758 :140737284466725:8379 :140737284466770:25137 :140737284466782:33516 :140737284466800:41895 :140737338431136:753908 :140737338431195:125649 :140737338431208:83766 :140737338431218:83766 :140737338431227:209415 :140737338431246:167532 :140737338431263:209415 :140737338431291:167532 :140737338431307:7736 :140737338431320:15472 :140737338431339:11604 :140737338431357:11604 :140737338431371:30944 :140737338431410:7736 :140737338431419:27076 :140737338431443:7708 :140737338431464:125649 :140737338431484:335064 :140737338432000:380150 :140737338436016:966 :140737338436025:5796 :140737338436344:1932 :140737338436360:1932 :140737338436612:966 :140737338436621:2415 :140737338436644:4347 :140737338436678:2898 :140737338436707:966 :140737338436720:1932 :140737338436752:57477 :140737338436827:10143 :140737338436840:6762 :140737338436849:13524 :140737338436960:2898 :140737338437740:1449 :140737338437750:4347 :140737338441888:335160 :140737338441916:83790 :140737338441925:167580 :140737338441942:167580 :140737338441962:83790 :140737338441975:1449 :140737338442146:2415 :140737338442160:167504 :140737338442240:125685 :140737338442254:165648 :140737338442271:496944 :140737338442320:1932 :140737338442338:966 :140737338442347:1449 :140737338442360:966 :140737338442720:125652 :140737338442733:376956 :140737338442761:125652 :140737338442779:125652 :140737338442828:83768 :140737338442835:209415 :140737339471856:100548 :140737339471873:58317 :140737339471887:75995 :140737339472048:11396 :140737339472053:374 :140737339472098:27555 :140737339472128:935 :140737339472145:33920 :140737339472205:8480 :140737339472214:12720 :140737340682448:83790 :140737340685104:83768 :140737340738576:83768 :140737340746096:335160 :140737340746124:83790 :140737340746129:83790 :140737340816768:75411 :140737340816816:50256
|
tsp/fingerprint/pieces/segment.6
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
+
T:140737284461024:16708 :140737284461168:83576 :140737284461184:83540 :140737284461296:50124 :140737284461312:16716 :140737284464176:100248 :140737284464218:33416 :140737284464240:16708 :140737284464248:100248 :140737284464289:25062 :140737284464300:75186 :140737284464340:33416 :140737284464362:16708 :140737284464370:100248 :140737284464412:25062 :140737284464423:75186 :140737284465360:83540 :140737284465397:167080 :140737284465489:66832 :140737284465522:33416 :140737284465536:33416 :140737284465552:25062 :140737284465600:117012 :140737284465643:25074 :140737284465658:41790 :140737284465678:16716 :140737284465688:127533 :140737284465697:340056 :140737284465703:58506 :140737284465727:16708 :140737284465737:33416 :140737284465751:50124 :140737284465774:33416 :140737284465792:33416 :140737284465809:33416 :140737284465823:66864 :140737284466025:33432 :140737284466042:16716 :140737284466050:50148 :140737284466070:16716 :140737284466075:25074 :140737284466085:8358 :140737284466090:25077 :140737284466099:8359 :140737284466104:16718 :140737284466112:25074 :140737284466512:142018 :140737284466569:100248 :140737284466610:16708 :140737284466623:91894 :140737284466674:91894 :140737284466704:16708 :140737284466712:16708 :140737284466717:16708 :140737284466725:8354 :140737284466770:25062 :140737284466782:33416 :140737284466800:41770 :140737338431136:752184 :140737338431180:4 :140737338431195:125367 :140737338431208:83578 :140737338431218:83578 :140737338431227:208945 :140737338431246:167156 :140737338431263:208945 :140737338431291:167156 :140737338431307:7802 :140737338431320:15604 :140737338431339:11703 :140737338431357:11703 :140737338431371:31208 :140737338431410:7802 :140737338431419:27307 :140737338431443:7782 :140737338431464:125367 :140737338431484:334312 :140737338432000:378880 :140737338436016:974 :140737338436025:5844 :140737338436344:1948 :140737338436360:1948 :140737338436612:974 :140737338436621:2435 :140737338436644:4383 :140737338436678:2922 :140737338436707:974 :140737338436720:1948 :140737338436752:57953 :140737338436827:10227 :140737338436840:6818 :140737338436849:13636 :140737338436960:2922 :140737338437740:1461 :140737338437750:4383 :140737338441888:334160 :140737338441916:83540 :140737338441925:167080 :140737338441942:167080 :140737338441962:83540 :140737338441975:1461 :140737338442146:2435 :140737338442160:167060 :140737338442240:125310 :140737338442254:165132 :140737338442271:495396 :140737338442320:1948 :140737338442338:974 :140737338442347:1461 :140737338442360:974 :140737338442720:125364 :140737338442733:376092 :140737338442761:125364 :140737338442779:125364 :140737338442828:83576 :140737338442835:208942 :140737339471856:100248 :140737339471873:59769 :140737339471887:84695 :140737339472048:10278 :140737339472053:166 :140737339472098:25280 :140737339472128:415 :140737339472145:23872 :140737339472205:5968 :140737339472214:8952 :140737340682448:83540 :140737340685104:83576 :140737340738576:83576 :140737340746096:334160 :140737340746124:83540 :140737340746129:83540 :140737340816768:75186 :140737340816816:50148
|
tsp/fingerprint/pieces/segment.7
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
+
T:140737284461024:16484 :140737284461168:82398 :140737284461184:82426 :140737284461296:49456 :140737284461312:16480 :140737284464176:98916 :140737284464218:32972 :140737284464240:16486 :140737284464248:98916 :140737284464289:24729 :140737284464300:74187 :140737284464340:32972 :140737284464362:16486 :140737284464370:98916 :140737284464412:24729 :140737284464423:74178 :140737284465360:82420 :140737284465397:164840 :140737284465489:65936 :140737284465522:32968 :140737284465536:32968 :140737284465552:24726 :140737284465600:115360 :140737284465643:24720 :140737284465658:41200 :140737284465678:16480 :140737284465688:154557 :140737284465697:412176 :140737284465703:57680 :140737284465727:16486 :140737284465737:32972 :140737284465751:49452 :140737284465774:32968 :140737284465792:32968 :140737284465809:32968 :140737284465823:65912 :140737284466025:32960 :140737284466042:16480 :140737284466050:49440 :140737284466070:16478 :140737284466075:24717 :140737284466085:8239 :140737284466090:24717 :140737284466099:8239 :140737284466104:16478 :140737284466112:24720 :140737284466512:140114 :140737284466569:98904 :140737284466610:16484 :140737284466623:90662 :140737284466674:90662 :140737284466704:16484 :140737284466712:16484 :140737284466717:16484 :140737284466725:8242 :140737284466770:24726 :140737284466782:32968 :140737284466800:41210 :140737338431136:741582 :140737338431195:123597 :140737338431208:82398 :140737338431218:82398 :140737338431227:205995 :140737338431246:164796 :140737338431263:205995 :140737338431291:164796 :140737338431307:9360 :140737338431320:18720 :140737338431339:14040 :140737338431357:14040 :140737338431371:37440 :140737338431410:9360 :140737338431419:32760 :140737338431443:9330 :140737338431464:123597 :140737338431484:329592 :140737338432000:365190 :140737338436016:1174 :140737338436025:7044 :140737338436344:2348 :140737338436360:2348 :140737338436612:1174 :140737338436621:2935 :140737338436644:5283 :140737338436678:3522 :140737338436707:1174 :140737338436720:2348 :140737338436752:69853 :140737338436827:12327 :140737338436840:8218 :140737338436849:16436 :140737338436960:3522 :140737338437740:1761 :140737338437750:5283 :140737338441888:329704 :140737338441916:82426 :140737338441925:164852 :140737338441942:164852 :140737338441962:82426 :140737338441975:1761 :140737338442146:2935 :140737338442160:164844 :140737338442240:123639 :140737338442254:162504 :140737338442271:487512 :140737338442320:2348 :140737338442338:1174 :140737338442347:1761 :140737338442360:1174 :140737338442720:123597 :140737338442733:370791 :140737338442761:123597 :140737338442779:123597 :140737338442828:82398 :140737338442835:205995 :140737338442842:3 :140737339471856:98912 :140737339471873:65184 :140737339471887:103128 :140737339472048:6000 :140737339472053:48 :140737339472098:14880 :140737339472128:120 :140737339472145:8816 :140737339472205:2204 :140737339472214:3306 :140737340682448:82426 :140737340685104:82398 :140737340738576:82398 :140737340746096:329704 :140737340746124:82426 :140737340746129:82426 :140737340816768:74178 :140737340816816:49440
|
tsp/fingerprint/pieces/segment.8
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
+
T:140737284461024:16488 :140737284461168:82494 :140737284461184:82434 :140737284461296:49460 :140737284461312:16500 :140737284464176:98916 :140737284464218:32972 :140737284464240:16486 :140737284464248:98916 :140737284464289:24729 :140737284464300:74187 :140737284464340:32972 :140737284464362:16486 :140737284464370:98916 :140737284464412:24729 :140737284464423:74196 :140737284465360:82440 :140737284465397:164880 :140737284465489:65952 :140737284465522:32976 :140737284465536:32976 :140737284465552:24732 :140737284465600:115500 :140737284465643:24750 :140737284465658:41250 :140737284465678:16500 :140737284465688:152427 :140737284465697:406416 :140737284465703:57750 :140737284465727:16486 :140737284465737:32972 :140737284465751:49464 :140737284465774:32976 :140737284465792:32976 :140737284465809:32976 :140737284465823:66008 :140737284466025:33000 :140737284466042:16500 :140737284466050:49500 :140737284466070:16502 :140737284466075:24753 :140737284466085:8251 :140737284466090:24753 :140737284466099:8251 :140737284466104:16502 :140737284466112:24750 :140737284466512:140148 :140737284466569:98928 :140737284466610:16488 :140737284466623:90684 :140737284466674:90684 :140737284466704:16488 :140737284466712:16488 :140737284466717:16488 :140737284466725:8244 :140737284466770:24732 :140737284466782:32976 :140737284466800:41220 :140737338431136:742435 :140737338431195:123738 :140737338431208:82492 :140737338431218:82492 :140737338431227:206230 :140737338431246:164984 :140737338431263:206230 :140737338431291:164984 :140737338431307:9446 :140737338431320:18892 :140737338431339:14169 :140737338431357:14169 :140737338431371:37784 :140737338431410:9446 :140737338431419:33061 :140737338431443:9402 :140737338431464:123738 :140737338431484:329968 :140737338432000:365230 :140737338436016:1174 :140737338436025:7044 :140737338436344:2348 :140737338436360:2348 :140737338436612:1174 :140737338436621:2935 :140737338436644:5283 :140737338436678:3522 :140737338436707:1174 :140737338436720:2348 :140737338436752:69853 :140737338436827:12327 :140737338436840:8218 :140737338436849:16436 :140737338436960:3522 :140737338437740:1761 :140737338437750:5283 :140737338441888:329736 :140737338441916:82434 :140737338441925:164868 :140737338441942:164868 :140737338441962:82434 :140737338441975:1761 :140737338442146:2935 :140737338442160:164860 :140737338442240:123651 :140737338442254:162520 :140737338442271:487560 :140737338442320:2348 :140737338442338:1174 :140737338442347:1761 :140737338442360:1174 :140737338442720:123741 :140737338442733:371223 :140737338442761:123741 :140737338442779:123741 :140737338442828:82494 :140737338442835:206230 :140737339471856:98920 :140737339471873:64866 :140737339471887:101820 :140737339471903:2 :140737339472048:6216 :140737339472053:48 :140737339472098:15420 :140737339472128:120 :140737339472145:10064 :140737339472205:2516 :140737339472214:3774 :140737340682448:82434 :140737340685104:82494 :140737340738576:82494 :140737340746096:329736 :140737340746124:82434 :140737340746129:82434 :140737340816768:74196 :140737340816816:49500
|
tsp/fingerprint/pieces/segment.9
ADDED
|
@@ -0,0 +1 @@
|
|
|
|
|
|
|
| 1 |
+
T:140737284461024:16542 :140737284461168:82648 :140737284461184:82710 :140737284461296:49626 :140737284461312:16528 :140737284464176:99252 :140737284464218:33084 :140737284464240:16542 :140737284464248:99252 :140737284464289:24813 :140737284464300:74439 :140737284464340:33084 :140737284464362:16542 :140737284464370:99252 :140737284464412:24813 :140737284464423:74439 :140737284465360:82710 :140737284465397:165420 :140737284465489:66168 :140737284465522:33084 :140737284465536:33084 :140737284465552:24813 :140737284465600:115682 :140737284465643:24789 :140737284465658:41315 :140737284465678:16526 :140737284465688:149181 :140737284465697:397880 :140737284465703:57841 :140737284465727:16542 :140737284465737:33084 :140737284465751:49626 :140737284465774:33084 :140737284465792:33084 :140737284465809:33084 :140737284465823:66104 :140737284466025:33056 :140737284466042:16528 :140737284466050:49578 :140737284466070:16526 :140737284466075:24789 :140737284466085:8263 :140737284466090:24789 :140737284466099:8263 :140737284466104:16526 :140737284466112:24792 :140737284466512:140607 :140737284466569:99252 :140737284466610:16542 :140737284466623:90981 :140737284466674:90981 :140737284466704:16542 :140737284466712:16542 :140737284466717:16542 :140737284466725:8271 :140737284466770:24813 :140737284466782:33084 :140737284466800:41355 :140737338431136:743814 :140737338431149:11 :140737338431195:123972 :140737338431208:82648 :140737338431218:82648 :140737338431227:206620 :140737338431246:165296 :140737338431263:206620 :140737338431291:165296 :140737338431307:8910 :140737338431320:17816 :140737338431339:13362 :140737338431357:13362 :140737338431371:35632 :140737338431410:8908 :140737338431419:31178 :140737338431443:8876 :140737338431464:123972 :140737338431484:330592 :140737338431504:2 :140737338431514:3 :140737338431536:5 :140737338431563:2 :140737338431575:3 :140737338431587:4 :140737338431604:2 :140737338431618:3 :140737338431632:2 :140737338431673:2 :140737338431684:2 :140737338431696:8 :140737338431735:3 :140737338431752:8 :140737338431790:3 :140737338432000:368690 :140737338433104:5 :140737338436016:1120 :140737338436025:6720 :140737338436102:5 :140737338436344:2240 :140737338436360:2240 :140737338436380:2 :140737338436612:1118 :140737338436621:2795 :140737338436644:5031 :140737338436678:3354 :140737338436707:1118 :140737338436720:2236 :140737338436752:66521 :140737338436827:11739 :140737338436840:7826 :140737338436849:15652 :140737338436960:3354 :140737338437096:24 :140737338437220:12 :140737338437280:21 :140737338437378:3 :140737338437394:3 :140737338437408:2 :140737338437417:4 :140737338437433:3 :140737338437447:2 :140737338437457:2 :140737338437466:2 :140737338437475:2 :140737338437484:4 :140737338437683:2 :140737338437740:1677 :140737338437750:5040 :140737338437872:5 :140737338437897:3 :140737338437909:4 :140737338438368:12 :140737338438528:2 :140737338439000:3 :140737338439485:5 :140737338439508:7 :140737338441888:330840 :140737338441916:82710 :140737338441925:165420 :140737338441942:165420 :140737338441962:82710 :140737338441975:1680 :140737338442146:2800 :140737338442160:165420 :140737338442240:124065 :140737338442254:163180 :140737338442271:489540 :140737338442320:2240 :140737338442338:1120 :140737338442347:1680 :140737338442360:1120 :140737338442720:123972 :140737338442733:371916 :140737338442761:123969 :140737338442779:123969 :140737338442828:82646 :140737338442835:206620 :140737339471856:99252 :140737339471873:64293 :140737339471887:100415 :140737339472048:6764 :140737339472053:32 :140737339472098:16830 :140737339472128:80 :140737339472145:10784 :140737339472205:2696 :140737339472214:4044 :140737340682448:82710 :140737340685104:82648 :140737340738576:82648 :140737340746096:330840 :140737340746124:82710 :140737340746129:82710 :140737340816768:74439 :140737340816816:49584
|
tsp/fingerprint/run_0/PARAMS.in
ADDED
|
@@ -0,0 +1,268 @@
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# File : PARAMS.golden_cove
|
| 2 |
+
# Date : 02/27/25
|
| 3 |
+
# Description : Golden Cove Configuration
|
| 4 |
+
# Author : Surim Oh <[email protected]>
|
| 5 |
+
#
|
| 6 |
+
# Based on documentation found here:
|
| 7 |
+
# https://en.wikipedia.org/wiki/Golden_Cove
|
| 8 |
+
# https://en.wikichip.org/wiki/intel/microarchitectures/golden_cove
|
| 9 |
+
# https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/3
|
| 10 |
+
|
| 11 |
+
## Simulation Parameters
|
| 12 |
+
--mode full
|
| 13 |
+
--model cmp
|
| 14 |
+
--sim_limit none
|
| 15 |
+
|
| 16 |
+
## Core Parameters
|
| 17 |
+
|
| 18 |
+
# Femptoseconds, 3.2GHz, used for energy estimates.
|
| 19 |
+
--chip_cycle_time 312500
|
| 20 |
+
|
| 21 |
+
|
| 22 |
+
### Fetch Stage
|
| 23 |
+
--fetch_off_path_ops 1
|
| 24 |
+
|
| 25 |
+
#### ICache
|
| 26 |
+
--icache_size 32768
|
| 27 |
+
--icache_assoc 8
|
| 28 |
+
--icache_line_size 64
|
| 29 |
+
|
| 30 |
+
### Uop Cache
|
| 31 |
+
# inclusive w/ L1i
|
| 32 |
+
--uop_cache_enable 1
|
| 33 |
+
--uop_cache_width 8
|
| 34 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 35 |
+
--uop_cache_assoc 8
|
| 36 |
+
--iprf_on_uop_cache_hit 1
|
| 37 |
+
|
| 38 |
+
### Branch Predictor
|
| 39 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 40 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 41 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 42 |
+
--bp_mech tage64k
|
| 43 |
+
|
| 44 |
+
|
| 45 |
+
#### BTB
|
| 46 |
+
|
| 47 |
+
# TODO
|
| 48 |
+
# multi-level BTB
|
| 49 |
+
# 128 entry L0 BTB
|
| 50 |
+
# 6144 entry L1 BTB
|
| 51 |
+
# 12888 entry L2 BTB
|
| 52 |
+
# ~2 entry Return Stack
|
| 53 |
+
# roughly 2x8192 for now
|
| 54 |
+
# BTB model to use.
|
| 55 |
+
--btb_mech generic
|
| 56 |
+
--btb_entries 12288
|
| 57 |
+
--btb_assoc 4
|
| 58 |
+
--btb_main_latency 3
|
| 59 |
+
--btb_l0_present 1
|
| 60 |
+
--btb_l0_entries 128
|
| 61 |
+
--btb_l0_assoc 4
|
| 62 |
+
--btb_l0_latency 1
|
| 63 |
+
--btb_l1_present 1
|
| 64 |
+
--btb_l1_entries 6144
|
| 65 |
+
--btb_l1_assoc 4
|
| 66 |
+
--btb_l1_latency 2
|
| 67 |
+
|
| 68 |
+
# Allow the BTB to be updated by off path ops.
|
| 69 |
+
--btb_off_path_writes 1
|
| 70 |
+
|
| 71 |
+
# NT branches are not inserted in BTB, but do not trigger resteer
|
| 72 |
+
# since we continue without a control flow change
|
| 73 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 74 |
+
|
| 75 |
+
#### CRS
|
| 76 |
+
|
| 77 |
+
# Enable return stack
|
| 78 |
+
--enable_crs 1
|
| 79 |
+
--crs_entries 128
|
| 80 |
+
--crs_realistic 1
|
| 81 |
+
|
| 82 |
+
### iBP
|
| 83 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 84 |
+
--ibtb_mech tc_tagged
|
| 85 |
+
# iBTB Model. tc_tagless, tc_tagged, tc_hybrid.
|
| 86 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 87 |
+
--tc_entries 4096
|
| 88 |
+
--tc_assoc 4
|
| 89 |
+
|
| 90 |
+
### Decode Stage
|
| 91 |
+
--decode_width 6
|
| 92 |
+
--decode_cycles 5
|
| 93 |
+
|
| 94 |
+
### Instruction Decode Queue
|
| 95 |
+
--idq_size 144
|
| 96 |
+
|
| 97 |
+
### Map Stage
|
| 98 |
+
--map_cycles 5
|
| 99 |
+
|
| 100 |
+
# register renaming table
|
| 101 |
+
--reg_renaming_scheme 1
|
| 102 |
+
--reg_table_integer_physical_size 280
|
| 103 |
+
--reg_table_vector_physical_size 332
|
| 104 |
+
|
| 105 |
+
### Issue Stage
|
| 106 |
+
|
| 107 |
+
# Max number of instructions to be renamed, and issued per cycle.
|
| 108 |
+
--issue_width 6
|
| 109 |
+
|
| 110 |
+
--rs_fill_width 0
|
| 111 |
+
# rs_sizes ~205 in total, and they are split into three different reservation stations (RS1, RS2, RS3) where each has 97, 70, 38 entries respectively
|
| 112 |
+
# original architecture
|
| 113 |
+
# RS1 connected to port 0,1,5,6,10
|
| 114 |
+
# RS2 connected to port 2,3,11
|
| 115 |
+
# RS3 connected to port 7,8,4,9
|
| 116 |
+
# scarab does not split ST AGU port and ST port, merge them
|
| 117 |
+
# adjusted architecture to scarab ST AGU (port 4 and 9 removed. rs_size reduced to 186 from 205)
|
| 118 |
+
# RS1 connected to port 0,1,4,5,8
|
| 119 |
+
# RS2 connected to port 2,3,9
|
| 120 |
+
# RS3 connected to port 6,7 (port 4,9 removed, entries reduced to 19 from 38)
|
| 121 |
+
--rs_sizes 97 70 19
|
| 122 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 123 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 124 |
+
|
| 125 |
+
### Exec Stage
|
| 126 |
+
|
| 127 |
+
### DCache
|
| 128 |
+
--dcache_size 49152
|
| 129 |
+
--dcache_read_ports 1
|
| 130 |
+
--dcache_write_ports 1
|
| 131 |
+
--dcache_banks 8
|
| 132 |
+
--dcache_assoc 12
|
| 133 |
+
--dcache_line_size 64
|
| 134 |
+
--dcache_cycles 5
|
| 135 |
+
|
| 136 |
+
### Reorder/Retire Stage
|
| 137 |
+
|
| 138 |
+
# Max number of instructions to be retired per cycle.
|
| 139 |
+
--node_ret_width 8
|
| 140 |
+
--node_table_size 512
|
| 141 |
+
|
| 142 |
+
# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does
|
| 143 |
+
--stores_do_not_block_window 1
|
| 144 |
+
|
| 145 |
+
# TODO: confirm what this knob does
|
| 146 |
+
--prefs_do_not_block_window 1
|
| 147 |
+
|
| 148 |
+
|
| 149 |
+
## Uncore
|
| 150 |
+
|
| 151 |
+
### Mid-level cache
|
| 152 |
+
|
| 153 |
+
# Enable use of a midlevel cache between i/d and L1
|
| 154 |
+
# client 1.25 MiB (1310720 bytes) per core, 8-way, 15 cycles
|
| 155 |
+
# server 2 MiB (2097000 bytes) per core, 8-way, 16 cycles
|
| 156 |
+
--mlc_present 1
|
| 157 |
+
--mlc_size 2097000
|
| 158 |
+
--mlc_assoc 8
|
| 159 |
+
--mlc_cycles 16
|
| 160 |
+
|
| 161 |
+
|
| 162 |
+
### LLC
|
| 163 |
+
# 3 MiB per core, 16-way
|
| 164 |
+
--l1_size 3145728
|
| 165 |
+
--l1_banks 8
|
| 166 |
+
--l1_cycles 36 // just a guess
|
| 167 |
+
--l1_assoc 16
|
| 168 |
+
--l1_line_size 64
|
| 169 |
+
--l1_interleave_factor 64
|
| 170 |
+
|
| 171 |
+
|
| 172 |
+
### prefetcher
|
| 173 |
+
# Kept same as Kaby Lake
|
| 174 |
+
--pref_framework_on 1
|
| 175 |
+
--pref_stream_on 1
|
| 176 |
+
--pref_train_on_pref_misses 0
|
| 177 |
+
--pref_oracle_train 0
|
| 178 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 179 |
+
|
| 180 |
+
--stream_length 64
|
| 181 |
+
--stream_prefetch_n 4
|
| 182 |
+
--stream_start_dis 1
|
| 183 |
+
--stream_train_num 4
|
| 184 |
+
--stream_create_on_dc_miss 0
|
| 185 |
+
--stream_create_on_l1_miss 1
|
| 186 |
+
|
| 187 |
+
--pref_throttlefb_on=1
|
| 188 |
+
--pref_acc_thresh_1=0.75
|
| 189 |
+
--pref_acc_thresh_2=0.4
|
| 190 |
+
--pref_acc_thresh_3=0.4
|
| 191 |
+
--pref_timely_thresh=0.01
|
| 192 |
+
--pref_polpf_thresh=0.005
|
| 193 |
+
--pref_update_interval=8192
|
| 194 |
+
|
| 195 |
+
--mem_req_buffer_pref_watermark 4
|
| 196 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 197 |
+
|
| 198 |
+
### Memory
|
| 199 |
+
# Kept same as Kaby Lake
|
| 200 |
+
--addr_translation random
|
| 201 |
+
|
| 202 |
+
--mem_priority_ifetch 0
|
| 203 |
+
--mem_priority_dfetch 1
|
| 204 |
+
--mem_priority_dstore 2
|
| 205 |
+
--mem_priority_iprf 3
|
| 206 |
+
--mem_priority_dprf 4
|
| 207 |
+
--mem_priority_wb 5
|
| 208 |
+
--mem_priority_wb_nodirty 5
|
| 209 |
+
|
| 210 |
+
--mem_req_buffer_entries 32
|
| 211 |
+
--bus_width_in_bytes 8
|
| 212 |
+
|
| 213 |
+
--ramulator_standard DDR4
|
| 214 |
+
--ramulator_speed DDR4_2400R
|
| 215 |
+
--ramulator_org DDR4_8Gb_x8
|
| 216 |
+
--ramulator_channels 1
|
| 217 |
+
--ramulator_ranks 1
|
| 218 |
+
--ramulator_bankgroups 4
|
| 219 |
+
--ramulator_banks 4
|
| 220 |
+
--ramulator_chip_width 8
|
| 221 |
+
--ramulator_rows 65536
|
| 222 |
+
--ramulator_cols 1024
|
| 223 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 224 |
+
--ramulator_readq_entries 32
|
| 225 |
+
--ramulator_writeq_entries 32
|
| 226 |
+
--ramulator_record_cmd_trace FALSE
|
| 227 |
+
--ramulator_print_cmd_trace FALSE
|
| 228 |
+
--ramulator_tCK 833333
|
| 229 |
+
--ramulator_tCL 16
|
| 230 |
+
--ramulator_tCCD 6
|
| 231 |
+
--ramulator_tCCDS 4
|
| 232 |
+
--ramulator_tCCDL 6
|
| 233 |
+
--ramulator_tCWL 12
|
| 234 |
+
--ramulator_tBL 4
|
| 235 |
+
--ramulator_tWTR 9
|
| 236 |
+
--ramulator_tWTRS 3
|
| 237 |
+
--ramulator_tWTRL 9
|
| 238 |
+
--ramulator_tRP 16
|
| 239 |
+
--ramulator_tRPpb 16
|
| 240 |
+
--ramulator_tRPab 16
|
| 241 |
+
--ramulator_tRCD 16
|
| 242 |
+
--ramulator_tRCDR 16
|
| 243 |
+
--ramulator_tRCDW 16
|
| 244 |
+
--ramulator_tRAS 39
|
| 245 |
+
--dram_tech_in_nm 32
|
| 246 |
+
|
| 247 |
+
## Other
|
| 248 |
+
|
| 249 |
+
|
| 250 |
+
### Debug
|
| 251 |
+
--debug_inst_start 0
|
| 252 |
+
--debug_inst_stop -1
|
| 253 |
+
--debug_cycle_start 0
|
| 254 |
+
--debug_cycle_stop -1
|
| 255 |
+
|
| 256 |
+
|
| 257 |
+
## Stats and Params
|
| 258 |
+
--dump_params 1
|
| 259 |
+
--dump_stats 1
|
| 260 |
+
--dump_trace 0
|
| 261 |
+
|
| 262 |
+
####################################
|
| 263 |
+
--set_off_path_confirmed 1
|
| 264 |
+
|
| 265 |
+
--order_beyond_bus 1
|
| 266 |
+
|
| 267 |
+
--mem_ooo_stores 1
|
| 268 |
+
--mem_obey_store_dep 1
|
tsp/fingerprint/run_0/PARAMS.out
ADDED
|
@@ -0,0 +1,1102 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
|
|
|
|
|
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|
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|
|
|
|
|
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|
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|
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|
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|
|
|
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|
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|
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|
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|
|
|
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|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
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|
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|
|
|
|
|
|
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|
|
|
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|
|
|
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|
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|
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|
|
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|
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| 1 |
+
--mode trace_bbv_distributed
|
| 2 |
+
--model cmp
|
| 3 |
+
--frontend memtrace
|
| 4 |
+
--sim_limit none
|
| 5 |
+
--memtrace_roi_begin 1
|
| 6 |
+
--memtrace_roi_end 10000000
|
| 7 |
+
--use_fetched_count 1
|
| 8 |
+
--dump_params 1
|
| 9 |
+
--dump_stats 1
|
| 10 |
+
--dump_trace 0
|
| 11 |
+
--trace_bbv_output /dev/shm/baseline/traces/tsp/fingerprint/pieces/segment.0
|
| 12 |
+
--trace_footprint_output /dev/shm/baseline/traces/tsp/fingerprint/footprint_pieces/segment.0
|
| 13 |
+
--segment_instr_count 10000000
|
| 14 |
+
--mlc_present 1
|
| 15 |
+
--mlc_size 2097000
|
| 16 |
+
--mlc_assoc 8
|
| 17 |
+
--mlc_cycles 16
|
| 18 |
+
--l1_size 3145728
|
| 19 |
+
--l1_assoc 16
|
| 20 |
+
--l1_line_size 64
|
| 21 |
+
--l1_cycles 36 // just a guess
|
| 22 |
+
--l1_banks 8
|
| 23 |
+
--l1_interleave_factor 64
|
| 24 |
+
--addr_translation random
|
| 25 |
+
--icache_size 32768
|
| 26 |
+
--icache_assoc 8
|
| 27 |
+
--icache_line_size 64
|
| 28 |
+
--uop_cache_enable 1
|
| 29 |
+
--uop_cache_width 8
|
| 30 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 31 |
+
--uop_cache_assoc 8
|
| 32 |
+
--iprf_on_uop_cache_hit 1
|
| 33 |
+
--dcache_size 49152
|
| 34 |
+
--dcache_assoc 12
|
| 35 |
+
--dcache_line_size 64
|
| 36 |
+
--dcache_cycles 5
|
| 37 |
+
--dcache_read_ports 1
|
| 38 |
+
--dcache_write_ports 1
|
| 39 |
+
--dcache_banks 8
|
| 40 |
+
--mem_ooo_stores 1
|
| 41 |
+
--mem_obey_store_dep 1
|
| 42 |
+
--mem_req_buffer_entries 32
|
| 43 |
+
--mem_priority_ifetch 0
|
| 44 |
+
--mem_priority_dfetch 1
|
| 45 |
+
--mem_priority_dstore 2
|
| 46 |
+
--mem_priority_iprf 3
|
| 47 |
+
--mem_priority_dprf 4
|
| 48 |
+
--mem_priority_wb 5
|
| 49 |
+
--mem_priority_wb_nodirty 5
|
| 50 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 51 |
+
--mem_req_buffer_pref_watermark 4
|
| 52 |
+
--order_beyond_bus 1
|
| 53 |
+
--set_off_path_confirmed 1
|
| 54 |
+
--ramulator_standard DDR4
|
| 55 |
+
--ramulator_speed DDR4_2400R
|
| 56 |
+
--ramulator_org DDR4_8Gb_x8
|
| 57 |
+
--ramulator_channels 1
|
| 58 |
+
--ramulator_ranks 1
|
| 59 |
+
--ramulator_bankgroups 4
|
| 60 |
+
--ramulator_banks 4
|
| 61 |
+
--ramulator_chip_width 8
|
| 62 |
+
--bus_width_in_bytes 8
|
| 63 |
+
--ramulator_rows 65536
|
| 64 |
+
--ramulator_cols 1024
|
| 65 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 66 |
+
--ramulator_readq_entries 32
|
| 67 |
+
--ramulator_writeq_entries 32
|
| 68 |
+
--ramulator_record_cmd_trace FALSE
|
| 69 |
+
--ramulator_print_cmd_trace FALSE
|
| 70 |
+
--ramulator_tCK 833333
|
| 71 |
+
--ramulator_tCL 16
|
| 72 |
+
--ramulator_tCCD 6
|
| 73 |
+
--ramulator_tCCDS 4
|
| 74 |
+
--ramulator_tCCDL 6
|
| 75 |
+
--ramulator_tCWL 12
|
| 76 |
+
--ramulator_tBL 4
|
| 77 |
+
--ramulator_tWTR 9
|
| 78 |
+
--ramulator_tWTRS 3
|
| 79 |
+
--ramulator_tWTRL 9
|
| 80 |
+
--ramulator_tRP 16
|
| 81 |
+
--ramulator_tRPpb 16
|
| 82 |
+
--ramulator_tRPab 16
|
| 83 |
+
--ramulator_tRCD 16
|
| 84 |
+
--ramulator_tRCDR 16
|
| 85 |
+
--ramulator_tRCDW 16
|
| 86 |
+
--ramulator_tRAS 39
|
| 87 |
+
--dram_tech_in_nm 32
|
| 88 |
+
--chip_cycle_time 312500
|
| 89 |
+
--issue_width 6
|
| 90 |
+
--rs_fill_width 0
|
| 91 |
+
--node_table_size 512
|
| 92 |
+
--node_ret_width 8
|
| 93 |
+
--decode_width 6
|
| 94 |
+
--idq_size 144
|
| 95 |
+
--reg_renaming_scheme 1
|
| 96 |
+
--reg_table_integer_physical_size 280
|
| 97 |
+
--reg_table_vector_physical_size 332
|
| 98 |
+
--rs_sizes 97 70 19
|
| 99 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 100 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 101 |
+
--decode_cycles 5
|
| 102 |
+
--map_cycles 5
|
| 103 |
+
--fetch_off_path_ops 1
|
| 104 |
+
--stores_do_not_block_window 1
|
| 105 |
+
--prefs_do_not_block_window 1
|
| 106 |
+
--cbp_trace_r0 /dev/shm/baseline/traces/.staging/tsp-164844/raw_trace/drmemtrace.tsp.164856.4389.dir/trace/drmemtrace.tsp.164856.1160.trace.zip
|
| 107 |
+
--debug_cycle_start 0
|
| 108 |
+
--debug_cycle_stop -1
|
| 109 |
+
--debug_inst_start 0
|
| 110 |
+
--debug_inst_stop -1
|
| 111 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 112 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 113 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 114 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 115 |
+
--bp_mech tage64k
|
| 116 |
+
--btb_mech generic
|
| 117 |
+
--btb_entries 12288
|
| 118 |
+
--btb_assoc 4
|
| 119 |
+
--btb_off_path_writes 1
|
| 120 |
+
--btb_main_latency 3
|
| 121 |
+
--btb_l0_present 1
|
| 122 |
+
--btb_l0_entries 128
|
| 123 |
+
--btb_l0_assoc 4
|
| 124 |
+
--btb_l0_latency 1
|
| 125 |
+
--btb_l1_present 1
|
| 126 |
+
--btb_l1_entries 6144
|
| 127 |
+
--btb_l1_assoc 4
|
| 128 |
+
--btb_l1_latency 2
|
| 129 |
+
--enable_crs 1
|
| 130 |
+
--crs_entries 128
|
| 131 |
+
--crs_realistic 1
|
| 132 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 133 |
+
--ibtb_mech tc_tagged
|
| 134 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 135 |
+
--tc_entries 4096
|
| 136 |
+
--tc_assoc 4
|
| 137 |
+
--pref_stream_on 1
|
| 138 |
+
--stream_prefetch_n 4
|
| 139 |
+
--stream_start_dis 1
|
| 140 |
+
--stream_length 64
|
| 141 |
+
--stream_train_num 4
|
| 142 |
+
--stream_create_on_dc_miss 0
|
| 143 |
+
--stream_create_on_l1_miss 1
|
| 144 |
+
--pref_framework_on 1
|
| 145 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 146 |
+
--pref_train_on_pref_misses 0
|
| 147 |
+
--pref_oracle_train_on 0
|
| 148 |
+
--pref_throttlefb_on 1
|
| 149 |
+
--pref_acc_thresh_1 0.75
|
| 150 |
+
--pref_acc_thresh_2 0.4
|
| 151 |
+
--pref_acc_thresh_3 0.4
|
| 152 |
+
--pref_update_interval 8192
|
| 153 |
+
--pref_timely_thresh 0.01
|
| 154 |
+
--pref_polpf_thresh 0.005
|
| 155 |
+
1 1 1 1 1 1 1
|
| 156 |
+
|
| 157 |
+
--- Cut out everything below to use this file as PARAMS.in ---
|
| 158 |
+
|
| 159 |
+
Parameter status at compile time and values supplied on the command line:
|
| 160 |
+
|
| 161 |
+
SIM_MODE 0 trace_bbv_distributed
|
| 162 |
+
SIM_MODEL 0 cmp
|
| 163 |
+
FRONTEND FE_PIN_EXEC_DRIVEN memtrace
|
| 164 |
+
INST_LIMIT NULL
|
| 165 |
+
SIM_LIMIT "none" none
|
| 166 |
+
FORWARD_PROGRESS_LIMIT 100000000
|
| 167 |
+
FORWARD_PROGRESS_INTERVAL 10000
|
| 168 |
+
FAST_FORWARD 0
|
| 169 |
+
FAST_FORWARD_TRACE_INS 0
|
| 170 |
+
FAST_FORWARD_UNTIL_ADDR 0
|
| 171 |
+
MEMTRACE_ROI_BEGIN 0 1
|
| 172 |
+
MEMTRACE_ROI_END 0 10000000
|
| 173 |
+
FULL_WARMUP 0
|
| 174 |
+
WARMUP 0
|
| 175 |
+
HEARTBEAT_INTERVAL 1000000
|
| 176 |
+
NUM_HEARTBEATS 0
|
| 177 |
+
USE_FETCHED_COUNT FALSE 1
|
| 178 |
+
PERIODIC_DUMP FALSE
|
| 179 |
+
FILE_TAG ""
|
| 180 |
+
OUTPUT_DIR "."
|
| 181 |
+
STATUS_FILE NULL
|
| 182 |
+
BINDIR NULL
|
| 183 |
+
DUMP_PARAMS TRUE 1
|
| 184 |
+
DUMP_STATS TRUE 1
|
| 185 |
+
DUMP_TRACE FALSE 0
|
| 186 |
+
CLEAR_STATS "never"
|
| 187 |
+
STATS_TO_TRACE NULL
|
| 188 |
+
STAT_TRACE_FILE "stats.trace"
|
| 189 |
+
STAT_TRACE_INTERVAL "i:100000"
|
| 190 |
+
PIPEVIEW FALSE
|
| 191 |
+
PIPEVIEW_FILE "pipeview"
|
| 192 |
+
MEMVIEW FALSE
|
| 193 |
+
MEMVIEW_FILE "memview.out"
|
| 194 |
+
MEMVIEW_START "never"
|
| 195 |
+
INST_HASH_TABLE_SIZE 524288 const
|
| 196 |
+
STDOUT_FILE NULL
|
| 197 |
+
STDERR_FILE NULL
|
| 198 |
+
PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp"
|
| 199 |
+
PRINT_PID FALSE
|
| 200 |
+
USE_UNSURE_FREE_LISTS FALSE
|
| 201 |
+
OPTIMIZER2_MAX_NUM_SLAVES 64
|
| 202 |
+
OPTIMIZER2_PERFECT_MEMORYLESS FALSE
|
| 203 |
+
EXIT_COND 0
|
| 204 |
+
NUM_NOPS 0
|
| 205 |
+
NOPS_BB_START 0x5000000
|
| 206 |
+
IGNORE_BAR_FETCH FALSE
|
| 207 |
+
TRACE_BBV_OUTPUT NULL /dev/shm/baseline/traces/tsp/fingerprint/pieces/segment.0
|
| 208 |
+
TRACE_FOOTPRINT_OUTPUT "" /dev/shm/baseline/traces/tsp/fingerprint/footprint_pieces/segment.0
|
| 209 |
+
SEGMENT_INSTR_COUNT 0 10000000
|
| 210 |
+
ENABLE_SWPRF FALSE
|
| 211 |
+
MLC_PRESENT FALSE 1
|
| 212 |
+
MLC_SIZE (512 * 1024) 2097000
|
| 213 |
+
MLC_ASSOC 4 8
|
| 214 |
+
MLC_LINE_SIZE 64
|
| 215 |
+
MLC_CYCLES 12 16
|
| 216 |
+
PERFECT_MLC FALSE
|
| 217 |
+
MLC_READ_PORTS 1
|
| 218 |
+
MLC_WRITE_PORTS 1
|
| 219 |
+
MLC_BANKS 8
|
| 220 |
+
MLC_INTERLEAVE_FACTOR 64
|
| 221 |
+
MLC_CACHE_REPL_POLICY 0
|
| 222 |
+
MLC_WRITE_THROUGH FALSE
|
| 223 |
+
PREFETCH_UPDATE_LRU_MLC TRUE
|
| 224 |
+
FORCE_L1_MISS FALSE
|
| 225 |
+
L1_SIZE (4 * 1024 * 1024) 3145728
|
| 226 |
+
L1_ASSOC 8 16
|
| 227 |
+
L1_LINE_SIZE 64 64
|
| 228 |
+
L1_CYCLES 24 36 // just a guess
|
| 229 |
+
PERFECT_L1 FALSE
|
| 230 |
+
PRIVATE_L1 FALSE
|
| 231 |
+
L1_READ_PORTS 1
|
| 232 |
+
L1_WRITE_PORTS 1
|
| 233 |
+
L1_BANKS 8 8
|
| 234 |
+
L1_INTERLEAVE_FACTOR 64 64
|
| 235 |
+
L1_CACHE_REPL_POLICY 0
|
| 236 |
+
L1_WRITE_THROUGH FALSE
|
| 237 |
+
L1_IGNORE_WB FALSE
|
| 238 |
+
L1_USE_CORE_FREQ FALSE
|
| 239 |
+
MARK_L1_MISSES TRUE
|
| 240 |
+
PREFETCH_UPDATE_LRU_L1 TRUE
|
| 241 |
+
MEMORY_RANDOM_ADDR FALSE
|
| 242 |
+
VA_PAGE_SIZE_BYTES 4096
|
| 243 |
+
NUM_ADDR_NON_SIGN_EXTEND_BITS 48
|
| 244 |
+
ADDR_TRANSLATION 0 random
|
| 245 |
+
CONSTANT_MEMORY_LATENCY FALSE
|
| 246 |
+
MEMORY_CYCLES 100
|
| 247 |
+
STALL_MEM_REQS_ONLY FALSE
|
| 248 |
+
ICACHE_SIZE (64 * 1024) 32768
|
| 249 |
+
ICACHE_ASSOC 4 8
|
| 250 |
+
ICACHE_LINE_SIZE 64 64
|
| 251 |
+
PERFECT_ICACHE FALSE
|
| 252 |
+
ICACHE_READ_PORTS 1
|
| 253 |
+
ICACHE_WRITE_PORTS 1
|
| 254 |
+
ICACHE_BANKS 8
|
| 255 |
+
ICACHE_REPL 0
|
| 256 |
+
UOP_CACHE_ENABLE 1 1
|
| 257 |
+
UOP_CACHE_WIDTH 6 8
|
| 258 |
+
ALWAYS_LOOKUP_ICACHE 0
|
| 259 |
+
UOP_CACHE_INSERT_ONLY_ONPATH FALSE
|
| 260 |
+
UOP_CACHE_READ_PORTS 1
|
| 261 |
+
UOP_CACHE_LINES 384 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 262 |
+
UOP_CACHE_ASSOC 8 8
|
| 263 |
+
UOP_CACHE_MAX_IMM_DISP_LINE 4
|
| 264 |
+
IPRF_ON_UOP_CACHE_HIT FALSE 1
|
| 265 |
+
UOP_CACHE_REPL 0
|
| 266 |
+
PRIORITY_LINE_STICKINESS_PERCENT 50
|
| 267 |
+
PW_PRIORITY_LIST_FILEPATH "pw_priority_list.csv"
|
| 268 |
+
NUM_PRIORITY_PWS 10
|
| 269 |
+
PRIORITIZE_PWS_AFTER_FIRST_STICKY_UNTIL_BACKEND_STALL FALSE
|
| 270 |
+
NO_REPL_AFTER_QUEUE_SIZE 0
|
| 271 |
+
FDIP_UC_SIZE 0
|
| 272 |
+
FDIP_UC_ASSOC 4
|
| 273 |
+
FDIP_UC_INSERT_REPLPOL 0
|
| 274 |
+
MAP_STAGE_CONSUME_FROM_ICACHE_AND_UOC_SAME_CYCLE TRUE
|
| 275 |
+
UOP_QUEUE_LENGTH 7
|
| 276 |
+
DCACHE_SIZE (64 * 1024) 49152
|
| 277 |
+
DCACHE_ASSOC 1 12
|
| 278 |
+
DCACHE_LINE_SIZE 64 64
|
| 279 |
+
DCACHE_CYCLES 2 5
|
| 280 |
+
PERFECT_DCACHE FALSE
|
| 281 |
+
DCACHE_READ_PORTS 8 1
|
| 282 |
+
DCACHE_WRITE_PORTS 1 1
|
| 283 |
+
DCACHE_BANKS 1 8
|
| 284 |
+
DCACHE_INTERLEAVE_FACTOR 4
|
| 285 |
+
DCACHE_REPL 0
|
| 286 |
+
DCACHE_REPL_PREF_THRESH 1
|
| 287 |
+
MEM_OOO_STORES TRUE 1
|
| 288 |
+
MEM_OBEY_STORE_DEP TRUE 1
|
| 289 |
+
PREF_INSERT_LRU FALSE
|
| 290 |
+
PREF_INSERT_MIDDLE FALSE
|
| 291 |
+
PREF_INSERT_LOWQTR FALSE
|
| 292 |
+
PREF_INSERT_DYNACC FALSE
|
| 293 |
+
MEM_REQ_BUFFER_ENTRIES 32 32
|
| 294 |
+
PRIVATE_MSHR_ON TRUE
|
| 295 |
+
MEM_PRIORITY_IFETCH 0 0
|
| 296 |
+
MEM_PRIORITY_DFETCH 0 1
|
| 297 |
+
MEM_PRIORITY_DSTORE 0 2
|
| 298 |
+
MEM_PRIORITY_IPRF 9 3
|
| 299 |
+
MEM_PRIORITY_UOCPRF 9
|
| 300 |
+
MEM_PRIORITY_FDIPPRFON 8
|
| 301 |
+
MEM_PRIORITY_FDIPPRFOFF 9
|
| 302 |
+
MEM_PRIORITY_DPRF 10 4
|
| 303 |
+
MEM_PRIORITY_WB 0 5
|
| 304 |
+
MEM_PRIORITY_WB_NODIRTY 0 5
|
| 305 |
+
PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1
|
| 306 |
+
MEM_REQ_BUFFER_PREF_WATERMARK 0 4
|
| 307 |
+
MEM_REQ_BUFFER_WB_VALVE 2
|
| 308 |
+
MEM_L1_FILL_QUEUE_ENTRIES 32
|
| 309 |
+
MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE
|
| 310 |
+
MEM_MEM_QUEUE_PARTITION_ENABLE FALSE
|
| 311 |
+
MEM_BUS_OUT_QUEUE_AS_FIFO TRUE
|
| 312 |
+
OLDEST_FIRST_TO_MEM_QUEUE TRUE
|
| 313 |
+
ROUND_ROBIN_TO_MEM_QUEUE FALSE
|
| 314 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE FALSE
|
| 315 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0
|
| 316 |
+
L1_CYCLE_TIME 312500
|
| 317 |
+
MLCQ_TO_L1Q_TRANSFER_LATENCY 1
|
| 318 |
+
L1Q_TO_FSB_TRANSFER_LATENCY 1
|
| 319 |
+
PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE
|
| 320 |
+
KICKOUT_PREFETCHES FALSE
|
| 321 |
+
KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE
|
| 322 |
+
KICKOUT_OLDEST_PREFETCH FALSE
|
| 323 |
+
KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE
|
| 324 |
+
ORDER_BEYOND_BUS FALSE 1
|
| 325 |
+
ALL_FIFO_QUEUES FALSE
|
| 326 |
+
QUEUE_MLC_SIZE 0
|
| 327 |
+
QUEUE_L1_SIZE 0
|
| 328 |
+
QUEUE_BUS_OUT_SIZE 0
|
| 329 |
+
QUEUE_CORE_FILL_SIZE 0
|
| 330 |
+
ALLOW_TYPE_MATCHES FALSE
|
| 331 |
+
STREAM_PREFETCH_ON FALSE
|
| 332 |
+
DC_PREF_CACHE_ENABLE FALSE
|
| 333 |
+
DC_PREF_CACHE_CYCLE 0
|
| 334 |
+
PREF_INSERT_DCACHE_IMM TRUE
|
| 335 |
+
DC_PREF_CACHE_SIZE (64 * 1024)
|
| 336 |
+
DC_PREF_CACHE_ASSOC 4
|
| 337 |
+
DC_PREF_ONLY_L1HIT FALSE
|
| 338 |
+
PREF_CACHE_USE_RDY_CYCLE FALSE
|
| 339 |
+
IC_PREF_CACHE_ENABLE FALSE
|
| 340 |
+
IC_PREF_CACHE_SIZE (64 * 1024)
|
| 341 |
+
IC_PREF_CACHE_ASSOC 4
|
| 342 |
+
L1_PREF_CACHE_ENABLE FALSE
|
| 343 |
+
L1_PREF_CACHE_SIZE (1024 * 1024)
|
| 344 |
+
L1_PREF_CACHE_ASSOC 8
|
| 345 |
+
SET_OFF_PATH_CONFIRMED FALSE 1
|
| 346 |
+
USE_CONFIRMED_OFF FALSE
|
| 347 |
+
PREFCACHE_MOVE_OFFPATH FALSE
|
| 348 |
+
CACHE_STAT_ENABLE FALSE
|
| 349 |
+
PREF_DCACHE_HIT_FILL_L1 TRUE
|
| 350 |
+
PREF_ICACHE_HIT_FILL_L1 TRUE
|
| 351 |
+
CRITICAL_ACCESS_PLOT_ENABLE FALSE
|
| 352 |
+
CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat"
|
| 353 |
+
ROUND_ROBIN_TO_L1 FALSE
|
| 354 |
+
PREF_I_TOGETHER FALSE
|
| 355 |
+
ONE_MORE_CACHE_LINE_ENABLE FALSE
|
| 356 |
+
L1_STATIC_PARTITION_ENABLE 0
|
| 357 |
+
L1_STATIC_PARTITION NULL
|
| 358 |
+
L1_DYNAMIC_PARTITION_ENABLE FALSE
|
| 359 |
+
L1_DYNAMIC_PARTITION_POLICY 0
|
| 360 |
+
PARTITION_UMON_DSS_PREF_ENABLE FALSE
|
| 361 |
+
L1_CACHE_HIT_POSITION_COLLECT FALSE
|
| 362 |
+
L1_PART_ON FALSE
|
| 363 |
+
L1_PART_TRIGGER "c:1000000"
|
| 364 |
+
L1_PART_START "t:0"
|
| 365 |
+
L1_PART_WARMUP FALSE
|
| 366 |
+
L1_PART_SHADOW_WARMUP FALSE
|
| 367 |
+
L1_PART_METRIC 0
|
| 368 |
+
L1_PART_SEARCH 0
|
| 369 |
+
L1_PART_USE_STALLING TRUE
|
| 370 |
+
L1_PART_FILL_DELAY 0
|
| 371 |
+
L1_SHADOW_TAGS_MODULO 1
|
| 372 |
+
HIER_MSHR_ON FALSE
|
| 373 |
+
PERF_PRED_ENABLE FALSE
|
| 374 |
+
PERF_PRED_MECH PERF_PRED_CP
|
| 375 |
+
PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY
|
| 376 |
+
PERF_PRED_COUNT_ALL FALSE
|
| 377 |
+
PERF_PRED_COUNT_INST_MISSES TRUE
|
| 378 |
+
PERF_PRED_COUNT_PREFETCHES FALSE
|
| 379 |
+
PERF_PRED_COUNT_OFFPATH_REQS FALSE
|
| 380 |
+
PERF_PRED_COUNT_BW_REQS TRUE
|
| 381 |
+
PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE
|
| 382 |
+
PERF_PRED_SLACK_PERIOD_SIZE 32
|
| 383 |
+
PERF_PRED_REQS_FINISH_AT_FILL FALSE
|
| 384 |
+
PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE
|
| 385 |
+
PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE
|
| 386 |
+
DUMB_MODEL_AVG_REQ_DISTANCE 100
|
| 387 |
+
DUMB_MODEL_RANDOMIZE_DISTANCE FALSE
|
| 388 |
+
DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL
|
| 389 |
+
DUMB_MODEL_AVG_ROW_HITS 1
|
| 390 |
+
DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL
|
| 391 |
+
DUMB_MODEL_MLP 1
|
| 392 |
+
DUMB_MODEL_MLP_PER_CORE NULL
|
| 393 |
+
RAMULATOR_STANDARD "DDR4" DDR4
|
| 394 |
+
RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R
|
| 395 |
+
RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8
|
| 396 |
+
RAMULATOR_CHANNELS 1 1
|
| 397 |
+
RAMULATOR_RANKS 1 1
|
| 398 |
+
RAMULATOR_BANKGROUPS 4 4
|
| 399 |
+
RAMULATOR_BANKS 4 4
|
| 400 |
+
RAMULATOR_CHIP_WIDTH 8 8
|
| 401 |
+
BUS_WIDTH_IN_BYTES 8 8
|
| 402 |
+
RAMULATOR_ROWS 65536 65536
|
| 403 |
+
RAMULATOR_COLS 1024 1024
|
| 404 |
+
RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap
|
| 405 |
+
RAMULATOR_READQ_ENTRIES 32 32
|
| 406 |
+
RAMULATOR_WRITEQ_ENTRIES 32 32
|
| 407 |
+
RAMULATOR_REC_CMD_TRACE "off" FALSE
|
| 408 |
+
RAMULATOR_PRINT_CMD_TRACE "off" FALSE
|
| 409 |
+
RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on"
|
| 410 |
+
RAMULATOR_TCK 833333 833333
|
| 411 |
+
RAMULATOR_TCL 16 16
|
| 412 |
+
RAMULATOR_TCCD 6 6
|
| 413 |
+
RAMULATOR_TCCDS 4 4
|
| 414 |
+
RAMULATOR_TCCDL 6 6
|
| 415 |
+
RAMULATOR_TCWL 12 12
|
| 416 |
+
RAMULATOR_TBL 4 4
|
| 417 |
+
RAMULATOR_TWTR 9 9
|
| 418 |
+
RAMULATOR_TWTRS 3 3
|
| 419 |
+
RAMULATOR_TWTRL 9 9
|
| 420 |
+
RAMULATOR_TRP 16 16
|
| 421 |
+
RAMULATOR_TRPpb 16 16
|
| 422 |
+
RAMULATOR_TRPab 16 16
|
| 423 |
+
RAMULATOR_TRCD 16 16
|
| 424 |
+
RAMULATOR_TRCDR 16 16
|
| 425 |
+
RAMULATOR_TRCDW 16 16
|
| 426 |
+
RAMULATOR_TRAS 39 39
|
| 427 |
+
DRAM_TECH_IN_NM 32 32
|
| 428 |
+
DVFS_ON FALSE
|
| 429 |
+
DVFS_METRIC DVFS_METRIC_NUM_ELEMS
|
| 430 |
+
DVFS_CONFIGS NULL
|
| 431 |
+
DVFS_CONFIG_FILE NULL
|
| 432 |
+
DVFS_START "t:0"
|
| 433 |
+
DVFS_PERIOD "t:312500000000"
|
| 434 |
+
DVFS_LOG TRUE
|
| 435 |
+
DVFS_INDIVIDUAL_CORES FALSE
|
| 436 |
+
DVFS_CHIP_LEVEL FALSE
|
| 437 |
+
DVFS_STATIC NULL
|
| 438 |
+
DVFS_FORCE_CONFIG NULL
|
| 439 |
+
DVFS_REPLAY_CONFIG_TRACE NULL
|
| 440 |
+
DVFS_USE_ORACLE FALSE
|
| 441 |
+
DVFS_USE_BW_SHARING FALSE
|
| 442 |
+
DVFS_USE_DRAM_SHARING FALSE
|
| 443 |
+
DVFS_USE_STALL_TIME FALSE
|
| 444 |
+
DVFS_DRAM_SHARING_SOLVER_BIN NULL
|
| 445 |
+
DVFS_DRAM_SHARING_SOLVER_STRICT TRUE
|
| 446 |
+
DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95
|
| 447 |
+
DVFS_BW_SHARING_MAX_REQS 28.0
|
| 448 |
+
DVFS_BW_SHARING_MAX_RW_COST 0.25
|
| 449 |
+
DVFS_BW_SHARING_NO_PREF_STALL TRUE
|
| 450 |
+
DVFS_BW_SHARING_CRIT_STATS TRUE
|
| 451 |
+
DVFS_COUNT_L1_ACCESS_STALL FALSE
|
| 452 |
+
NUM_CORES 1
|
| 453 |
+
CHIP_CYCLE_TIME 312500 312500
|
| 454 |
+
CORE_0_CYCLE_TIME 312500
|
| 455 |
+
CORE_1_CYCLE_TIME 312500
|
| 456 |
+
CORE_2_CYCLE_TIME 312500
|
| 457 |
+
CORE_3_CYCLE_TIME 312500
|
| 458 |
+
CORE_4_CYCLE_TIME 312500
|
| 459 |
+
CORE_5_CYCLE_TIME 312500
|
| 460 |
+
CORE_6_CYCLE_TIME 312500
|
| 461 |
+
CORE_7_CYCLE_TIME 312500
|
| 462 |
+
CORE_8_CYCLE_TIME 312500
|
| 463 |
+
CORE_9_CYCLE_TIME 312500
|
| 464 |
+
CORE_10_CYCLE_TIME 312500
|
| 465 |
+
CORE_11_CYCLE_TIME 312500
|
| 466 |
+
CORE_12_CYCLE_TIME 312500
|
| 467 |
+
CORE_13_CYCLE_TIME 312500
|
| 468 |
+
CORE_14_CYCLE_TIME 312500
|
| 469 |
+
CORE_15_CYCLE_TIME 312500
|
| 470 |
+
CORE_16_CYCLE_TIME 312500
|
| 471 |
+
CORE_17_CYCLE_TIME 312500
|
| 472 |
+
CORE_18_CYCLE_TIME 312500
|
| 473 |
+
CORE_19_CYCLE_TIME 312500
|
| 474 |
+
CORE_20_CYCLE_TIME 312500
|
| 475 |
+
CORE_21_CYCLE_TIME 312500
|
| 476 |
+
CORE_22_CYCLE_TIME 312500
|
| 477 |
+
CORE_23_CYCLE_TIME 312500
|
| 478 |
+
CORE_24_CYCLE_TIME 312500
|
| 479 |
+
CORE_25_CYCLE_TIME 312500
|
| 480 |
+
CORE_26_CYCLE_TIME 312500
|
| 481 |
+
CORE_27_CYCLE_TIME 312500
|
| 482 |
+
CORE_28_CYCLE_TIME 312500
|
| 483 |
+
CORE_29_CYCLE_TIME 312500
|
| 484 |
+
CORE_30_CYCLE_TIME 312500
|
| 485 |
+
CORE_31_CYCLE_TIME 312500
|
| 486 |
+
CORE_32_CYCLE_TIME 312500
|
| 487 |
+
CORE_33_CYCLE_TIME 312500
|
| 488 |
+
CORE_34_CYCLE_TIME 312500
|
| 489 |
+
CORE_35_CYCLE_TIME 312500
|
| 490 |
+
CORE_36_CYCLE_TIME 312500
|
| 491 |
+
CORE_37_CYCLE_TIME 312500
|
| 492 |
+
CORE_38_CYCLE_TIME 312500
|
| 493 |
+
CORE_39_CYCLE_TIME 312500
|
| 494 |
+
CORE_40_CYCLE_TIME 312500
|
| 495 |
+
CORE_41_CYCLE_TIME 312500
|
| 496 |
+
CORE_42_CYCLE_TIME 312500
|
| 497 |
+
CORE_43_CYCLE_TIME 312500
|
| 498 |
+
CORE_44_CYCLE_TIME 312500
|
| 499 |
+
CORE_45_CYCLE_TIME 312500
|
| 500 |
+
CORE_46_CYCLE_TIME 312500
|
| 501 |
+
CORE_47_CYCLE_TIME 312500
|
| 502 |
+
CORE_48_CYCLE_TIME 312500
|
| 503 |
+
CORE_49_CYCLE_TIME 312500
|
| 504 |
+
CORE_50_CYCLE_TIME 312500
|
| 505 |
+
CORE_51_CYCLE_TIME 312500
|
| 506 |
+
CORE_52_CYCLE_TIME 312500
|
| 507 |
+
CORE_53_CYCLE_TIME 312500
|
| 508 |
+
CORE_54_CYCLE_TIME 312500
|
| 509 |
+
CORE_55_CYCLE_TIME 312500
|
| 510 |
+
CORE_56_CYCLE_TIME 312500
|
| 511 |
+
CORE_57_CYCLE_TIME 312500
|
| 512 |
+
CORE_58_CYCLE_TIME 312500
|
| 513 |
+
CORE_59_CYCLE_TIME 312500
|
| 514 |
+
CORE_60_CYCLE_TIME 312500
|
| 515 |
+
CORE_61_CYCLE_TIME 312500
|
| 516 |
+
CORE_62_CYCLE_TIME 312500
|
| 517 |
+
CORE_63_CYCLE_TIME 312500
|
| 518 |
+
TOPDOWN_FU_EXEC_FEW 0
|
| 519 |
+
ISSUE_WIDTH 4 6
|
| 520 |
+
RS_FILL_WIDTH 8 0
|
| 521 |
+
NODE_TABLE_SIZE 256 512
|
| 522 |
+
NODE_RET_WIDTH 4 8
|
| 523 |
+
NODE_RETIRE_RATE 10
|
| 524 |
+
DECODE_WIDTH 4 6
|
| 525 |
+
IDQ_SIZE 140 144
|
| 526 |
+
REG_RENAMING_SCHEME 0 1
|
| 527 |
+
REG_TABLE_INTEGER_PHYSICAL_SIZE 256 280
|
| 528 |
+
REG_TABLE_VECTOR_PHYSICAL_SIZE 256 332
|
| 529 |
+
REG_TABLE_INTEGER_VIRTUAL_SIZE 256
|
| 530 |
+
REG_TABLE_VECTOR_VIRTUAL_SIZE 256
|
| 531 |
+
REG_RENAMING_MOVE_ELIMINATE FALSE
|
| 532 |
+
NODE_ISSUE_QUEUE_DISPATCH_SCHEME 0
|
| 533 |
+
NODE_ISSUE_QUEUE_SCHEDULE_SCHEME 0
|
| 534 |
+
ISSUE_QUEUE_PARALLEL_PICK FALSE
|
| 535 |
+
RS_SIZES "256" 97 70 19
|
| 536 |
+
RS_CONNECTIONS "xF" b0100110011 b1000001100 b0011000000
|
| 537 |
+
FU_TYPES "0, 0, 0, 0" b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 538 |
+
LSQ_ENABLE TRUE
|
| 539 |
+
LOAD_QUEUE_ENTRY_NUM 128
|
| 540 |
+
STORE_QUEUE_ENTRY_NUM 72
|
| 541 |
+
DECODE_CYCLES 1 5
|
| 542 |
+
MAP_CYCLES 1 5
|
| 543 |
+
ICACHE_LATENCY 3
|
| 544 |
+
EXTRA_REDIRECT_CYCLES 0
|
| 545 |
+
EXTRA_RECOVERY_CYCLES 0
|
| 546 |
+
EXTRA_CALLSYS_CYCLES 20 const
|
| 547 |
+
DIE_ON_CALLSYS FALSE
|
| 548 |
+
DIE_ON_RET_STALL_THRESH 0
|
| 549 |
+
DIE_ON_RET_STALL_CORE 0
|
| 550 |
+
DIE_ON_MEM_BLOCK_THRESH 0
|
| 551 |
+
DIE_ON_MEM_BLOCK_CORE 0
|
| 552 |
+
ICACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 553 |
+
UOP_CACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 554 |
+
FETCH_OFF_PATH_OPS TRUE 1
|
| 555 |
+
WP_COLLECT_STATS TRUE
|
| 556 |
+
OP_INV_DELAY 1
|
| 557 |
+
OP_NOP_DELAY 1
|
| 558 |
+
OP_CF_DELAY 1
|
| 559 |
+
OP_MOV_DELAY 1
|
| 560 |
+
OP_CMOV_DELAY 1
|
| 561 |
+
OP_LDA_DELAY 1
|
| 562 |
+
OP_ILD_DELAY 1
|
| 563 |
+
OP_IST_DELAY 1
|
| 564 |
+
OP_IADD_DELAY 1
|
| 565 |
+
OP_IMUL_DELAY 3
|
| 566 |
+
OP_IDIV_DELAY -20
|
| 567 |
+
OP_ICMP_DELAY 1
|
| 568 |
+
OP_LOGIC_DELAY 1
|
| 569 |
+
OP_SHIFT_DELAY 1
|
| 570 |
+
OP_FLD_DELAY 1
|
| 571 |
+
OP_FST_DELAY 1
|
| 572 |
+
OP_FCVT_DELAY 3
|
| 573 |
+
OP_FADD_DELAY 3
|
| 574 |
+
OP_FMUL_DELAY 5
|
| 575 |
+
OP_FMA_DELAY 5
|
| 576 |
+
OP_FDIV_DELAY -20
|
| 577 |
+
OP_FCMP_DELAY 3
|
| 578 |
+
OP_FCMOV_DELAY 1
|
| 579 |
+
OP_GATHER_DELAY 12
|
| 580 |
+
OP_SCATTER_DELAY 18
|
| 581 |
+
OP_PIPELINED_FAST_DELAY 2
|
| 582 |
+
OP_PIPELINED_MEDIUM_DELAY 5
|
| 583 |
+
OP_PIPELINED_SLOW_DELAY 10
|
| 584 |
+
OP_NOTPIPELINED_MEDIUM_DELAY -5
|
| 585 |
+
OP_NOTPIPELINED_SLOW_DELAY -20
|
| 586 |
+
OP_NOTPIPELINED_VERY_SLOW_DELAY -100
|
| 587 |
+
UNIFORM_OP_DELAY 0
|
| 588 |
+
STALL_ON_WAIT_MEM TRUE
|
| 589 |
+
STORES_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 590 |
+
PREFS_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 591 |
+
OBEY_REG_DEP TRUE
|
| 592 |
+
TRACK_L1_MISS_DEPS FALSE
|
| 593 |
+
CBP_TRACE_R0 NULL /dev/shm/baseline/traces/.staging/tsp-164844/raw_trace/drmemtrace.tsp.164856.4389.dir/trace/drmemtrace.tsp.164856.1160.trace.zip
|
| 594 |
+
CBP_TRACE_R1 NULL
|
| 595 |
+
CBP_TRACE_R2 NULL
|
| 596 |
+
CBP_TRACE_R3 NULL
|
| 597 |
+
CBP_TRACE_R4 NULL
|
| 598 |
+
CBP_TRACE_R5 NULL
|
| 599 |
+
CBP_TRACE_R6 NULL
|
| 600 |
+
CBP_TRACE_R7 NULL
|
| 601 |
+
CBP_TRACE_R8 NULL
|
| 602 |
+
CBP_TRACE_R9 NULL
|
| 603 |
+
CBP_TRACE_R10 NULL
|
| 604 |
+
CBP_TRACE_R11 NULL
|
| 605 |
+
CBP_TRACE_R12 NULL
|
| 606 |
+
CBP_TRACE_R13 NULL
|
| 607 |
+
CBP_TRACE_R14 NULL
|
| 608 |
+
CBP_TRACE_R15 NULL
|
| 609 |
+
CBP_TRACE_R16 NULL
|
| 610 |
+
CBP_TRACE_R17 NULL
|
| 611 |
+
CBP_TRACE_R18 NULL
|
| 612 |
+
CBP_TRACE_R19 NULL
|
| 613 |
+
CBP_TRACE_R20 NULL
|
| 614 |
+
CBP_TRACE_R21 NULL
|
| 615 |
+
CBP_TRACE_R22 NULL
|
| 616 |
+
CBP_TRACE_R23 NULL
|
| 617 |
+
CBP_TRACE_R24 NULL
|
| 618 |
+
CBP_TRACE_R25 NULL
|
| 619 |
+
CBP_TRACE_R26 NULL
|
| 620 |
+
CBP_TRACE_R27 NULL
|
| 621 |
+
CBP_TRACE_R28 NULL
|
| 622 |
+
CBP_TRACE_R29 NULL
|
| 623 |
+
CBP_TRACE_R30 NULL
|
| 624 |
+
CBP_TRACE_R31 NULL
|
| 625 |
+
CBP_TRACE_R32 NULL
|
| 626 |
+
CBP_TRACE_R33 NULL
|
| 627 |
+
CBP_TRACE_R34 NULL
|
| 628 |
+
CBP_TRACE_R35 NULL
|
| 629 |
+
CBP_TRACE_R36 NULL
|
| 630 |
+
CBP_TRACE_R37 NULL
|
| 631 |
+
CBP_TRACE_R38 NULL
|
| 632 |
+
CBP_TRACE_R39 NULL
|
| 633 |
+
CBP_TRACE_R40 NULL
|
| 634 |
+
CBP_TRACE_R41 NULL
|
| 635 |
+
CBP_TRACE_R42 NULL
|
| 636 |
+
CBP_TRACE_R43 NULL
|
| 637 |
+
CBP_TRACE_R44 NULL
|
| 638 |
+
CBP_TRACE_R45 NULL
|
| 639 |
+
CBP_TRACE_R46 NULL
|
| 640 |
+
CBP_TRACE_R47 NULL
|
| 641 |
+
CBP_TRACE_R48 NULL
|
| 642 |
+
CBP_TRACE_R49 NULL
|
| 643 |
+
CBP_TRACE_R50 NULL
|
| 644 |
+
CBP_TRACE_R51 NULL
|
| 645 |
+
CBP_TRACE_R52 NULL
|
| 646 |
+
CBP_TRACE_R53 NULL
|
| 647 |
+
CBP_TRACE_R54 NULL
|
| 648 |
+
CBP_TRACE_R55 NULL
|
| 649 |
+
CBP_TRACE_R56 NULL
|
| 650 |
+
CBP_TRACE_R57 NULL
|
| 651 |
+
CBP_TRACE_R58 NULL
|
| 652 |
+
CBP_TRACE_R59 NULL
|
| 653 |
+
CBP_TRACE_R60 NULL
|
| 654 |
+
CBP_TRACE_R61 NULL
|
| 655 |
+
CBP_TRACE_R62 NULL
|
| 656 |
+
CBP_TRACE_R63 NULL
|
| 657 |
+
FE_FTQ_BLOCK_NUM 32
|
| 658 |
+
FE_FTQ_TAKEN_CFS_PER_CYCLE 2
|
| 659 |
+
FE_FTQ_FT_PER_CYCLE 1
|
| 660 |
+
DUMB_CORE_ON FALSE
|
| 661 |
+
DUMB_CORE 1
|
| 662 |
+
DCACHE_MISS_RATE 10
|
| 663 |
+
L1_MISS_RATE 10
|
| 664 |
+
TRACE_BUF_SIZE 0
|
| 665 |
+
PERFECT_CONFIDENCE FALSE
|
| 666 |
+
CONFIDENCE_ENABLE FALSE
|
| 667 |
+
CONFIDENCE_MECH 0
|
| 668 |
+
CONF_OFF_PATH_THRESHOLD 15
|
| 669 |
+
CONF_OFF_PATH_INC 5
|
| 670 |
+
CONF_BTB_MISS_BP_TAKEN FALSE
|
| 671 |
+
CONF_IPC_RATE_CONF FALSE
|
| 672 |
+
CONF_BTB_MISS_BP_TAKEN_THRESHOLD 0
|
| 673 |
+
CONF_BTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 674 |
+
CONF_IBTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 675 |
+
CONF_MISFETCH_RATE_CYCLES_THRESHOLD 1.0
|
| 676 |
+
CONF_MISPRED_RATE_CYCLES_THRESHOLD 1.0
|
| 677 |
+
CONF_BTB_MISS_SAMPLE_RATE 100000
|
| 678 |
+
CONF_IBTB_MISS_SAMPLE_RATE 100000
|
| 679 |
+
CONF_MISFETCH_SAMPLE_RATE 100000
|
| 680 |
+
CONF_MISPRED_SAMPLE_RATE 100000
|
| 681 |
+
CONF_IPC_SAMPLE_RATE 100000
|
| 682 |
+
CONF_BTB_MISS_RATE_WEIGHT 200
|
| 683 |
+
CONF_BTB_MISS_BP_TAKEN_CONF TRUE
|
| 684 |
+
CONF_IBTB_MISS_BP_TAKEN_CONF TRUE
|
| 685 |
+
CONF_BTB_MISS_RATE_CONF TRUE
|
| 686 |
+
CONF_IBTB_MISS_RATE_CONF TRUE
|
| 687 |
+
CONF_MISFETCH_RATE_CONF TRUE
|
| 688 |
+
CONF_MISPRED_RATE_CONF TRUE
|
| 689 |
+
CONF_INV_BP_CONF TRUE
|
| 690 |
+
CONF_PERFECT_BTB_MISS_CONF FALSE
|
| 691 |
+
CONF_PERFECT_IBTB_MISS_CONF FALSE
|
| 692 |
+
CONF_PERFECT_MISFETCH_CONF FALSE
|
| 693 |
+
CONF_PERFECT_MISPRED_CONF FALSE
|
| 694 |
+
CONF_LOG_DFE_TO_REC FALSE
|
| 695 |
+
CONF_LOG_PHASE_CYCLES FALSE
|
| 696 |
+
NUM_BPS 1
|
| 697 |
+
DFE0_TRIGGER_POLICY 0
|
| 698 |
+
DFE1_TRIGGER_POLICY 1
|
| 699 |
+
DFE2_TRIGGER_POLICY 1
|
| 700 |
+
DFE3_TRIGGER_POLICY 1
|
| 701 |
+
DFE4_TRIGGER_POLICY 1
|
| 702 |
+
DFE0_STOP_POLICY 0
|
| 703 |
+
DFE1_STOP_POLICY 1
|
| 704 |
+
DFE2_STOP_POLICY 1
|
| 705 |
+
DFE3_STOP_POLICY 1
|
| 706 |
+
DFE4_STOP_POLICY 1
|
| 707 |
+
LOOKAHEAD_BUF_SIZE 0
|
| 708 |
+
DEBUG_CYCLE_START 0 0
|
| 709 |
+
DEBUG_CYCLE_STOP 0 -1
|
| 710 |
+
DEBUG_TIME_START 0
|
| 711 |
+
DEBUG_TIME_STOP 0
|
| 712 |
+
DEBUG_INST_START 0 0
|
| 713 |
+
DEBUG_INST_STOP 0 -1
|
| 714 |
+
DEBUG_OP_START 0
|
| 715 |
+
DEBUG_OP_STOP 0
|
| 716 |
+
DEBUG_CACHE_LIB FALSE
|
| 717 |
+
DEBUG_HASH_LIB FALSE
|
| 718 |
+
DEBUG_LIST_LIB FALSE
|
| 719 |
+
DEBUG_PORT_LIB FALSE
|
| 720 |
+
DEBUG_BUS_LIB FALSE
|
| 721 |
+
DEBUG_OP_POOL FALSE
|
| 722 |
+
DEBUG_ORACLE FALSE
|
| 723 |
+
DEBUG_FRONTEND FALSE
|
| 724 |
+
DEBUG_ADDR_TRANS FALSE
|
| 725 |
+
DEBUG_BP FALSE
|
| 726 |
+
DEBUG_BP_DIR FALSE
|
| 727 |
+
DEBUG_BTB FALSE
|
| 728 |
+
DEBUG_CRS FALSE
|
| 729 |
+
DEBUG_MAP FALSE
|
| 730 |
+
DEBUG_MEMORY FALSE
|
| 731 |
+
DEBUG_REPLAY FALSE
|
| 732 |
+
DEBUG_FREQ FALSE
|
| 733 |
+
DEBUG_MODEL FALSE
|
| 734 |
+
DEBUG_THREAD FALSE
|
| 735 |
+
DEBUG_DECOUPLED_FE FALSE
|
| 736 |
+
DEBUG_CONF FALSE
|
| 737 |
+
DEBUG_ICACHE_STAGE FALSE
|
| 738 |
+
DEBUG_DECODE_STAGE FALSE
|
| 739 |
+
DEBUG_CPP_CACHE FALSE
|
| 740 |
+
DEBUG_UOP_CACHE FALSE
|
| 741 |
+
DEBUG_UOP_QUEUE_STAGE FALSE
|
| 742 |
+
DEBUG_IDQ_STAGE FALSE
|
| 743 |
+
DEBUG_MAP_STAGE FALSE
|
| 744 |
+
DEBUG_NODE_STAGE FALSE
|
| 745 |
+
DEBUG_EXEC_STAGE FALSE
|
| 746 |
+
DEBUG_DCACHE_STAGE FALSE
|
| 747 |
+
DEBUG_RETIRED_UOPS FALSE
|
| 748 |
+
DEBUG_EXC_INSERTS FALSE
|
| 749 |
+
DEBUG_BP_CONF FALSE
|
| 750 |
+
DEBUG_ONPATH_CONF FALSE
|
| 751 |
+
DEBUG_STREAM FALSE
|
| 752 |
+
DEBUG_STREAM_MEM FALSE
|
| 753 |
+
DEBUG_WAY FALSE
|
| 754 |
+
DEBUG_L2MARKV FALSE
|
| 755 |
+
DEBUG_L2L1PREF FALSE
|
| 756 |
+
DEBUG_PERF_PRED FALSE
|
| 757 |
+
DEBUG_POWER_UTILS FALSE
|
| 758 |
+
DEBUG_DVFS FALSE
|
| 759 |
+
DEBUG_TRACE_READ FALSE
|
| 760 |
+
DEBUG_INST_FIELDS FALSE
|
| 761 |
+
DEBUG_OP_FIELDS FALSE
|
| 762 |
+
DEBUG_PIN_EXEC_DRIVEN FALSE
|
| 763 |
+
DEBUG_CACHE_PART FALSE
|
| 764 |
+
DEBUG_OPTIMIZER2 FALSE
|
| 765 |
+
DEBUG_PREF FALSE
|
| 766 |
+
DEBUG_FDIP FALSE
|
| 767 |
+
DEBUG_EIP FALSE
|
| 768 |
+
DEBUG_DJOLT FALSE
|
| 769 |
+
DEBUG_FNLMMA FALSE
|
| 770 |
+
PERFECT_BP FALSE
|
| 771 |
+
PERFECT_BTB FALSE
|
| 772 |
+
PERFECT_IBP FALSE
|
| 773 |
+
PERFECT_CRS FALSE
|
| 774 |
+
PERFECT_CBR_BTB FALSE
|
| 775 |
+
PERFECT_NT_BTB FALSE 0 # deprecated, effectively always true.
|
| 776 |
+
CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle
|
| 777 |
+
UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 778 |
+
BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec.
|
| 779 |
+
BP_MECH TAGE64K_BP tage64k
|
| 780 |
+
BP_MECH_L0 BIMODAL_BP
|
| 781 |
+
BP_L0_LATENCY 1
|
| 782 |
+
BP_MAIN_LATENCY 3
|
| 783 |
+
BIMODAL_ENTRIES (4 * 1024)
|
| 784 |
+
HIST_LENGTH 16
|
| 785 |
+
PHT_CTR_BITS 2 const
|
| 786 |
+
BHT_ENTRIES (4 * 1024)
|
| 787 |
+
BHT_ASSOC 4
|
| 788 |
+
HYBRIDS_INDEX_LENGTH 16
|
| 789 |
+
HYBRIDG_HIST_LENGTH 16
|
| 790 |
+
HYBRIDP_HIST_LENGTH 16
|
| 791 |
+
FILTER_INDEX_LENGTH 16
|
| 792 |
+
USE_FILTER FALSE
|
| 793 |
+
INF_HYBRIDGP FALSE
|
| 794 |
+
BP_HASH_TOS FALSE
|
| 795 |
+
IBTB_HASH_TOS FALSE
|
| 796 |
+
BTB_MECH GENERIC_BTB generic
|
| 797 |
+
BTB_ENTRIES 12288 12288
|
| 798 |
+
BTB_ASSOC 4 4
|
| 799 |
+
BTB_NUM_BRSLOT 1
|
| 800 |
+
BTB_BLOCK_SIZE 64
|
| 801 |
+
BTB_OFF_PATH_WRITES TRUE 1
|
| 802 |
+
BTB_MAIN_LATENCY 3 3
|
| 803 |
+
BTB_L0_PRESENT FALSE 1
|
| 804 |
+
BTB_L0_ENTRIES 128 128
|
| 805 |
+
BTB_L0_ASSOC 4 4
|
| 806 |
+
BTB_L0_LATENCY 1 1
|
| 807 |
+
BTB_L1_PRESENT FALSE 1
|
| 808 |
+
BTB_L1_ENTRIES 6144 6144
|
| 809 |
+
BTB_L1_ASSOC 4 4
|
| 810 |
+
BTB_L1_LATENCY 2 2
|
| 811 |
+
ENABLE_CRS TRUE 1
|
| 812 |
+
CRS_ENTRIES 32 128
|
| 813 |
+
CRS_REALISTIC 0 1
|
| 814 |
+
ENABLE_IBP TRUE 1 # Enable the indirect branch predictor
|
| 815 |
+
USE_PAT_HIST TRUE
|
| 816 |
+
IBTB_MECH 1 tc_tagged
|
| 817 |
+
IBTB_HIST_LENGTH 16
|
| 818 |
+
IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb.
|
| 819 |
+
TARGETS_IN_HIST 4
|
| 820 |
+
TC_ENTRIES (4 * 1024) 4096
|
| 821 |
+
TC_ASSOC 4 4
|
| 822 |
+
NUM_CORR_BRANCHES 3
|
| 823 |
+
SEL_HIST_BP_ENTRIES 8192
|
| 824 |
+
SEL_HIST_LENGTH 16
|
| 825 |
+
SEL_HIST_DYN_CNT_TH 16
|
| 826 |
+
SEL_HIST_MISPRED_TH 4
|
| 827 |
+
ENABLE_BP_CONF FALSE
|
| 828 |
+
CONF_MECH 0
|
| 829 |
+
PERF_BP_CONF_PRED FALSE
|
| 830 |
+
BPC_BITS 16
|
| 831 |
+
BPC_MECH 1
|
| 832 |
+
BPC_CTR_RESET TRUE
|
| 833 |
+
BPC_CIT_BITS 8
|
| 834 |
+
BPC_CIT_TH 50
|
| 835 |
+
BPC_CTR_BITS 3
|
| 836 |
+
OPC_COUNT_ZEROS FALSE
|
| 837 |
+
OPC_COUNT_THRESH 10
|
| 838 |
+
INF_LOOP FALSE
|
| 839 |
+
INF_LOOP_BUCKETS 811
|
| 840 |
+
LOOP_ENTRIES (4 * 1024)
|
| 841 |
+
LOOP_ASSOC 4
|
| 842 |
+
LOOP_COUNT_MAX 127
|
| 843 |
+
LOOP_REPEAT_MAX 15
|
| 844 |
+
KNOB_PRINT_BRINFO FALSE
|
| 845 |
+
BR_MISPRED_FILE NULL
|
| 846 |
+
SPEC_LEVEL 3
|
| 847 |
+
RANDOM_DETERMINISTIC TRUE
|
| 848 |
+
TAGESCL64KB_SC TRUE
|
| 849 |
+
TAGESCL64KB_LOOP TRUE
|
| 850 |
+
TAGESCL64KB_ALT TRUE
|
| 851 |
+
CONF_PERCEPTRON_TH 0
|
| 852 |
+
CONF_PERCEPTRON_CTR_BITS 8
|
| 853 |
+
CONF_PERCEPTRON_ENTRIES 127
|
| 854 |
+
CONF_PERCEPTRON_THRESH_OVRD 0
|
| 855 |
+
CONF_HIST_LENGTH 32
|
| 856 |
+
PERCEPTRON_CONF_USE_CONF FALSE
|
| 857 |
+
PERCEPTRON_CONF_TRAIN_HIS FALSE
|
| 858 |
+
PERCEPTRON_CONF_TRAIN_CONF FALSE
|
| 859 |
+
PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE
|
| 860 |
+
PERCEPTRON_TRAIN_MISP_FACTOR 1
|
| 861 |
+
PERCEPTRON_TRAIN_CORR_FACTOR 1
|
| 862 |
+
PERCEPTRON_CONF_HIS_BOTH FALSE
|
| 863 |
+
PERCEPTRON_CONF_HIS_BOTH_LENGTH 4
|
| 864 |
+
MTAGE_REALISTIC_SC_40K FALSE
|
| 865 |
+
MTAGE_REALISTIC_SC_100K FALSE
|
| 866 |
+
H2P_TABLE_BUCKETS 16384
|
| 867 |
+
H2P_MIN_EXEC 5000
|
| 868 |
+
H2P_MIN_MISPRED 333
|
| 869 |
+
H2P_MISPRED_RATIO_PERMIL 10
|
| 870 |
+
H2P_TRACK_CBR TRUE
|
| 871 |
+
H2P_TRACK_REP TRUE
|
| 872 |
+
H2P_TRACK_CALL FALSE
|
| 873 |
+
H2P_TRACK_IBR FALSE
|
| 874 |
+
H2P_TRACK_ICALL FALSE
|
| 875 |
+
H2P_TRACK_RET FALSE
|
| 876 |
+
POWER_INTF_ON FALSE
|
| 877 |
+
POWER_INTF_ENABLE_SCALING FALSE
|
| 878 |
+
POWER_INTF_EXEC "power/power_intf.py"
|
| 879 |
+
POWER_INTF_REF_CHIP_TECH_NM 22
|
| 880 |
+
POWER_INTF_REF_CHIP_FREQ (3.2e9)
|
| 881 |
+
POWER_INTF_REF_MEMORY_FREQ (0.8e9)
|
| 882 |
+
POWER_OTHER (0.0)
|
| 883 |
+
PREF_STREAM_ON FALSE 1
|
| 884 |
+
PREF_STREAM_PER_CORE_ENABLE FALSE
|
| 885 |
+
STREAM_BUFFER_N 16
|
| 886 |
+
STREAM_PREFETCH_N 2 4
|
| 887 |
+
STREAM_START_DIS 5 1
|
| 888 |
+
STREAM_LENGTH 16 64
|
| 889 |
+
STREAM_FULL_N 1
|
| 890 |
+
STREAM_TRAIN_LENGTH 16
|
| 891 |
+
STREAM_TRAIN_NUM 1 4
|
| 892 |
+
PREF_ACC_USE_CACHE FALSE
|
| 893 |
+
STREAM_STALL_ON_QUEUE_FULL FALSE
|
| 894 |
+
PREF_SCHEDULE_NUM 4
|
| 895 |
+
TRAIN_FILTER_SIZE 32
|
| 896 |
+
PREF_REQ_Q_SIZE 64
|
| 897 |
+
STREAM_CREATE_ON_DC_MISS FALSE 0
|
| 898 |
+
STREAM_CREATE_ON_L1_MISS TRUE 1
|
| 899 |
+
STREAM_TRAIN_ON_WRONGPATH TRUE
|
| 900 |
+
STREAM_CREATE_ON_WRONGPATH TRUE
|
| 901 |
+
STREAM_PREF_INTO_DCACHE FALSE
|
| 902 |
+
REMOVE_REDUNDANT_STREAM FALSE
|
| 903 |
+
L2HIT_STREAM_SCHEDULE_NUM 4
|
| 904 |
+
PREF_REQ_QUEUE_FILTER_ON FALSE
|
| 905 |
+
HW_PREF_HIT_TRAIN_STREAM FALSE
|
| 906 |
+
L2HIT_STREAM_BUFFER_N 32
|
| 907 |
+
L2HIT_STREAM_PREFETCH_N 2
|
| 908 |
+
L2HIT_STREAM_START_DIS 2
|
| 909 |
+
L2HIT_STREAM_LENGTH 8
|
| 910 |
+
L2HIT_PREF_REQ_Q_SIZE 128
|
| 911 |
+
L2HIT_L2ACCESS_REQ_Q_SIZE 64
|
| 912 |
+
PREF_STREAM_ACCPERSTREAM FALSE
|
| 913 |
+
PREF_ACC_DISTANCE_10 128
|
| 914 |
+
PREF_FRAMEWORK_ON FALSE 1
|
| 915 |
+
PREF_TRACE_ON FALSE
|
| 916 |
+
PREF_UMLC_ON FALSE
|
| 917 |
+
PREF_UL1_ON TRUE
|
| 918 |
+
PREF_DL0REQ_QUEUE_SIZE 32
|
| 919 |
+
PREF_UMLC_REQ_QUEUE_SIZE 64
|
| 920 |
+
PREF_UL1REQ_QUEUE_SIZE 128
|
| 921 |
+
PREF_SHARED_QUEUES TRUE
|
| 922 |
+
PREF_DL0_MISS_ON TRUE
|
| 923 |
+
PREF_DL0_HIT_ON TRUE
|
| 924 |
+
PREF_DL0REQ_QUEUE_FILTER_ON TRUE
|
| 925 |
+
PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE
|
| 926 |
+
PREF_UL1REQ_QUEUE_FILTER_ON TRUE
|
| 927 |
+
PREF_DL0REQ_ADD_FILTER_ON TRUE
|
| 928 |
+
PREF_UMLC_REQ_ADD_FILTER_ON TRUE
|
| 929 |
+
PREF_UL1REQ_ADD_FILTER_ON TRUE
|
| 930 |
+
PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 931 |
+
PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 932 |
+
PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1
|
| 933 |
+
PREF_DL0SCHEDULE_NUM 4
|
| 934 |
+
PREF_UMLC_SCHEDULE_NUM 4
|
| 935 |
+
PREF_UL1SCHEDULE_NUM 4
|
| 936 |
+
PREF_L1Q_DEMAND_RESERVE 0
|
| 937 |
+
PREF_REPORT_PREF_MATCH_AS_MISS FALSE
|
| 938 |
+
PREF_REPORT_PREF_MATCH_AS_HIT TRUE
|
| 939 |
+
PREF_UPDATE_ON_WRONGPATH TRUE
|
| 940 |
+
PREF_TRAIN_ON_PREF_MISSES FALSE 0
|
| 941 |
+
PREF_ORACLE_TRAIN_ON FALSE 0
|
| 942 |
+
PREF_REQ_DROP FALSE
|
| 943 |
+
PREF_THROTTLE_ON FALSE
|
| 944 |
+
PREF_THROTTLEFB_ON FALSE 1
|
| 945 |
+
PREF_ACC_THRESH_1 0.90 0.75
|
| 946 |
+
PREF_ACC_THRESH_2 0.70 0.4
|
| 947 |
+
PREF_ACC_THRESH_3 0.60 0.4
|
| 948 |
+
PREF_ACC_THRESH_4 0.40
|
| 949 |
+
PREF_UPDATE_INTERVAL 0 8192
|
| 950 |
+
PREF_ANALYZE_LOAD FALSE
|
| 951 |
+
PREF_POL_THRESH_1 0.25
|
| 952 |
+
PREF_POL_THRESH_2 0.10
|
| 953 |
+
PREF_POLBV_ON FALSE
|
| 954 |
+
PREF_POLBV_SIZE 1024
|
| 955 |
+
PREF_TIMELY_THRESH 0.05 0.01
|
| 956 |
+
PREF_POLPF_THRESH 0.01 0.005
|
| 957 |
+
PREF_DEGFB_USEONLYACC FALSE
|
| 958 |
+
PREF_DEGFB_USEONLYPOL FALSE
|
| 959 |
+
PREF_DEGFB_USEONLYLATE FALSE
|
| 960 |
+
PREF_TIMELY_THRESH_2 0.005
|
| 961 |
+
PREF_DEGFB_STATPHASEFILE FALSE
|
| 962 |
+
PREF_MAX_DEGFB 4
|
| 963 |
+
PREF_DHAL FALSE
|
| 964 |
+
PREF_DHAL_SENTTHRESH 16
|
| 965 |
+
PREF_DHAL_USETHRESH_MAX 12
|
| 966 |
+
PREF_DHAL_USETHRESH_MIN2 8
|
| 967 |
+
PREF_DHAL_USETHRESH_MIN1 4
|
| 968 |
+
PREF_DHAL_MAXDEG 64
|
| 969 |
+
PREF_HFILTER_ON FALSE
|
| 970 |
+
PREF_HFILTER_INDEX_BITS 12
|
| 971 |
+
PREF_HFILTER_USE_PC FALSE
|
| 972 |
+
PREF_HFILTER_PRED_USELESS_THRES 2
|
| 973 |
+
PREF_HFILTER_RESET_ENABLE FALSE
|
| 974 |
+
PREF_HFILTER_RESET_INTERVAL 100000
|
| 975 |
+
EIP_ENABLE 0
|
| 976 |
+
L1I_ENTANGLED_TABLE_INDEX_BITS 9
|
| 977 |
+
L1I_ENTANGLED_TABLE_WAYS 16
|
| 978 |
+
DJOLT_ENABLE 0
|
| 979 |
+
FNLMMA_ENABLE 0
|
| 980 |
+
FDIP_ENABLE 1
|
| 981 |
+
FDIP_ALWAYS_PREFETCH FALSE
|
| 982 |
+
PERFECT_FDIP FALSE
|
| 983 |
+
IPRF_MAX_FTQ_ENTRY_CYC 2
|
| 984 |
+
FDIP_BLOOM_FILTER FALSE
|
| 985 |
+
FDIP_BLOOM_ENTRIES 4000
|
| 986 |
+
FDIP_BLOOM2_ENTRIES 1000
|
| 987 |
+
FDIP_BLOOM4_ENTRIES 1000
|
| 988 |
+
FDIP_BLOOM_SIZE 16384
|
| 989 |
+
FDIP_BLOOM_HASHES 6
|
| 990 |
+
FDIP_BLOOM_CLEAR_UNUSEFUL_RATIO 0.95
|
| 991 |
+
FDIP_BLOOM_CLEAR_CYC_PERIOD 10000
|
| 992 |
+
FDIP_UTILITY_HASH_ENABLE 0
|
| 993 |
+
FDIP_UTILITY_PREF_POLICY 0
|
| 994 |
+
FDIP_ADJUSTABLE_FTQ 0
|
| 995 |
+
FDIP_ADJUSTABLE_FTQ_CYC 100000
|
| 996 |
+
UTILITY_RATIO_THRESHOLD 0.58
|
| 997 |
+
TIMELINESS_RATIO_THRESHOLD 0.82
|
| 998 |
+
FDIP_PREF_NO_LATENCY FALSE
|
| 999 |
+
UDP_USEFUL_THRESHOLD 0
|
| 1000 |
+
UDP_WEIGHT_USEFUL 4
|
| 1001 |
+
UDP_WEIGHT_UNUSEFUL 1
|
| 1002 |
+
UDP_WEIGHT_POSITIVE_SATURATION 2147483647
|
| 1003 |
+
FDIP_GHIST_HASHING FALSE
|
| 1004 |
+
FDIP_UTILITY_ONLY_TRAIN_OFF_PATH FALSE
|
| 1005 |
+
FDIP_GHIST_BITS 8
|
| 1006 |
+
UFTQ_MIN_FTQ_BLOCK_NUM 4
|
| 1007 |
+
UFTQ_MAX_FTQ_BLOCK_NUM 64
|
| 1008 |
+
FDIP_SENIORITY_FTQ_HOLD_CYC 30000
|
| 1009 |
+
FDIP_PERFECT_PREFETCH FALSE
|
| 1010 |
+
FDIP_FREEZE_AT_MEM_BUF_LIMIT TRUE
|
| 1011 |
+
FDIP_DUAL_PATH_PREF_IC_ENABLE FALSE
|
| 1012 |
+
FDIP_DUAL_PATH_PREF_UOC_ENABLE FALSE
|
| 1013 |
+
TOP_MISPRED_BR_FILEPATH "br_resteer_coverage.csv"
|
| 1014 |
+
TOP_MISPRED_BR_RESTEER_COVERAGE 0
|
| 1015 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_ENABLE FALSE
|
| 1016 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_MISPRED_THRESHOLD 1
|
| 1017 |
+
FDIP_PRINT_CL_INFO FALSE
|
| 1018 |
+
BRANCH_MISPREDICTION_TABLE_SIZE 0
|
| 1019 |
+
UOC_PREF FALSE
|
| 1020 |
+
UOC_ORACLE_PREF FALSE
|
| 1021 |
+
UOC_ZERO_LATENCY_PREF FALSE
|
| 1022 |
+
L2L1PREF_ON FALSE
|
| 1023 |
+
L2WAY_PREF FALSE
|
| 1024 |
+
L2MARKV_PREF_ON FALSE
|
| 1025 |
+
L2NEXT_PREF_ON FALSE
|
| 1026 |
+
L2HIT_STREAM_PREF_ON FALSE
|
| 1027 |
+
L2L1_DC_HIT_TRAIN FALSE
|
| 1028 |
+
L1_HIT_DUMP_FILE_ON FALSE
|
| 1029 |
+
L1_HIT_DUMP_WO_TXT FALSE
|
| 1030 |
+
L1_HIT_DUMPFILE "l1hit_dump.out"
|
| 1031 |
+
IDEAL_L2_L1_PREFETCHER FALSE
|
| 1032 |
+
IDEAL_L2_ICACHE_PREFETCHER FALSE
|
| 1033 |
+
L1WAY_PREF_SEND_QUEUE 4
|
| 1034 |
+
L1PREF_REQ_QUEUE_SIZE 1024
|
| 1035 |
+
L1PREF_IMMEDIATE FALSE
|
| 1036 |
+
L1WAY_PREF_TIMER_DIS 1000
|
| 1037 |
+
L1MARKV_PREF_SEND_QUEUE 4
|
| 1038 |
+
L1PREF_MARKV_REQ_QUEUE_SIZE 1024
|
| 1039 |
+
MARKV_L2ACCESS_REQ_Q_SIZE 64
|
| 1040 |
+
L1MARKV_PREF_IMMEDIATE FALSE
|
| 1041 |
+
L1MARKV_PREF_TIMER_DIS 1
|
| 1042 |
+
L2L1_HIT_TRAIN TRUE
|
| 1043 |
+
L1MARKV_REQ_TH 1
|
| 1044 |
+
L2L1_IMMEDIATE_PREF_CACHE FALSE
|
| 1045 |
+
L2L1_FILL_PREF_CACHE FALSE
|
| 1046 |
+
L2L1_L2_HIT_STAT FALSE
|
| 1047 |
+
PREF_GHB_ON FALSE
|
| 1048 |
+
DEBUG_PREF_GHB FALSE
|
| 1049 |
+
PREF_GHB_BUFFER_N 1024
|
| 1050 |
+
PREF_GHB_INDEX_N 128
|
| 1051 |
+
PREF_GHB_CZONE_BITS 12
|
| 1052 |
+
PREF_GHB_DEGREE 16
|
| 1053 |
+
PREF_GHB_MAX_DEGREE 32
|
| 1054 |
+
PREF_STRIDE_ON FALSE
|
| 1055 |
+
DEBUG_PREF_STRIDE FALSE
|
| 1056 |
+
PREF_STRIDE_TABLE_N 1024
|
| 1057 |
+
PREF_STRIDE_REGION_BITS 16
|
| 1058 |
+
PREF_STRIDE_DEGREE 4
|
| 1059 |
+
PREF_STRIDE_DISTANCE 16
|
| 1060 |
+
PREF_STRIDE_STARTDISTANCE 1
|
| 1061 |
+
PREF_STRIDE_SINGLE_THRESH 6
|
| 1062 |
+
PREF_STRIDE_MULTI_THRESH 6
|
| 1063 |
+
PREF_STRIDE_SINGLE_STRIDE_MODE FALSE
|
| 1064 |
+
PREF_STRIDEPC_ON FALSE
|
| 1065 |
+
DEBUG_PREF_STRIDEPC FALSE
|
| 1066 |
+
PREF_STRIDEPC_TABLE_N 1024
|
| 1067 |
+
PREF_STRIDEPC_DEGREE 4
|
| 1068 |
+
PREF_STRIDEPC_DISTANCE 16
|
| 1069 |
+
PREF_STRIDEPC_USELOADADDR FALSE
|
| 1070 |
+
PREF_STRIDEPC_TRAINNUM 2
|
| 1071 |
+
PREF_STRIDEPC_STARTDIS 4
|
| 1072 |
+
PREF_PHASE_ON FALSE
|
| 1073 |
+
PREF_PHASE_STUDY FALSE
|
| 1074 |
+
DEBUG_PREF_PHASE FALSE
|
| 1075 |
+
PREF_PHASE_PRIME_HASH 16381
|
| 1076 |
+
PREF_PHASE_INFOSIZE 16384
|
| 1077 |
+
PREF_PHASE_LOG2REGIONSIZE 12
|
| 1078 |
+
PREF_PHASE_REGIONENTRIES 64
|
| 1079 |
+
PREF_PHASE_TRACKEDREGIONS 32
|
| 1080 |
+
PREF_PHASE_INTERVAL 100000
|
| 1081 |
+
PREF_PHASE_TABLE_SIZE 64
|
| 1082 |
+
PREF_PHASE_MAXDIFF_THRESH 64
|
| 1083 |
+
PREF_PHASE_MIN_MISSES 64
|
| 1084 |
+
PREF_PHASE_MISSPER 0.4
|
| 1085 |
+
PREF_2DC_ON FALSE
|
| 1086 |
+
DEBUG_PREF_2DC FALSE
|
| 1087 |
+
PREF_2DC_CACHE_SIZE (1 * 1024)
|
| 1088 |
+
PREF_2DC_CACHE_ASSOC 4
|
| 1089 |
+
PREF_2DC_CACHE_LINE_SIZE 1
|
| 1090 |
+
PREF_2DC_DEGREE 16
|
| 1091 |
+
PREF_2DC_ZONE_SHIFT 10
|
| 1092 |
+
PREF_2DC_TAG_SIZE 16
|
| 1093 |
+
PREF_2DC_NUM_REGIONS 64
|
| 1094 |
+
PREF_2DC_REGION_HASH 61
|
| 1095 |
+
PREF_MARKOV_ON FALSE
|
| 1096 |
+
DEBUG_PREF_MARKOV FALSE
|
| 1097 |
+
PREF_MARKOV_NUM_ENTRIES 65536
|
| 1098 |
+
PREF_MARKOV_NUM_NEXT_STATES 8
|
| 1099 |
+
PREF_MARKOV_SEND_ON_PREF_HIT TRUE
|
| 1100 |
+
PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE
|
| 1101 |
+
PREF_MARKOV_TABLE_UPDATE_POLICY 0
|
| 1102 |
+
PREF_MARKOV_SEND_THRESHOLD 0
|
tsp/fingerprint/run_0/sim.log
ADDED
|
@@ -0,0 +1,830 @@
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|
| 1 |
+
[0]: ad: 0x7ffff3d8e870, op: 427
|
| 2 |
+
[0]: ad: 0x7ffff3d8e87a, op: 109
|
| 3 |
+
[0]: ad: 0x7ffff3d8e87d, op: 98
|
| 4 |
+
[0]: ad: 0x7ffff3d8e881, op: 388
|
| 5 |
+
[0]: ad: 0x7ffff3d8e889, op: 316
|
| 6 |
+
new bb detected: 1
|
| 7 |
+
[1]: ad: 0x7ffff3d8e852, op: 427
|
| 8 |
+
[1]: ad: 0x7ffff3d8e855, op: 427
|
| 9 |
+
[1]: ad: 0x7ffff3d8e859, op: 75
|
| 10 |
+
new bb detected: 2
|
| 11 |
+
[2]: ad: 0x7ffff3d8d280, op: 482
|
| 12 |
+
[2]: ad: 0x7ffff3d8d284, op: 316
|
| 13 |
+
new bb detected: 3
|
| 14 |
+
[3]: ad: 0x7ffff733a970, op: 482
|
| 15 |
+
[3]: ad: 0x7ffff733a974, op: 847
|
| 16 |
+
[3]: ad: 0x7ffff733a977, op: 427
|
| 17 |
+
[3]: ad: 0x7ffff733a97c, op: 671
|
| 18 |
+
[3]: ad: 0x7ffff733a97d, op: 104
|
| 19 |
+
[3]: ad: 0x7ffff733a981, op: 427
|
| 20 |
+
[3]: ad: 0x7ffff733a984, op: 427
|
| 21 |
+
[3]: ad: 0x7ffff733a987, op: 75
|
| 22 |
+
new bb detected: 4
|
| 23 |
+
[4]: ad: 0x7ffff732b0d0, op: 482
|
| 24 |
+
[4]: ad: 0x7ffff732b0d4, op: 316
|
| 25 |
+
new bb detected: 5
|
| 26 |
+
[5]: ad: 0x7ffff71080a0, op: 482
|
| 27 |
+
[5]: ad: 0x7ffff71080a4, op: 671
|
| 28 |
+
[5]: ad: 0x7ffff71080a6, op: 671
|
| 29 |
+
[5]: ad: 0x7ffff71080a7, op: 427
|
| 30 |
+
[5]: ad: 0x7ffff71080aa, op: 671
|
| 31 |
+
[5]: ad: 0x7ffff71080ab, op: 826
|
| 32 |
+
[5]: ad: 0x7ffff71080af, op: 109
|
| 33 |
+
[5]: ad: 0x7ffff71080b6, op: 330
|
| 34 |
+
new bb detected: 6
|
| 35 |
+
[6]: ad: 0x7ffff71080bc, op: 847
|
| 36 |
+
[6]: ad: 0x7ffff71080bf, op: 329
|
| 37 |
+
new bb detected: 7
|
| 38 |
+
[7]: ad: 0x7ffff71080c5, op: 388
|
| 39 |
+
[7]: ad: 0x7ffff71080c9, op: 1723
|
| 40 |
+
[7]: ad: 0x7ffff71080cc, op: 109
|
| 41 |
+
[7]: ad: 0x7ffff71080d0, op: 319
|
| 42 |
+
new bb detected: 8
|
| 43 |
+
[8]: ad: 0x7ffff71081b0, op: 31
|
| 44 |
+
[8]: ad: 0x7ffff71081b4, op: 388
|
| 45 |
+
[8]: ad: 0x7ffff71081b8, op: 799
|
| 46 |
+
[8]: ad: 0x7ffff71081bc, op: 316
|
| 47 |
+
new bb detected: 9
|
| 48 |
+
[9]: ad: 0x7ffff71080d6, op: 427
|
| 49 |
+
[9]: ad: 0x7ffff71080dd, op: 427
|
| 50 |
+
[9]: ad: 0x7ffff71080e1, op: 847
|
| 51 |
+
[9]: ad: 0x7ffff71080e4, op: 330
|
| 52 |
+
new bb detected: 10
|
| 53 |
+
[10]: ad: 0x7ffff71080ea, op: 109
|
| 54 |
+
[10]: ad: 0x7ffff71080f1, op: 319
|
| 55 |
+
new bb detected: 11
|
| 56 |
+
[11]: ad: 0x7ffff7108200, op: 468
|
| 57 |
+
[11]: ad: 0x7ffff7108205, op: 847
|
| 58 |
+
[11]: ad: 0x7ffff7108208, op: 330
|
| 59 |
+
new bb detected: 12
|
| 60 |
+
[12]: ad: 0x7ffff710820e, op: 388
|
| 61 |
+
[12]: ad: 0x7ffff7108213, op: 427
|
| 62 |
+
[12]: ad: 0x7ffff7108217, op: 847
|
| 63 |
+
[12]: ad: 0x7ffff7108219, op: 325
|
| 64 |
+
new bb detected: 13
|
| 65 |
+
[13]: ad: 0x7ffff710821f, op: 427
|
| 66 |
+
[13]: ad: 0x7ffff7108222, op: 826
|
| 67 |
+
[13]: ad: 0x7ffff7108225, op: 799
|
| 68 |
+
[13]: ad: 0x7ffff7108229, op: 1723
|
| 69 |
+
[13]: ad: 0x7ffff710822c, op: 427
|
| 70 |
+
[13]: ad: 0x7ffff7108230, op: 427
|
| 71 |
+
[13]: ad: 0x7ffff7108235, op: 427
|
| 72 |
+
[13]: ad: 0x7ffff710823d, op: 8
|
| 73 |
+
[13]: ad: 0x7ffff7108241, op: 616
|
| 74 |
+
[13]: ad: 0x7ffff7108242, op: 616
|
| 75 |
+
[13]: ad: 0x7ffff7108243, op: 616
|
| 76 |
+
[13]: ad: 0x7ffff7108245, op: 740
|
| 77 |
+
new bb detected: 14
|
| 78 |
+
[14]: ad: 0x7ffff733a98c, op: 847
|
| 79 |
+
[14]: ad: 0x7ffff733a98f, op: 330
|
| 80 |
+
new bb detected: 15
|
| 81 |
+
[15]: ad: 0x7ffff733a991, op: 616
|
| 82 |
+
[15]: ad: 0x7ffff733a992, op: 740
|
| 83 |
+
new bb detected: 16
|
| 84 |
+
[16]: ad: 0x7ffff3d8e85e, op: 427
|
| 85 |
+
[16]: ad: 0x7ffff3d8e862, op: 427
|
| 86 |
+
[16]: ad: 0x7ffff3d8e865, op: 8
|
| 87 |
+
[16]: ad: 0x7ffff3d8e868, op: 316
|
| 88 |
+
new bb detected: 17
|
| 89 |
+
[17]: ad: 0x7ffff3d8e7bf, op: 427
|
| 90 |
+
[17]: ad: 0x7ffff3d8e7c2, op: 826
|
| 91 |
+
[17]: ad: 0x7ffff3d8e7c5, op: 388
|
| 92 |
+
[17]: ad: 0x7ffff3d8e7ca, op: 454
|
| 93 |
+
[17]: ad: 0x7ffff3d8e7cf, op: 427
|
| 94 |
+
[17]: ad: 0x7ffff3d8e7d2, op: 388
|
| 95 |
+
[17]: ad: 0x7ffff3d8e7d6, op: 454
|
| 96 |
+
[17]: ad: 0x7ffff3d8e7db, op: 669
|
| 97 |
+
[17]: ad: 0x7ffff3d8e7df, op: 429
|
| 98 |
+
[17]: ad: 0x7ffff3d8e7e3, op: 847
|
| 99 |
+
[17]: ad: 0x7ffff3d8e7e6, op: 321
|
| 100 |
+
new bb detected: 18
|
| 101 |
+
[18]: ad: 0x7ffff3d8e810, op: 427
|
| 102 |
+
[18]: ad: 0x7ffff3d8e813, op: 75
|
| 103 |
+
new bb detected: 19
|
| 104 |
+
[19]: ad: 0x7ffff3d8d2f0, op: 482
|
| 105 |
+
[19]: ad: 0x7ffff3d8d2f4, op: 316
|
| 106 |
+
new bb detected: 20
|
| 107 |
+
[20]: ad: 0x7ffff72037f0, op: 482
|
| 108 |
+
[20]: ad: 0x7ffff72037f4, op: 427
|
| 109 |
+
[20]: ad: 0x7ffff72037f7, op: 109
|
| 110 |
+
[20]: ad: 0x7ffff72037fb, op: 310
|
| 111 |
+
new bb detected: 21
|
| 112 |
+
[21]: ad: 0x7ffff7203801, op: 1232
|
| 113 |
+
[21]: ad: 0x7ffff7203805, op: 109
|
| 114 |
+
[21]: ad: 0x7ffff7203809, op: 319
|
| 115 |
+
new bb detected: 22
|
| 116 |
+
[22]: ad: 0x7ffff720380f, op: 1232
|
| 117 |
+
[22]: ad: 0x7ffff7203815, op: 1232
|
| 118 |
+
[22]: ad: 0x7ffff7203819, op: 1232
|
| 119 |
+
[22]: ad: 0x7ffff720381f, op: 1704
|
| 120 |
+
[22]: ad: 0x7ffff7203822, op: 740
|
| 121 |
+
new bb detected: 23
|
| 122 |
+
[23]: ad: 0x7ffff3d8e818, op: 847
|
| 123 |
+
[23]: ad: 0x7ffff3d8e81b, op: 321
|
| 124 |
+
new bb detected: 24
|
| 125 |
+
[24]: ad: 0x7ffff3d8e81d, op: 427
|
| 126 |
+
[24]: ad: 0x7ffff3d8e820, op: 75
|
| 127 |
+
new bb detected: 25
|
| 128 |
+
[25]: ad: 0x7ffff3d8d270, op: 482
|
| 129 |
+
[25]: ad: 0x7ffff3d8d274, op: 316
|
| 130 |
+
new bb detected: 26
|
| 131 |
+
[26]: ad: 0x7ffff7338c10, op: 482
|
| 132 |
+
[26]: ad: 0x7ffff7338c14, op: 316
|
| 133 |
+
new bb detected: 27
|
| 134 |
+
[27]: ad: 0x7ffff732bb30, op: 482
|
| 135 |
+
[27]: ad: 0x7ffff732bb34, op: 316
|
| 136 |
+
new bb detected: 28
|
| 137 |
+
[28]: ad: 0x7ffff71083e0, op: 482
|
| 138 |
+
[28]: ad: 0x7ffff71083e4, op: 847
|
| 139 |
+
[28]: ad: 0x7ffff71083e7, op: 330
|
| 140 |
+
new bb detected: 29
|
| 141 |
+
[29]: ad: 0x7ffff71083ed, op: 671
|
| 142 |
+
[29]: ad: 0x7ffff71083ee, op: 388
|
| 143 |
+
[29]: ad: 0x7ffff71083f2, op: 671
|
| 144 |
+
[29]: ad: 0x7ffff71083f3, op: 826
|
| 145 |
+
[29]: ad: 0x7ffff71083f7, op: 427
|
| 146 |
+
[29]: ad: 0x7ffff71083fe, op: 427
|
| 147 |
+
[29]: ad: 0x7ffff7108402, op: 427
|
| 148 |
+
[29]: ad: 0x7ffff7108405, op: 847
|
| 149 |
+
[29]: ad: 0x7ffff7108407, op: 325
|
| 150 |
+
new bb detected: 30
|
| 151 |
+
[30]: ad: 0x7ffff7108409, op: 427
|
| 152 |
+
[30]: ad: 0x7ffff7108410, op: 109
|
| 153 |
+
[30]: ad: 0x7ffff7108415, op: 330
|
| 154 |
+
new bb detected: 31
|
| 155 |
+
[31]: ad: 0x7ffff710841b, op: 388
|
| 156 |
+
[31]: ad: 0x7ffff7108422, op: 847
|
| 157 |
+
[31]: ad: 0x7ffff7108424, op: 330
|
| 158 |
+
new bb detected: 32
|
| 159 |
+
[32]: ad: 0x7ffff710844c, op: 1723
|
| 160 |
+
[32]: ad: 0x7ffff710844e, op: 75
|
| 161 |
+
new bb detected: 33
|
| 162 |
+
[33]: ad: 0x7ffff71056a0, op: 671
|
| 163 |
+
[33]: ad: 0x7ffff71056a2, op: 671
|
| 164 |
+
[33]: ad: 0x7ffff71056a4, op: 671
|
| 165 |
+
[33]: ad: 0x7ffff71056a6, op: 427
|
| 166 |
+
[33]: ad: 0x7ffff71056a9, op: 671
|
| 167 |
+
[33]: ad: 0x7ffff71056ab, op: 671
|
| 168 |
+
[33]: ad: 0x7ffff71056ac, op: 671
|
| 169 |
+
[33]: ad: 0x7ffff71056ad, op: 826
|
| 170 |
+
[33]: ad: 0x7ffff71056b1, op: 427
|
| 171 |
+
[33]: ad: 0x7ffff71056b5, op: 427
|
| 172 |
+
[33]: ad: 0x7ffff71056be, op: 427
|
| 173 |
+
[33]: ad: 0x7ffff71056c3, op: 1723
|
| 174 |
+
[33]: ad: 0x7ffff71056c5, op: 427
|
| 175 |
+
[33]: ad: 0x7ffff71056c8, op: 31
|
| 176 |
+
[33]: ad: 0x7ffff71056cc, op: 427
|
| 177 |
+
[33]: ad: 0x7ffff71056cf, op: 480
|
| 178 |
+
[33]: ad: 0x7ffff71056d2, op: 109
|
| 179 |
+
[33]: ad: 0x7ffff71056d5, op: 319
|
| 180 |
+
new bb detected: 34
|
| 181 |
+
[34]: ad: 0x7ffff71056db, op: 427
|
| 182 |
+
[34]: ad: 0x7ffff71056de, op: 847
|
| 183 |
+
[34]: ad: 0x7ffff71056e2, op: 325
|
| 184 |
+
new bb detected: 35
|
| 185 |
+
[35]: ad: 0x7ffff71056e8, op: 109
|
| 186 |
+
[35]: ad: 0x7ffff71056ec, op: 311
|
| 187 |
+
new bb detected: 36
|
| 188 |
+
[36]: ad: 0x7ffff71056f2, op: 31
|
| 189 |
+
[36]: ad: 0x7ffff71056f5, op: 325
|
| 190 |
+
new bb detected: 37
|
| 191 |
+
[37]: ad: 0x7ffff71056fb, op: 427
|
| 192 |
+
[37]: ad: 0x7ffff7105702, op: 427
|
| 193 |
+
[37]: ad: 0x7ffff7105705, op: 427
|
| 194 |
+
[37]: ad: 0x7ffff7105709, op: 847
|
| 195 |
+
[37]: ad: 0x7ffff710570c, op: 330
|
| 196 |
+
new bb detected: 38
|
| 197 |
+
[38]: ad: 0x7ffff710570e, op: 388
|
| 198 |
+
[38]: ad: 0x7ffff7105712, op: 799
|
| 199 |
+
[38]: ad: 0x7ffff7105716, op: 109
|
| 200 |
+
[38]: ad: 0x7ffff710571d, op: 311
|
| 201 |
+
new bb detected: 39
|
| 202 |
+
[39]: ad: 0x7ffff710571f, op: 427
|
| 203 |
+
[39]: ad: 0x7ffff7105726, op: 427
|
| 204 |
+
[39]: ad: 0x7ffff710572d, op: 388
|
| 205 |
+
[39]: ad: 0x7ffff7105731, op: 109
|
| 206 |
+
[39]: ad: 0x7ffff7105735, op: 330
|
| 207 |
+
new bb detected: 40
|
| 208 |
+
[40]: ad: 0x7ffff710573b, op: 468
|
| 209 |
+
[40]: ad: 0x7ffff710573f, op: 427
|
| 210 |
+
[40]: ad: 0x7ffff7105742, op: 109
|
| 211 |
+
[40]: ad: 0x7ffff7105745, op: 310
|
| 212 |
+
new bb detected: 41
|
| 213 |
+
[41]: ad: 0x7ffff7105a00, op: 427
|
| 214 |
+
[41]: ad: 0x7ffff7105a07, op: 8
|
| 215 |
+
[41]: ad: 0x7ffff7105a0a, op: 427
|
| 216 |
+
[41]: ad: 0x7ffff7105a0e, op: 427
|
| 217 |
+
[41]: ad: 0x7ffff7105a11, op: 799
|
| 218 |
+
[41]: ad: 0x7ffff7105a15, op: 1723
|
| 219 |
+
[41]: ad: 0x7ffff7105a1d, op: 427
|
| 220 |
+
[41]: ad: 0x7ffff7105a21, op: 427
|
| 221 |
+
[41]: ad: 0x7ffff7105a29, op: 427
|
| 222 |
+
[41]: ad: 0x7ffff7105a2d, op: 316
|
| 223 |
+
new bb detected: 42
|
| 224 |
+
[42]: ad: 0x7ffff71057e8, op: 427
|
| 225 |
+
[42]: ad: 0x7ffff71057ed, op: 826
|
| 226 |
+
[42]: ad: 0x7ffff71057f6, op: 325
|
| 227 |
+
new bb detected: 43
|
| 228 |
+
[43]: ad: 0x7ffff71057fc, op: 8
|
| 229 |
+
[43]: ad: 0x7ffff7105800, op: 616
|
| 230 |
+
[43]: ad: 0x7ffff7105801, op: 616
|
| 231 |
+
[43]: ad: 0x7ffff7105802, op: 616
|
| 232 |
+
[43]: ad: 0x7ffff7105804, op: 616
|
| 233 |
+
[43]: ad: 0x7ffff7105806, op: 616
|
| 234 |
+
[43]: ad: 0x7ffff7105808, op: 616
|
| 235 |
+
[43]: ad: 0x7ffff710580a, op: 740
|
| 236 |
+
new bb detected: 44
|
| 237 |
+
[44]: ad: 0x7ffff7108453, op: 427
|
| 238 |
+
[44]: ad: 0x7ffff7108456, op: 8
|
| 239 |
+
[44]: ad: 0x7ffff710845a, op: 616
|
| 240 |
+
[44]: ad: 0x7ffff710845b, op: 616
|
| 241 |
+
[44]: ad: 0x7ffff710845c, op: 740
|
| 242 |
+
new bb detected: 45
|
| 243 |
+
[45]: ad: 0x7ffff3d8e825, op: 316
|
| 244 |
+
new bb detected: 46
|
| 245 |
+
[46]: ad: 0x7ffff3d8e7f2, op: 436
|
| 246 |
+
[46]: ad: 0x7ffff3d8e7f7, op: 427
|
| 247 |
+
[46]: ad: 0x7ffff3d8e7fb, op: 467
|
| 248 |
+
[46]: ad: 0x7ffff3d8e7ff, op: 8
|
| 249 |
+
[46]: ad: 0x7ffff3d8e803, op: 616
|
| 250 |
+
[46]: ad: 0x7ffff3d8e804, op: 616
|
| 251 |
+
[46]: ad: 0x7ffff3d8e805, op: 616
|
| 252 |
+
[46]: ad: 0x7ffff3d8e807, op: 616
|
| 253 |
+
[46]: ad: 0x7ffff3d8e809, op: 616
|
| 254 |
+
[46]: ad: 0x7ffff3d8e80b, op: 616
|
| 255 |
+
[46]: ad: 0x7ffff3d8e80d, op: 740
|
| 256 |
+
new bb detected: 47
|
| 257 |
+
[47]: ad: 0x7ffff3d8e390, op: 427
|
| 258 |
+
[47]: ad: 0x7ffff3d8e394, op: 8
|
| 259 |
+
[47]: ad: 0x7ffff3d8e397, op: 316
|
| 260 |
+
new bb detected: 48
|
| 261 |
+
[48]: ad: 0x7ffff3d8e351, op: 427
|
| 262 |
+
[48]: ad: 0x7ffff3d8e355, op: 427
|
| 263 |
+
[48]: ad: 0x7ffff3d8e358, op: 826
|
| 264 |
+
[48]: ad: 0x7ffff3d8e35c, op: 427
|
| 265 |
+
[48]: ad: 0x7ffff3d8e35e, op: 427
|
| 266 |
+
[48]: ad: 0x7ffff3d8e362, op: 427
|
| 267 |
+
[48]: ad: 0x7ffff3d8e367, op: 826
|
| 268 |
+
[48]: ad: 0x7ffff3d8e370, op: 325
|
| 269 |
+
new bb detected: 49
|
| 270 |
+
[49]: ad: 0x7ffff3d8e372, op: 8
|
| 271 |
+
[49]: ad: 0x7ffff3d8e376, op: 616
|
| 272 |
+
[49]: ad: 0x7ffff3d8e377, op: 616
|
| 273 |
+
[49]: ad: 0x7ffff3d8e378, op: 740
|
| 274 |
+
new bb detected: 50
|
| 275 |
+
[50]: ad: 0x7ffff3d8e46e, op: 427
|
| 276 |
+
[50]: ad: 0x7ffff3d8e471, op: 427
|
| 277 |
+
[50]: ad: 0x7ffff3d8e476, op: 427
|
| 278 |
+
[50]: ad: 0x7ffff3d8e47b, op: 75
|
| 279 |
+
new bb detected: 51
|
| 280 |
+
[51]: ad: 0x7ffff3d8e480, op: 427
|
| 281 |
+
[51]: ad: 0x7ffff3d8e485, op: 427
|
| 282 |
+
[51]: ad: 0x7ffff3d8e489, op: 427
|
| 283 |
+
[51]: ad: 0x7ffff3d8e48c, op: 75
|
| 284 |
+
new bb detected: 52
|
| 285 |
+
[52]: ad: 0x7ffff3d8d1e0, op: 482
|
| 286 |
+
[52]: ad: 0x7ffff3d8d1e4, op: 316
|
| 287 |
+
new bb detected: 53
|
| 288 |
+
[53]: ad: 0x7ffff734bd80, op: 482
|
| 289 |
+
[53]: ad: 0x7ffff734bd84, op: 427
|
| 290 |
+
[53]: ad: 0x7ffff734bd88, op: 454
|
| 291 |
+
[53]: ad: 0x7ffff734bd8d, op: 454
|
| 292 |
+
[53]: ad: 0x7ffff734bd92, op: 669
|
| 293 |
+
[53]: ad: 0x7ffff734bd96, op: 467
|
| 294 |
+
[53]: ad: 0x7ffff734bd99, op: 427
|
| 295 |
+
[53]: ad: 0x7ffff734bd9c, op: 427
|
| 296 |
+
[53]: ad: 0x7ffff734bda0, op: 740
|
| 297 |
+
new bb detected: 54
|
| 298 |
+
[54]: ad: 0x7ffff3d8e491, op: 427
|
| 299 |
+
[54]: ad: 0x7ffff3d8e495, op: 8
|
| 300 |
+
[54]: ad: 0x7ffff3d8e49a, op: 109
|
| 301 |
+
[54]: ad: 0x7ffff3d8e49d, op: 325
|
| 302 |
+
new bb detected: 55
|
| 303 |
+
[55]: ad: 0x7ffff3d8e421, op: 427
|
| 304 |
+
[55]: ad: 0x7ffff3d8e427, op: 427
|
| 305 |
+
[55]: ad: 0x7ffff3d8e42e, op: 465
|
| 306 |
+
[55]: ad: 0x7ffff3d8e431, op: 427
|
| 307 |
+
[55]: ad: 0x7ffff3d8e435, op: 427
|
| 308 |
+
[55]: ad: 0x7ffff3d8e438, op: 8
|
| 309 |
+
[55]: ad: 0x7ffff3d8e43b, op: 109
|
| 310 |
+
[55]: ad: 0x7ffff3d8e43d, op: 320
|
| 311 |
+
new bb detected: 56
|
| 312 |
+
[56]: ad: 0x7ffff3d8e418, op: 8
|
| 313 |
+
[56]: ad: 0x7ffff3d8e41c, op: 109
|
| 314 |
+
[56]: ad: 0x7ffff3d8e41f, op: 330
|
| 315 |
+
new bb detected: 57
|
| 316 |
+
[57]: ad: 0x7ffff3d8e49f, op: 8
|
| 317 |
+
[57]: ad: 0x7ffff3d8e4a3, op: 616
|
| 318 |
+
[57]: ad: 0x7ffff3d8e4a4, op: 616
|
| 319 |
+
[57]: ad: 0x7ffff3d8e4a5, op: 616
|
| 320 |
+
[57]: ad: 0x7ffff3d8e4a7, op: 616
|
| 321 |
+
[57]: ad: 0x7ffff3d8e4a9, op: 616
|
| 322 |
+
[57]: ad: 0x7ffff3d8e4ab, op: 616
|
| 323 |
+
[57]: ad: 0x7ffff3d8e4ad, op: 740
|
| 324 |
+
new bb detected: 58
|
| 325 |
+
[58]: ad: 0x7ffff3d8e596, op: 847
|
| 326 |
+
[58]: ad: 0x7ffff3d8e599, op: 330
|
| 327 |
+
new bb detected: 59
|
| 328 |
+
[59]: ad: 0x7ffff3d8e59b, op: 427
|
| 329 |
+
[59]: ad: 0x7ffff3d8e5a0, op: 847
|
| 330 |
+
[59]: ad: 0x7ffff3d8e5a3, op: 330
|
| 331 |
+
new bb detected: 60
|
| 332 |
+
[60]: ad: 0x7ffff3d8e5a5, op: 75
|
| 333 |
+
new bb detected: 61
|
| 334 |
+
[61]: ad: 0x7ffff3d8e5aa, op: 427
|
| 335 |
+
[61]: ad: 0x7ffff3d8e5ae, op: 847
|
| 336 |
+
[61]: ad: 0x7ffff3d8e5b1, op: 330
|
| 337 |
+
new bb detected: 62
|
| 338 |
+
[62]: ad: 0x7ffff3d8e5b3, op: 75
|
| 339 |
+
new bb detected: 63
|
| 340 |
+
[63]: ad: 0x7ffff3d8e5b8, op: 427
|
| 341 |
+
[63]: ad: 0x7ffff3d8e5bb, op: 75
|
| 342 |
+
new bb detected: 64
|
| 343 |
+
[64]: ad: 0x7ffff3d8e5c0, op: 427
|
| 344 |
+
[64]: ad: 0x7ffff3d8e5c3, op: 109
|
| 345 |
+
[64]: ad: 0x7ffff3d8e5c6, op: 325
|
| 346 |
+
new bb detected: 65
|
| 347 |
+
[65]: ad: 0x7ffff3d8e569, op: 427
|
| 348 |
+
[65]: ad: 0x7ffff3d8e56d, op: 826
|
| 349 |
+
[65]: ad: 0x7ffff3d8e572, op: 427
|
| 350 |
+
[65]: ad: 0x7ffff3d8e575, op: 75
|
| 351 |
+
new bb detected: 66
|
| 352 |
+
[66]: ad: 0x7ffff3d8d300, op: 482
|
| 353 |
+
[66]: ad: 0x7ffff3d8d304, op: 316
|
| 354 |
+
new bb detected: 67
|
| 355 |
+
[67]: ad: 0x7ffff734bdb0, op: 482
|
| 356 |
+
[67]: ad: 0x7ffff734bdb4, op: 427
|
| 357 |
+
[67]: ad: 0x7ffff734bdb7, op: 427
|
| 358 |
+
[67]: ad: 0x7ffff734bdbb, op: 427
|
| 359 |
+
[67]: ad: 0x7ffff734bdbe, op: 427
|
| 360 |
+
[67]: ad: 0x7ffff734bdc2, op: 740
|
| 361 |
+
new bb detected: 68
|
| 362 |
+
[68]: ad: 0x7ffff3d8e57a, op: 427
|
| 363 |
+
[68]: ad: 0x7ffff3d8e57d, op: 75
|
| 364 |
+
new bb detected: 69
|
| 365 |
+
[69]: ad: 0x7ffff3d8e582, op: 427
|
| 366 |
+
[69]: ad: 0x7ffff3d8e585, op: 427
|
| 367 |
+
[69]: ad: 0x7ffff3d8e588, op: 427
|
| 368 |
+
[69]: ad: 0x7ffff3d8e58b, op: 427
|
| 369 |
+
[69]: ad: 0x7ffff3d8e58e, op: 427
|
| 370 |
+
[69]: ad: 0x7ffff3d8e591, op: 75
|
| 371 |
+
new bb detected: 70
|
| 372 |
+
[70]: ad: 0x7ffff3d8e3c0, op: 482
|
| 373 |
+
[70]: ad: 0x7ffff3d8e3c4, op: 671
|
| 374 |
+
[70]: ad: 0x7ffff3d8e3c6, op: 671
|
| 375 |
+
[70]: ad: 0x7ffff3d8e3c8, op: 671
|
| 376 |
+
[70]: ad: 0x7ffff3d8e3ca, op: 671
|
| 377 |
+
[70]: ad: 0x7ffff3d8e3cc, op: 671
|
| 378 |
+
[70]: ad: 0x7ffff3d8e3cd, op: 427
|
| 379 |
+
[70]: ad: 0x7ffff3d8e3d0, op: 671
|
| 380 |
+
[70]: ad: 0x7ffff3d8e3d1, op: 826
|
| 381 |
+
[70]: ad: 0x7ffff3d8e3d5, op: 427
|
| 382 |
+
[70]: ad: 0x7ffff3d8e3d9, op: 427
|
| 383 |
+
[70]: ad: 0x7ffff3d8e3dd, op: 465
|
| 384 |
+
[70]: ad: 0x7ffff3d8e3e1, op: 109
|
| 385 |
+
[70]: ad: 0x7ffff3d8e3e5, op: 330
|
| 386 |
+
new bb detected: 71
|
| 387 |
+
[71]: ad: 0x7ffff3d8e3eb, op: 427
|
| 388 |
+
[71]: ad: 0x7ffff3d8e3f1, op: 109
|
| 389 |
+
[71]: ad: 0x7ffff3d8e3f4, op: 315
|
| 390 |
+
new bb detected: 72
|
| 391 |
+
[72]: ad: 0x7ffff3d8e3fa, op: 427
|
| 392 |
+
[72]: ad: 0x7ffff3d8e3fd, op: 427
|
| 393 |
+
[72]: ad: 0x7ffff3d8e401, op: 427
|
| 394 |
+
[72]: ad: 0x7ffff3d8e405, op: 109
|
| 395 |
+
[72]: ad: 0x7ffff3d8e408, op: 330
|
| 396 |
+
new bb detected: 73
|
| 397 |
+
[73]: ad: 0x7ffff3d8e40e, op: 796
|
| 398 |
+
[73]: ad: 0x7ffff3d8e412, op: 316
|
| 399 |
+
new bb detected: 74
|
| 400 |
+
[74]: ad: 0x7ffff3d8e427, op: 427
|
| 401 |
+
[74]: ad: 0x7ffff3d8e42e, op: 465
|
| 402 |
+
[74]: ad: 0x7ffff3d8e431, op: 427
|
| 403 |
+
[74]: ad: 0x7ffff3d8e435, op: 427
|
| 404 |
+
[74]: ad: 0x7ffff3d8e438, op: 8
|
| 405 |
+
[74]: ad: 0x7ffff3d8e43b, op: 109
|
| 406 |
+
[74]: ad: 0x7ffff3d8e43d, op: 320
|
| 407 |
+
new bb detected: 75
|
| 408 |
+
[75]: ad: 0x7ffff3d8e43f, op: 427
|
| 409 |
+
[75]: ad: 0x7ffff3d8e444, op: 75
|
| 410 |
+
new bb detected: 76
|
| 411 |
+
[76]: ad: 0x7ffff3d8e449, op: 427
|
| 412 |
+
[76]: ad: 0x7ffff3d8e44c, op: 427
|
| 413 |
+
[76]: ad: 0x7ffff3d8e44f, op: 427
|
| 414 |
+
[76]: ad: 0x7ffff3d8e452, op: 75
|
| 415 |
+
new bb detected: 77
|
| 416 |
+
[77]: ad: 0x7ffff3d8de30, op: 482
|
| 417 |
+
[77]: ad: 0x7ffff3d8de34, op: 671
|
| 418 |
+
[77]: ad: 0x7ffff3d8de36, op: 678
|
| 419 |
+
[77]: ad: 0x7ffff3d8de3a, op: 671
|
| 420 |
+
[77]: ad: 0x7ffff3d8de3b, op: 427
|
| 421 |
+
[77]: ad: 0x7ffff3d8de3e, op: 671
|
| 422 |
+
[77]: ad: 0x7ffff3d8de3f, op: 427
|
| 423 |
+
[77]: ad: 0x7ffff3d8de43, op: 427
|
| 424 |
+
[77]: ad: 0x7ffff3d8de46, op: 826
|
| 425 |
+
[77]: ad: 0x7ffff3d8de49, op: 427
|
| 426 |
+
[77]: ad: 0x7ffff3d8de51, op: 467
|
| 427 |
+
[77]: ad: 0x7ffff3d8de54, op: 330
|
| 428 |
+
new bb detected: 78
|
| 429 |
+
[78]: ad: 0x7ffff3d8de5a, op: 427
|
| 430 |
+
[78]: ad: 0x7ffff3d8de64, op: 427
|
| 431 |
+
[78]: ad: 0x7ffff3d8de67, op: 109
|
| 432 |
+
[78]: ad: 0x7ffff3d8de6a, op: 319
|
| 433 |
+
new bb detected: 79
|
| 434 |
+
[79]: ad: 0x7ffff3d8de70, op: 427
|
| 435 |
+
[79]: ad: 0x7ffff3d8de73, op: 75
|
| 436 |
+
new bb detected: 80
|
| 437 |
+
[80]: ad: 0x7ffff3d8de78, op: 427
|
| 438 |
+
[80]: ad: 0x7ffff3d8de7b, op: 454
|
| 439 |
+
[80]: ad: 0x7ffff3d8de80, op: 8
|
| 440 |
+
[80]: ad: 0x7ffff3d8de83, op: 669
|
| 441 |
+
[80]: ad: 0x7ffff3d8de87, op: 427
|
| 442 |
+
[80]: ad: 0x7ffff3d8de8b, op: 467
|
| 443 |
+
[80]: ad: 0x7ffff3d8de8e, op: 427
|
| 444 |
+
[80]: ad: 0x7ffff3d8de92, op: 427
|
| 445 |
+
[80]: ad: 0x7ffff3d8de96, op: 427
|
| 446 |
+
[80]: ad: 0x7ffff3d8de99, op: 826
|
| 447 |
+
[80]: ad: 0x7ffff3d8de9c, op: 109
|
| 448 |
+
[80]: ad: 0x7ffff3d8de9f, op: 330
|
| 449 |
+
new bb detected: 81
|
| 450 |
+
[81]: ad: 0x7ffff3d8dea1, op: 427
|
| 451 |
+
[81]: ad: 0x7ffff3d8dea4, op: 427
|
| 452 |
+
[81]: ad: 0x7ffff3d8dea7, op: 75
|
| 453 |
+
new bb detected: 82
|
| 454 |
+
[82]: ad: 0x7ffff720394d, op: 109
|
| 455 |
+
[82]: ad: 0x7ffff7203954, op: 319
|
| 456 |
+
new bb detected: 83
|
| 457 |
+
[83]: ad: 0x7ffff7203956, op: 1232
|
| 458 |
+
[83]: ad: 0x7ffff720395b, op: 109
|
| 459 |
+
[83]: ad: 0x7ffff7203962, op: 311
|
| 460 |
+
new bb detected: 84
|
| 461 |
+
[84]: ad: 0x7ffff7203911, op: 1232
|
| 462 |
+
[84]: ad: 0x7ffff7203917, op: 1232
|
| 463 |
+
[84]: ad: 0x7ffff720391d, op: 1232
|
| 464 |
+
[84]: ad: 0x7ffff7203921, op: 1232
|
| 465 |
+
[84]: ad: 0x7ffff7203926, op: 1232
|
| 466 |
+
[84]: ad: 0x7ffff720392c, op: 1232
|
| 467 |
+
[84]: ad: 0x7ffff7203932, op: 1704
|
| 468 |
+
[84]: ad: 0x7ffff7203935, op: 740
|
| 469 |
+
new bb detected: 85
|
| 470 |
+
[85]: ad: 0x7ffff3d8deac, op: 427
|
| 471 |
+
[85]: ad: 0x7ffff3d8deaf, op: 8
|
| 472 |
+
[85]: ad: 0x7ffff3d8deb2, op: 678
|
| 473 |
+
[85]: ad: 0x7ffff3d8deb6, op: 427
|
| 474 |
+
[85]: ad: 0x7ffff3d8deba, op: 427
|
| 475 |
+
[85]: ad: 0x7ffff3d8debe, op: 826
|
| 476 |
+
[85]: ad: 0x7ffff3d8dec2, op: 427
|
| 477 |
+
[85]: ad: 0x7ffff3d8deca, op: 467
|
| 478 |
+
[85]: ad: 0x7ffff3d8dece, op: 330
|
| 479 |
+
new bb detected: 86
|
| 480 |
+
[86]: ad: 0x7ffff3d8ded4, op: 427
|
| 481 |
+
[86]: ad: 0x7ffff3d8dede, op: 427
|
| 482 |
+
[86]: ad: 0x7ffff3d8dee1, op: 109
|
| 483 |
+
[86]: ad: 0x7ffff3d8dee4, op: 319
|
| 484 |
+
new bb detected: 87
|
| 485 |
+
[87]: ad: 0x7ffff3d8deea, op: 427
|
| 486 |
+
[87]: ad: 0x7ffff3d8deed, op: 75
|
| 487 |
+
new bb detected: 88
|
| 488 |
+
[88]: ad: 0x7ffff3d8def2, op: 427
|
| 489 |
+
[88]: ad: 0x7ffff3d8def5, op: 454
|
| 490 |
+
[88]: ad: 0x7ffff3d8defa, op: 8
|
| 491 |
+
[88]: ad: 0x7ffff3d8defd, op: 669
|
| 492 |
+
[88]: ad: 0x7ffff3d8df01, op: 427
|
| 493 |
+
[88]: ad: 0x7ffff3d8df05, op: 467
|
| 494 |
+
[88]: ad: 0x7ffff3d8df09, op: 427
|
| 495 |
+
[88]: ad: 0x7ffff3d8df0d, op: 427
|
| 496 |
+
[88]: ad: 0x7ffff3d8df11, op: 427
|
| 497 |
+
[88]: ad: 0x7ffff3d8df14, op: 826
|
| 498 |
+
[88]: ad: 0x7ffff3d8df17, op: 109
|
| 499 |
+
[88]: ad: 0x7ffff3d8df1a, op: 330
|
| 500 |
+
new bb detected: 89
|
| 501 |
+
[89]: ad: 0x7ffff3d8df1c, op: 427
|
| 502 |
+
[89]: ad: 0x7ffff3d8df1f, op: 427
|
| 503 |
+
[89]: ad: 0x7ffff3d8df22, op: 75
|
| 504 |
+
new bb detected: 90
|
| 505 |
+
[90]: ad: 0x7ffff72038b0, op: 109
|
| 506 |
+
[90]: ad: 0x7ffff72038b3, op: 318
|
| 507 |
+
new bb detected: 91
|
| 508 |
+
[91]: ad: 0x7ffff72038e2, op: 1232
|
| 509 |
+
[91]: ad: 0x7ffff72038e6, op: 1232
|
| 510 |
+
[91]: ad: 0x7ffff72038ec, op: 1232
|
| 511 |
+
[91]: ad: 0x7ffff72038f0, op: 1232
|
| 512 |
+
[91]: ad: 0x7ffff72038f6, op: 740
|
| 513 |
+
new bb detected: 92
|
| 514 |
+
[92]: ad: 0x7ffff3d8df27, op: 427
|
| 515 |
+
[92]: ad: 0x7ffff3d8df2a, op: 427
|
| 516 |
+
[92]: ad: 0x7ffff3d8df2e, op: 8
|
| 517 |
+
[92]: ad: 0x7ffff3d8df31, op: 427
|
| 518 |
+
[92]: ad: 0x7ffff3d8df35, op: 427
|
| 519 |
+
[92]: ad: 0x7ffff3d8df39, op: 616
|
| 520 |
+
[92]: ad: 0x7ffff3d8df3a, op: 616
|
| 521 |
+
[92]: ad: 0x7ffff3d8df3b, op: 616
|
| 522 |
+
[92]: ad: 0x7ffff3d8df3d, op: 740
|
| 523 |
+
new bb detected: 93
|
| 524 |
+
[93]: ad: 0x7ffff3d8e457, op: 427
|
| 525 |
+
[93]: ad: 0x7ffff3d8e45a, op: 826
|
| 526 |
+
[93]: ad: 0x7ffff3d8e45e, op: 427
|
| 527 |
+
[93]: ad: 0x7ffff3d8e461, op: 8
|
| 528 |
+
[93]: ad: 0x7ffff3d8e465, op: 756
|
| 529 |
+
[93]: ad: 0x7ffff3d8e469, op: 75
|
| 530 |
+
new bb detected: 94
|
| 531 |
+
[94]: ad: 0x7ffff3d8e2d0, op: 482
|
| 532 |
+
[94]: ad: 0x7ffff3d8e2d4, op: 671
|
| 533 |
+
[94]: ad: 0x7ffff3d8e2d5, op: 671
|
| 534 |
+
[94]: ad: 0x7ffff3d8e2d6, op: 826
|
| 535 |
+
[94]: ad: 0x7ffff3d8e2da, op: 427
|
| 536 |
+
[94]: ad: 0x7ffff3d8e2dd, op: 427
|
| 537 |
+
[94]: ad: 0x7ffff3d8e2e6, op: 427
|
| 538 |
+
[94]: ad: 0x7ffff3d8e2eb, op: 1723
|
| 539 |
+
[94]: ad: 0x7ffff3d8e2ed, op: 847
|
| 540 |
+
[94]: ad: 0x7ffff3d8e2ef, op: 315
|
| 541 |
+
new bb detected: 95
|
| 542 |
+
[95]: ad: 0x7ffff3d8e2f5, op: 427
|
| 543 |
+
[95]: ad: 0x7ffff3d8e2f9, op: 465
|
| 544 |
+
[95]: ad: 0x7ffff3d8e2fc, op: 427
|
| 545 |
+
[95]: ad: 0x7ffff3d8e2ff, op: 8
|
| 546 |
+
[95]: ad: 0x7ffff3d8e302, op: 388
|
| 547 |
+
[95]: ad: 0x7ffff3d8e30a, op: 427
|
| 548 |
+
[95]: ad: 0x7ffff3d8e30e, op: 427
|
| 549 |
+
[95]: ad: 0x7ffff3d8e315, op: 431
|
| 550 |
+
[95]: ad: 0x7ffff3d8e319, op: 465
|
| 551 |
+
[95]: ad: 0x7ffff3d8e31d, op: 8
|
| 552 |
+
[95]: ad: 0x7ffff3d8e320, op: 465
|
| 553 |
+
[95]: ad: 0x7ffff3d8e323, op: 427
|
| 554 |
+
[95]: ad: 0x7ffff3d8e327, op: 427
|
| 555 |
+
[95]: ad: 0x7ffff3d8e32a, op: 8
|
| 556 |
+
[95]: ad: 0x7ffff3d8e32e, op: 427
|
| 557 |
+
[95]: ad: 0x7ffff3d8e333, op: 431
|
| 558 |
+
[95]: ad: 0x7ffff3d8e337, op: 668
|
| 559 |
+
[95]: ad: 0x7ffff3d8e33b, op: 454
|
| 560 |
+
[95]: ad: 0x7ffff3d8e340, op: 109
|
| 561 |
+
[95]: ad: 0x7ffff3d8e344, op: 330
|
| 562 |
+
new bb detected: 96
|
| 563 |
+
[96]: ad: 0x7ffff3d8e380, op: 427
|
| 564 |
+
[96]: ad: 0x7ffff3d8e383, op: 388
|
| 565 |
+
[96]: ad: 0x7ffff3d8e388, op: 427
|
| 566 |
+
[96]: ad: 0x7ffff3d8e38b, op: 75
|
| 567 |
+
new bb detected: 97
|
| 568 |
+
[97]: ad: 0x7ffff3d8e750, op: 482
|
| 569 |
+
[97]: ad: 0x7ffff3d8e754, op: 671
|
| 570 |
+
[97]: ad: 0x7ffff3d8e756, op: 427
|
| 571 |
+
[97]: ad: 0x7ffff3d8e759, op: 427
|
| 572 |
+
[97]: ad: 0x7ffff3d8e763, op: 671
|
| 573 |
+
[97]: ad: 0x7ffff3d8e765, op: 671
|
| 574 |
+
[97]: ad: 0x7ffff3d8e767, op: 671
|
| 575 |
+
[97]: ad: 0x7ffff3d8e769, op: 671
|
| 576 |
+
[97]: ad: 0x7ffff3d8e76a, op: 671
|
| 577 |
+
[97]: ad: 0x7ffff3d8e76b, op: 826
|
| 578 |
+
[97]: ad: 0x7ffff3d8e76f, op: 427
|
| 579 |
+
[97]: ad: 0x7ffff3d8e773, op: 427
|
| 580 |
+
[97]: ad: 0x7ffff3d8e776, op: 427
|
| 581 |
+
[97]: ad: 0x7ffff3d8e779, op: 826
|
| 582 |
+
[97]: ad: 0x7ffff3d8e77c, op: 756
|
| 583 |
+
[97]: ad: 0x7ffff3d8e780, op: 109
|
| 584 |
+
[97]: ad: 0x7ffff3d8e783, op: 330
|
| 585 |
+
new bb detected: 98
|
| 586 |
+
[98]: ad: 0x7ffff3d8e789, op: 847
|
| 587 |
+
[98]: ad: 0x7ffff3d8e78c, op: 427
|
| 588 |
+
[98]: ad: 0x7ffff3d8e791, op: 427
|
| 589 |
+
[98]: ad: 0x7ffff3d8e794, op: 427
|
| 590 |
+
[98]: ad: 0x7ffff3d8e797, op: 104
|
| 591 |
+
[98]: ad: 0x7ffff3d8e79b, op: 1723
|
| 592 |
+
[98]: ad: 0x7ffff3d8e79d, op: 8
|
| 593 |
+
[98]: ad: 0x7ffff3d8e7a0, op: 427
|
| 594 |
+
[98]: ad: 0x7ffff3d8e7a3, op: 770
|
| 595 |
+
[98]: ad: 0x7ffff3d8e7a6, op: 826
|
| 596 |
+
[98]: ad: 0x7ffff3d8e7a9, op: 847
|
| 597 |
+
[98]: ad: 0x7ffff3d8e7ac, op: 325
|
| 598 |
+
new bb detected: 99
|
| 599 |
+
[99]: ad: 0x7ffff3d8e7b2, op: 847
|
| 600 |
+
[99]: ad: 0x7ffff3d8e7b5, op: 325
|
| 601 |
+
new bb detected: 100
|
| 602 |
+
[100]: ad: 0x7ffff710574b, op: 109
|
| 603 |
+
[100]: ad: 0x7ffff7105752, op: 319
|
| 604 |
+
new bb detected: 101
|
| 605 |
+
[101]: ad: 0x7ffff7105758, op: 388
|
| 606 |
+
[101]: ad: 0x7ffff710575d, op: 427
|
| 607 |
+
[101]: ad: 0x7ffff7105761, op: 109
|
| 608 |
+
[101]: ad: 0x7ffff7105765, op: 311
|
| 609 |
+
new bb detected: 102
|
| 610 |
+
[102]: ad: 0x7ffff710576b, op: 31
|
| 611 |
+
[102]: ad: 0x7ffff710576f, op: 109
|
| 612 |
+
[102]: ad: 0x7ffff7105777, op: 318
|
| 613 |
+
new bb detected: 103
|
| 614 |
+
[103]: ad: 0x7ffff710577d, op: 427
|
| 615 |
+
[103]: ad: 0x7ffff7105783, op: 847
|
| 616 |
+
[103]: ad: 0x7ffff7105785, op: 325
|
| 617 |
+
new bb detected: 104
|
| 618 |
+
[104]: ad: 0x7ffff710578b, op: 427
|
| 619 |
+
[104]: ad: 0x7ffff7105794, op: 799
|
| 620 |
+
[104]: ad: 0x7ffff7105797, op: 388
|
| 621 |
+
[104]: ad: 0x7ffff710579a, op: 8
|
| 622 |
+
[104]: ad: 0x7ffff710579e, op: 427
|
| 623 |
+
[104]: ad: 0x7ffff71057a2, op: 427
|
| 624 |
+
[104]: ad: 0x7ffff71057aa, op: 847
|
| 625 |
+
[104]: ad: 0x7ffff71057ac, op: 325
|
| 626 |
+
new bb detected: 105
|
| 627 |
+
[105]: ad: 0x7ffff71057b2, op: 109
|
| 628 |
+
[105]: ad: 0x7ffff71057b5, op: 330
|
| 629 |
+
new bb detected: 106
|
| 630 |
+
[106]: ad: 0x7ffff71057bb, op: 388
|
| 631 |
+
[106]: ad: 0x7ffff71057bf, op: 799
|
| 632 |
+
[106]: ad: 0x7ffff71057c3, op: 1723
|
| 633 |
+
[106]: ad: 0x7ffff71057c6, op: 427
|
| 634 |
+
[106]: ad: 0x7ffff71057ca, op: 427
|
| 635 |
+
[106]: ad: 0x7ffff71057ce, op: 847
|
| 636 |
+
[106]: ad: 0x7ffff71057d1, op: 330
|
| 637 |
+
new bb detected: 107
|
| 638 |
+
[107]: ad: 0x7ffff71057d3, op: 31
|
| 639 |
+
[107]: ad: 0x7ffff71057d7, op: 330
|
| 640 |
+
new bb detected: 108
|
| 641 |
+
[108]: ad: 0x7ffff71080f7, op: 427
|
| 642 |
+
[108]: ad: 0x7ffff71080ff, op: 847
|
| 643 |
+
[108]: ad: 0x7ffff7108101, op: 330
|
| 644 |
+
new bb detected: 109
|
| 645 |
+
[109]: ad: 0x7ffff7108250, op: 388
|
| 646 |
+
[109]: ad: 0x7ffff7108257, op: 427
|
| 647 |
+
[109]: ad: 0x7ffff710825a, op: 427
|
| 648 |
+
[109]: ad: 0x7ffff710825d, op: 75
|
| 649 |
+
new bb detected: 110
|
| 650 |
+
[110]: ad: 0x7ffff71069b0, op: 847
|
| 651 |
+
[110]: ad: 0x7ffff71069b3, op: 329
|
| 652 |
+
new bb detected: 111
|
| 653 |
+
[111]: ad: 0x7ffff71069b9, op: 671
|
| 654 |
+
[111]: ad: 0x7ffff71069bb, op: 388
|
| 655 |
+
[111]: ad: 0x7ffff71069bf, op: 671
|
| 656 |
+
[111]: ad: 0x7ffff71069c1, op: 671
|
| 657 |
+
[111]: ad: 0x7ffff71069c3, op: 671
|
| 658 |
+
[111]: ad: 0x7ffff71069c5, op: 671
|
| 659 |
+
[111]: ad: 0x7ffff71069c6, op: 427
|
| 660 |
+
[111]: ad: 0x7ffff71069c9, op: 671
|
| 661 |
+
[111]: ad: 0x7ffff71069ca, op: 427
|
| 662 |
+
[111]: ad: 0x7ffff71069cd, op: 826
|
| 663 |
+
[111]: ad: 0x7ffff71069d4, op: 109
|
| 664 |
+
[111]: ad: 0x7ffff71069d8, op: 319
|
| 665 |
+
new bb detected: 112
|
| 666 |
+
[112]: ad: 0x7ffff7106af8, op: 31
|
| 667 |
+
[112]: ad: 0x7ffff7106afc, op: 427
|
| 668 |
+
[112]: ad: 0x7ffff7106aff, op: 847
|
| 669 |
+
[112]: ad: 0x7ffff7106b02, op: 330
|
| 670 |
+
new bb detected: 113
|
| 671 |
+
[113]: ad: 0x7ffff7106b08, op: 427
|
| 672 |
+
[113]: ad: 0x7ffff7106b0b, op: 799
|
| 673 |
+
[113]: ad: 0x7ffff7106b0f, op: 109
|
| 674 |
+
[113]: ad: 0x7ffff7106b16, op: 311
|
| 675 |
+
new bb detected: 114
|
| 676 |
+
[114]: ad: 0x7ffff7106d60, op: 388
|
| 677 |
+
[114]: ad: 0x7ffff7106d64, op: 388
|
| 678 |
+
[114]: ad: 0x7ffff7106d68, op: 388
|
| 679 |
+
[114]: ad: 0x7ffff7106d70, op: 427
|
| 680 |
+
[114]: ad: 0x7ffff7106d74, op: 847
|
| 681 |
+
[114]: ad: 0x7ffff7106d77, op: 325
|
| 682 |
+
new bb detected: 115
|
| 683 |
+
[115]: ad: 0x7ffff7106c04, op: 847
|
| 684 |
+
[115]: ad: 0x7ffff7106c07, op: 325
|
| 685 |
+
new bb detected: 116
|
| 686 |
+
[116]: ad: 0x7ffff7106c0d, op: 8
|
| 687 |
+
[116]: ad: 0x7ffff7106c10, op: 427
|
| 688 |
+
[116]: ad: 0x7ffff7106c18, op: 427
|
| 689 |
+
[116]: ad: 0x7ffff7106c1c, op: 847
|
| 690 |
+
[116]: ad: 0x7ffff7106c1e, op: 325
|
| 691 |
+
new bb detected: 117
|
| 692 |
+
[117]: ad: 0x7ffff7106c24, op: 388
|
| 693 |
+
[117]: ad: 0x7ffff7106c28, op: 427
|
| 694 |
+
[117]: ad: 0x7ffff7106c2b, op: 799
|
| 695 |
+
[117]: ad: 0x7ffff7106c2f, op: 1723
|
| 696 |
+
[117]: ad: 0x7ffff7106c32, op: 427
|
| 697 |
+
[117]: ad: 0x7ffff7106c36, op: 427
|
| 698 |
+
[117]: ad: 0x7ffff7106c3a, op: 799
|
| 699 |
+
[117]: ad: 0x7ffff7106c3d, op: 109
|
| 700 |
+
[117]: ad: 0x7ffff7106c40, op: 325
|
| 701 |
+
new bb detected: 118
|
| 702 |
+
[118]: ad: 0x7ffff7106c46, op: 427
|
| 703 |
+
[118]: ad: 0x7ffff7106c4d, op: 388
|
| 704 |
+
[118]: ad: 0x7ffff7106c51, op: 799
|
| 705 |
+
[118]: ad: 0x7ffff7106c55, op: 427
|
| 706 |
+
[118]: ad: 0x7ffff7106c5a, op: 847
|
| 707 |
+
[118]: ad: 0x7ffff7106c5d, op: 330
|
| 708 |
+
new bb detected: 119
|
| 709 |
+
[119]: ad: 0x7ffff7106c63, op: 109
|
| 710 |
+
[119]: ad: 0x7ffff7106c6a, op: 311
|
| 711 |
+
new bb detected: 120
|
| 712 |
+
[120]: ad: 0x7ffff7106c70, op: 468
|
| 713 |
+
[120]: ad: 0x7ffff7106c75, op: 109
|
| 714 |
+
[120]: ad: 0x7ffff7106c7c, op: 388
|
| 715 |
+
[120]: ad: 0x7ffff7106c80, op: 310
|
| 716 |
+
new bb detected: 121
|
| 717 |
+
[121]: ad: 0x7ffff7106cdb, op: 427
|
| 718 |
+
[121]: ad: 0x7ffff7106cdf, op: 847
|
| 719 |
+
[121]: ad: 0x7ffff7106ce2, op: 330
|
| 720 |
+
new bb detected: 122
|
| 721 |
+
[122]: ad: 0x7ffff7106ce8, op: 847
|
| 722 |
+
[122]: ad: 0x7ffff7106ceb, op: 325
|
| 723 |
+
new bb detected: 123
|
| 724 |
+
[123]: ad: 0x7ffff7106cf1, op: 427
|
| 725 |
+
[123]: ad: 0x7ffff7106cf9, op: 427
|
| 726 |
+
[123]: ad: 0x7ffff7106cfd, op: 847
|
| 727 |
+
[123]: ad: 0x7ffff7106cff, op: 330
|
| 728 |
+
new bb detected: 124
|
| 729 |
+
[124]: ad: 0x7ffff7106c90, op: 388
|
| 730 |
+
[124]: ad: 0x7ffff7106c94, op: 427
|
| 731 |
+
[124]: ad: 0x7ffff7106c97, op: 799
|
| 732 |
+
[124]: ad: 0x7ffff7106c9b, op: 1723
|
| 733 |
+
[124]: ad: 0x7ffff7106c9e, op: 427
|
| 734 |
+
[124]: ad: 0x7ffff7106ca2, op: 427
|
| 735 |
+
[124]: ad: 0x7ffff7106ca9, op: 427
|
| 736 |
+
[124]: ad: 0x7ffff7106cad, op: 427
|
| 737 |
+
[124]: ad: 0x7ffff7106cb2, op: 468
|
| 738 |
+
[124]: ad: 0x7ffff7106cb7, op: 1723
|
| 739 |
+
[124]: ad: 0x7ffff7106cbb, op: 427
|
| 740 |
+
[124]: ad: 0x7ffff7106cbf, op: 8
|
| 741 |
+
[124]: ad: 0x7ffff7106cc2, op: 427
|
| 742 |
+
[124]: ad: 0x7ffff7106cc6, op: 427
|
| 743 |
+
[124]: ad: 0x7ffff7106ccb, op: 468
|
| 744 |
+
[124]: ad: 0x7ffff7106cce, op: 109
|
| 745 |
+
[124]: ad: 0x7ffff7106cd5, op: 318
|
| 746 |
+
new bb detected: 125
|
| 747 |
+
[125]: ad: 0x7ffff710706c, op: 427
|
| 748 |
+
[125]: ad: 0x7ffff7107072, op: 847
|
| 749 |
+
[125]: ad: 0x7ffff7107074, op: 325
|
| 750 |
+
new bb detected: 126
|
| 751 |
+
[126]: ad: 0x7ffff7107076, op: 8
|
| 752 |
+
[126]: ad: 0x7ffff710707d, op: 427
|
| 753 |
+
[126]: ad: 0x7ffff7107080, op: 616
|
| 754 |
+
[126]: ad: 0x7ffff7107081, op: 616
|
| 755 |
+
[126]: ad: 0x7ffff7107082, op: 616
|
| 756 |
+
[126]: ad: 0x7ffff7107084, op: 616
|
| 757 |
+
[126]: ad: 0x7ffff7107086, op: 616
|
| 758 |
+
[126]: ad: 0x7ffff7107088, op: 616
|
| 759 |
+
[126]: ad: 0x7ffff710708a, op: 740
|
| 760 |
+
new bb detected: 127
|
| 761 |
+
[127]: ad: 0x7ffff7108262, op: 847
|
| 762 |
+
[127]: ad: 0x7ffff7108265, op: 330
|
| 763 |
+
new bb detected: 128
|
| 764 |
+
[128]: ad: 0x7ffff710826b, op: 427
|
| 765 |
+
[128]: ad: 0x7ffff710826f, op: 847
|
| 766 |
+
[128]: ad: 0x7ffff7108272, op: 325
|
| 767 |
+
new bb detected: 129
|
| 768 |
+
[129]: ad: 0x7ffff7108278, op: 31
|
| 769 |
+
[129]: ad: 0x7ffff710827b, op: 330
|
| 770 |
+
new bb detected: 130
|
| 771 |
+
[130]: ad: 0x7ffff71081a2, op: 8
|
| 772 |
+
[130]: ad: 0x7ffff71081a6, op: 616
|
| 773 |
+
[130]: ad: 0x7ffff71081a7, op: 616
|
| 774 |
+
[130]: ad: 0x7ffff71081a8, op: 616
|
| 775 |
+
[130]: ad: 0x7ffff71081aa, op: 740
|
| 776 |
+
new bb detected: 131
|
| 777 |
+
[131]: ad: 0x7ffff72038b5, op: 109
|
| 778 |
+
[131]: ad: 0x7ffff72038b8, op: 318
|
| 779 |
+
new bb detected: 132
|
| 780 |
+
[132]: ad: 0x7ffff7203900, op: 427
|
| 781 |
+
[132]: ad: 0x7ffff7203905, op: 427
|
| 782 |
+
[132]: ad: 0x7ffff7203908, op: 427
|
| 783 |
+
[132]: ad: 0x7ffff720390b, op: 427
|
| 784 |
+
[132]: ad: 0x7ffff7203910, op: 740
|
| 785 |
+
new bb detected: 133
|
| 786 |
+
Scarab gitrev: 7185dea
|
| 787 |
+
Warning: Scarab expects the trace file type to include OFFLINE_FILE_TYPE_ARCH_REGDEPS (0x20000), but got type: 0xe40
|
| 788 |
+
Scarab started at Fri Jul 17 21:08:30 2026
|
| 789 |
+
|
| 790 |
+
read from initialization: 0x7ffff3d8e870
|
| 791 |
+
advanceReader: ROI end reached (ordinal 10000002 > roi_end 10000000)
|
| 792 |
+
Reached end of trace (last_inst) pc=0x7ffff3d8e3f4
|
| 793 |
+
[72]: ad: 0x7ffff3d8e3eb, op: 427
|
| 794 |
+
[72]: ad: 0x7ffff3d8e3f1, op: 109
|
| 795 |
+
DUP bb detected at trace end
|
| 796 |
+
to be appened segment num 1
|
| 797 |
+
10000000
|
| 798 |
+
10000000
|
| 799 |
+
====================================
|
| 800 |
+
TRACE_INST_TAKEN_NOT_CF:0
|
| 801 |
+
TRACE_INST_TAKEN_CF_BR:160663
|
| 802 |
+
TRACE_INST_TAKEN_CF_CBR:281378
|
| 803 |
+
TRACE_INST_TAKEN_CF_REP:0
|
| 804 |
+
TRACE_INST_TAKEN_CF_CALL:239068
|
| 805 |
+
TRACE_INST_TAKEN_CF_IBR:205680
|
| 806 |
+
TRACE_INST_TAKEN_CF_ICALL:0
|
| 807 |
+
TRACE_INST_TAKEN_CF_ICO:0
|
| 808 |
+
TRACE_INST_TAKEN_CF_RET:239070
|
| 809 |
+
TRACE_INST_TAKEN_CF_SYS:0
|
| 810 |
+
====================================
|
| 811 |
+
identity within this segment
|
| 812 |
+
2 bbs with same first pc
|
| 813 |
+
[72]: size 3, freq 8231
|
| 814 |
+
7ffff3d8e3eb: 427, 0
|
| 815 |
+
7ffff3d8e3f1: 109, 0
|
| 816 |
+
7ffff3d8e3f4: 315, 0
|
| 817 |
+
[72]: size 2, freq 1
|
| 818 |
+
7ffff3d8e3eb: 427, 0
|
| 819 |
+
7ffff3d8e3f1: 109, 0
|
| 820 |
+
1 / 133
|
| 821 |
+
========================================================
|
| 822 |
+
Number of blocks built : 133
|
| 823 |
+
Average size : 4.90 instructions
|
| 824 |
+
Number of blocks executed : 2114252
|
| 825 |
+
Average weighted size : 4.73 instructions
|
| 826 |
+
Number of total instructions : 10000000
|
| 827 |
+
Number of fetched instruction : 10000000
|
| 828 |
+
========================================================
|
| 829 |
+
Scarab finished at Fri Jul 17 21:08:35 2026
|
| 830 |
+
|
tsp/fingerprint/run_1/PARAMS.in
ADDED
|
@@ -0,0 +1,268 @@
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# File : PARAMS.golden_cove
|
| 2 |
+
# Date : 02/27/25
|
| 3 |
+
# Description : Golden Cove Configuration
|
| 4 |
+
# Author : Surim Oh <[email protected]>
|
| 5 |
+
#
|
| 6 |
+
# Based on documentation found here:
|
| 7 |
+
# https://en.wikipedia.org/wiki/Golden_Cove
|
| 8 |
+
# https://en.wikichip.org/wiki/intel/microarchitectures/golden_cove
|
| 9 |
+
# https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/3
|
| 10 |
+
|
| 11 |
+
## Simulation Parameters
|
| 12 |
+
--mode full
|
| 13 |
+
--model cmp
|
| 14 |
+
--sim_limit none
|
| 15 |
+
|
| 16 |
+
## Core Parameters
|
| 17 |
+
|
| 18 |
+
# Femptoseconds, 3.2GHz, used for energy estimates.
|
| 19 |
+
--chip_cycle_time 312500
|
| 20 |
+
|
| 21 |
+
|
| 22 |
+
### Fetch Stage
|
| 23 |
+
--fetch_off_path_ops 1
|
| 24 |
+
|
| 25 |
+
#### ICache
|
| 26 |
+
--icache_size 32768
|
| 27 |
+
--icache_assoc 8
|
| 28 |
+
--icache_line_size 64
|
| 29 |
+
|
| 30 |
+
### Uop Cache
|
| 31 |
+
# inclusive w/ L1i
|
| 32 |
+
--uop_cache_enable 1
|
| 33 |
+
--uop_cache_width 8
|
| 34 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 35 |
+
--uop_cache_assoc 8
|
| 36 |
+
--iprf_on_uop_cache_hit 1
|
| 37 |
+
|
| 38 |
+
### Branch Predictor
|
| 39 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 40 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 41 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 42 |
+
--bp_mech tage64k
|
| 43 |
+
|
| 44 |
+
|
| 45 |
+
#### BTB
|
| 46 |
+
|
| 47 |
+
# TODO
|
| 48 |
+
# multi-level BTB
|
| 49 |
+
# 128 entry L0 BTB
|
| 50 |
+
# 6144 entry L1 BTB
|
| 51 |
+
# 12888 entry L2 BTB
|
| 52 |
+
# ~2 entry Return Stack
|
| 53 |
+
# roughly 2x8192 for now
|
| 54 |
+
# BTB model to use.
|
| 55 |
+
--btb_mech generic
|
| 56 |
+
--btb_entries 12288
|
| 57 |
+
--btb_assoc 4
|
| 58 |
+
--btb_main_latency 3
|
| 59 |
+
--btb_l0_present 1
|
| 60 |
+
--btb_l0_entries 128
|
| 61 |
+
--btb_l0_assoc 4
|
| 62 |
+
--btb_l0_latency 1
|
| 63 |
+
--btb_l1_present 1
|
| 64 |
+
--btb_l1_entries 6144
|
| 65 |
+
--btb_l1_assoc 4
|
| 66 |
+
--btb_l1_latency 2
|
| 67 |
+
|
| 68 |
+
# Allow the BTB to be updated by off path ops.
|
| 69 |
+
--btb_off_path_writes 1
|
| 70 |
+
|
| 71 |
+
# NT branches are not inserted in BTB, but do not trigger resteer
|
| 72 |
+
# since we continue without a control flow change
|
| 73 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 74 |
+
|
| 75 |
+
#### CRS
|
| 76 |
+
|
| 77 |
+
# Enable return stack
|
| 78 |
+
--enable_crs 1
|
| 79 |
+
--crs_entries 128
|
| 80 |
+
--crs_realistic 1
|
| 81 |
+
|
| 82 |
+
### iBP
|
| 83 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 84 |
+
--ibtb_mech tc_tagged
|
| 85 |
+
# iBTB Model. tc_tagless, tc_tagged, tc_hybrid.
|
| 86 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 87 |
+
--tc_entries 4096
|
| 88 |
+
--tc_assoc 4
|
| 89 |
+
|
| 90 |
+
### Decode Stage
|
| 91 |
+
--decode_width 6
|
| 92 |
+
--decode_cycles 5
|
| 93 |
+
|
| 94 |
+
### Instruction Decode Queue
|
| 95 |
+
--idq_size 144
|
| 96 |
+
|
| 97 |
+
### Map Stage
|
| 98 |
+
--map_cycles 5
|
| 99 |
+
|
| 100 |
+
# register renaming table
|
| 101 |
+
--reg_renaming_scheme 1
|
| 102 |
+
--reg_table_integer_physical_size 280
|
| 103 |
+
--reg_table_vector_physical_size 332
|
| 104 |
+
|
| 105 |
+
### Issue Stage
|
| 106 |
+
|
| 107 |
+
# Max number of instructions to be renamed, and issued per cycle.
|
| 108 |
+
--issue_width 6
|
| 109 |
+
|
| 110 |
+
--rs_fill_width 0
|
| 111 |
+
# rs_sizes ~205 in total, and they are split into three different reservation stations (RS1, RS2, RS3) where each has 97, 70, 38 entries respectively
|
| 112 |
+
# original architecture
|
| 113 |
+
# RS1 connected to port 0,1,5,6,10
|
| 114 |
+
# RS2 connected to port 2,3,11
|
| 115 |
+
# RS3 connected to port 7,8,4,9
|
| 116 |
+
# scarab does not split ST AGU port and ST port, merge them
|
| 117 |
+
# adjusted architecture to scarab ST AGU (port 4 and 9 removed. rs_size reduced to 186 from 205)
|
| 118 |
+
# RS1 connected to port 0,1,4,5,8
|
| 119 |
+
# RS2 connected to port 2,3,9
|
| 120 |
+
# RS3 connected to port 6,7 (port 4,9 removed, entries reduced to 19 from 38)
|
| 121 |
+
--rs_sizes 97 70 19
|
| 122 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 123 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 124 |
+
|
| 125 |
+
### Exec Stage
|
| 126 |
+
|
| 127 |
+
### DCache
|
| 128 |
+
--dcache_size 49152
|
| 129 |
+
--dcache_read_ports 1
|
| 130 |
+
--dcache_write_ports 1
|
| 131 |
+
--dcache_banks 8
|
| 132 |
+
--dcache_assoc 12
|
| 133 |
+
--dcache_line_size 64
|
| 134 |
+
--dcache_cycles 5
|
| 135 |
+
|
| 136 |
+
### Reorder/Retire Stage
|
| 137 |
+
|
| 138 |
+
# Max number of instructions to be retired per cycle.
|
| 139 |
+
--node_ret_width 8
|
| 140 |
+
--node_table_size 512
|
| 141 |
+
|
| 142 |
+
# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does
|
| 143 |
+
--stores_do_not_block_window 1
|
| 144 |
+
|
| 145 |
+
# TODO: confirm what this knob does
|
| 146 |
+
--prefs_do_not_block_window 1
|
| 147 |
+
|
| 148 |
+
|
| 149 |
+
## Uncore
|
| 150 |
+
|
| 151 |
+
### Mid-level cache
|
| 152 |
+
|
| 153 |
+
# Enable use of a midlevel cache between i/d and L1
|
| 154 |
+
# client 1.25 MiB (1310720 bytes) per core, 8-way, 15 cycles
|
| 155 |
+
# server 2 MiB (2097000 bytes) per core, 8-way, 16 cycles
|
| 156 |
+
--mlc_present 1
|
| 157 |
+
--mlc_size 2097000
|
| 158 |
+
--mlc_assoc 8
|
| 159 |
+
--mlc_cycles 16
|
| 160 |
+
|
| 161 |
+
|
| 162 |
+
### LLC
|
| 163 |
+
# 3 MiB per core, 16-way
|
| 164 |
+
--l1_size 3145728
|
| 165 |
+
--l1_banks 8
|
| 166 |
+
--l1_cycles 36 // just a guess
|
| 167 |
+
--l1_assoc 16
|
| 168 |
+
--l1_line_size 64
|
| 169 |
+
--l1_interleave_factor 64
|
| 170 |
+
|
| 171 |
+
|
| 172 |
+
### prefetcher
|
| 173 |
+
# Kept same as Kaby Lake
|
| 174 |
+
--pref_framework_on 1
|
| 175 |
+
--pref_stream_on 1
|
| 176 |
+
--pref_train_on_pref_misses 0
|
| 177 |
+
--pref_oracle_train 0
|
| 178 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 179 |
+
|
| 180 |
+
--stream_length 64
|
| 181 |
+
--stream_prefetch_n 4
|
| 182 |
+
--stream_start_dis 1
|
| 183 |
+
--stream_train_num 4
|
| 184 |
+
--stream_create_on_dc_miss 0
|
| 185 |
+
--stream_create_on_l1_miss 1
|
| 186 |
+
|
| 187 |
+
--pref_throttlefb_on=1
|
| 188 |
+
--pref_acc_thresh_1=0.75
|
| 189 |
+
--pref_acc_thresh_2=0.4
|
| 190 |
+
--pref_acc_thresh_3=0.4
|
| 191 |
+
--pref_timely_thresh=0.01
|
| 192 |
+
--pref_polpf_thresh=0.005
|
| 193 |
+
--pref_update_interval=8192
|
| 194 |
+
|
| 195 |
+
--mem_req_buffer_pref_watermark 4
|
| 196 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 197 |
+
|
| 198 |
+
### Memory
|
| 199 |
+
# Kept same as Kaby Lake
|
| 200 |
+
--addr_translation random
|
| 201 |
+
|
| 202 |
+
--mem_priority_ifetch 0
|
| 203 |
+
--mem_priority_dfetch 1
|
| 204 |
+
--mem_priority_dstore 2
|
| 205 |
+
--mem_priority_iprf 3
|
| 206 |
+
--mem_priority_dprf 4
|
| 207 |
+
--mem_priority_wb 5
|
| 208 |
+
--mem_priority_wb_nodirty 5
|
| 209 |
+
|
| 210 |
+
--mem_req_buffer_entries 32
|
| 211 |
+
--bus_width_in_bytes 8
|
| 212 |
+
|
| 213 |
+
--ramulator_standard DDR4
|
| 214 |
+
--ramulator_speed DDR4_2400R
|
| 215 |
+
--ramulator_org DDR4_8Gb_x8
|
| 216 |
+
--ramulator_channels 1
|
| 217 |
+
--ramulator_ranks 1
|
| 218 |
+
--ramulator_bankgroups 4
|
| 219 |
+
--ramulator_banks 4
|
| 220 |
+
--ramulator_chip_width 8
|
| 221 |
+
--ramulator_rows 65536
|
| 222 |
+
--ramulator_cols 1024
|
| 223 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 224 |
+
--ramulator_readq_entries 32
|
| 225 |
+
--ramulator_writeq_entries 32
|
| 226 |
+
--ramulator_record_cmd_trace FALSE
|
| 227 |
+
--ramulator_print_cmd_trace FALSE
|
| 228 |
+
--ramulator_tCK 833333
|
| 229 |
+
--ramulator_tCL 16
|
| 230 |
+
--ramulator_tCCD 6
|
| 231 |
+
--ramulator_tCCDS 4
|
| 232 |
+
--ramulator_tCCDL 6
|
| 233 |
+
--ramulator_tCWL 12
|
| 234 |
+
--ramulator_tBL 4
|
| 235 |
+
--ramulator_tWTR 9
|
| 236 |
+
--ramulator_tWTRS 3
|
| 237 |
+
--ramulator_tWTRL 9
|
| 238 |
+
--ramulator_tRP 16
|
| 239 |
+
--ramulator_tRPpb 16
|
| 240 |
+
--ramulator_tRPab 16
|
| 241 |
+
--ramulator_tRCD 16
|
| 242 |
+
--ramulator_tRCDR 16
|
| 243 |
+
--ramulator_tRCDW 16
|
| 244 |
+
--ramulator_tRAS 39
|
| 245 |
+
--dram_tech_in_nm 32
|
| 246 |
+
|
| 247 |
+
## Other
|
| 248 |
+
|
| 249 |
+
|
| 250 |
+
### Debug
|
| 251 |
+
--debug_inst_start 0
|
| 252 |
+
--debug_inst_stop -1
|
| 253 |
+
--debug_cycle_start 0
|
| 254 |
+
--debug_cycle_stop -1
|
| 255 |
+
|
| 256 |
+
|
| 257 |
+
## Stats and Params
|
| 258 |
+
--dump_params 1
|
| 259 |
+
--dump_stats 1
|
| 260 |
+
--dump_trace 0
|
| 261 |
+
|
| 262 |
+
####################################
|
| 263 |
+
--set_off_path_confirmed 1
|
| 264 |
+
|
| 265 |
+
--order_beyond_bus 1
|
| 266 |
+
|
| 267 |
+
--mem_ooo_stores 1
|
| 268 |
+
--mem_obey_store_dep 1
|
tsp/fingerprint/run_1/PARAMS.out
ADDED
|
@@ -0,0 +1,1102 @@
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|
|
|
|
|
| 1 |
+
--mode trace_bbv_distributed
|
| 2 |
+
--model cmp
|
| 3 |
+
--frontend memtrace
|
| 4 |
+
--sim_limit none
|
| 5 |
+
--memtrace_roi_begin 10000001
|
| 6 |
+
--memtrace_roi_end 20000000
|
| 7 |
+
--use_fetched_count 1
|
| 8 |
+
--dump_params 1
|
| 9 |
+
--dump_stats 1
|
| 10 |
+
--dump_trace 0
|
| 11 |
+
--trace_bbv_output /dev/shm/baseline/traces/tsp/fingerprint/pieces/segment.1
|
| 12 |
+
--trace_footprint_output /dev/shm/baseline/traces/tsp/fingerprint/footprint_pieces/segment.1
|
| 13 |
+
--segment_instr_count 10000000
|
| 14 |
+
--mlc_present 1
|
| 15 |
+
--mlc_size 2097000
|
| 16 |
+
--mlc_assoc 8
|
| 17 |
+
--mlc_cycles 16
|
| 18 |
+
--l1_size 3145728
|
| 19 |
+
--l1_assoc 16
|
| 20 |
+
--l1_line_size 64
|
| 21 |
+
--l1_cycles 36 // just a guess
|
| 22 |
+
--l1_banks 8
|
| 23 |
+
--l1_interleave_factor 64
|
| 24 |
+
--addr_translation random
|
| 25 |
+
--icache_size 32768
|
| 26 |
+
--icache_assoc 8
|
| 27 |
+
--icache_line_size 64
|
| 28 |
+
--uop_cache_enable 1
|
| 29 |
+
--uop_cache_width 8
|
| 30 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 31 |
+
--uop_cache_assoc 8
|
| 32 |
+
--iprf_on_uop_cache_hit 1
|
| 33 |
+
--dcache_size 49152
|
| 34 |
+
--dcache_assoc 12
|
| 35 |
+
--dcache_line_size 64
|
| 36 |
+
--dcache_cycles 5
|
| 37 |
+
--dcache_read_ports 1
|
| 38 |
+
--dcache_write_ports 1
|
| 39 |
+
--dcache_banks 8
|
| 40 |
+
--mem_ooo_stores 1
|
| 41 |
+
--mem_obey_store_dep 1
|
| 42 |
+
--mem_req_buffer_entries 32
|
| 43 |
+
--mem_priority_ifetch 0
|
| 44 |
+
--mem_priority_dfetch 1
|
| 45 |
+
--mem_priority_dstore 2
|
| 46 |
+
--mem_priority_iprf 3
|
| 47 |
+
--mem_priority_dprf 4
|
| 48 |
+
--mem_priority_wb 5
|
| 49 |
+
--mem_priority_wb_nodirty 5
|
| 50 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 51 |
+
--mem_req_buffer_pref_watermark 4
|
| 52 |
+
--order_beyond_bus 1
|
| 53 |
+
--set_off_path_confirmed 1
|
| 54 |
+
--ramulator_standard DDR4
|
| 55 |
+
--ramulator_speed DDR4_2400R
|
| 56 |
+
--ramulator_org DDR4_8Gb_x8
|
| 57 |
+
--ramulator_channels 1
|
| 58 |
+
--ramulator_ranks 1
|
| 59 |
+
--ramulator_bankgroups 4
|
| 60 |
+
--ramulator_banks 4
|
| 61 |
+
--ramulator_chip_width 8
|
| 62 |
+
--bus_width_in_bytes 8
|
| 63 |
+
--ramulator_rows 65536
|
| 64 |
+
--ramulator_cols 1024
|
| 65 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 66 |
+
--ramulator_readq_entries 32
|
| 67 |
+
--ramulator_writeq_entries 32
|
| 68 |
+
--ramulator_record_cmd_trace FALSE
|
| 69 |
+
--ramulator_print_cmd_trace FALSE
|
| 70 |
+
--ramulator_tCK 833333
|
| 71 |
+
--ramulator_tCL 16
|
| 72 |
+
--ramulator_tCCD 6
|
| 73 |
+
--ramulator_tCCDS 4
|
| 74 |
+
--ramulator_tCCDL 6
|
| 75 |
+
--ramulator_tCWL 12
|
| 76 |
+
--ramulator_tBL 4
|
| 77 |
+
--ramulator_tWTR 9
|
| 78 |
+
--ramulator_tWTRS 3
|
| 79 |
+
--ramulator_tWTRL 9
|
| 80 |
+
--ramulator_tRP 16
|
| 81 |
+
--ramulator_tRPpb 16
|
| 82 |
+
--ramulator_tRPab 16
|
| 83 |
+
--ramulator_tRCD 16
|
| 84 |
+
--ramulator_tRCDR 16
|
| 85 |
+
--ramulator_tRCDW 16
|
| 86 |
+
--ramulator_tRAS 39
|
| 87 |
+
--dram_tech_in_nm 32
|
| 88 |
+
--chip_cycle_time 312500
|
| 89 |
+
--issue_width 6
|
| 90 |
+
--rs_fill_width 0
|
| 91 |
+
--node_table_size 512
|
| 92 |
+
--node_ret_width 8
|
| 93 |
+
--decode_width 6
|
| 94 |
+
--idq_size 144
|
| 95 |
+
--reg_renaming_scheme 1
|
| 96 |
+
--reg_table_integer_physical_size 280
|
| 97 |
+
--reg_table_vector_physical_size 332
|
| 98 |
+
--rs_sizes 97 70 19
|
| 99 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 100 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 101 |
+
--decode_cycles 5
|
| 102 |
+
--map_cycles 5
|
| 103 |
+
--fetch_off_path_ops 1
|
| 104 |
+
--stores_do_not_block_window 1
|
| 105 |
+
--prefs_do_not_block_window 1
|
| 106 |
+
--cbp_trace_r0 /dev/shm/baseline/traces/.staging/tsp-164844/raw_trace/drmemtrace.tsp.164856.4389.dir/trace/drmemtrace.tsp.164856.1160.trace.zip
|
| 107 |
+
--debug_cycle_start 0
|
| 108 |
+
--debug_cycle_stop -1
|
| 109 |
+
--debug_inst_start 0
|
| 110 |
+
--debug_inst_stop -1
|
| 111 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 112 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 113 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 114 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 115 |
+
--bp_mech tage64k
|
| 116 |
+
--btb_mech generic
|
| 117 |
+
--btb_entries 12288
|
| 118 |
+
--btb_assoc 4
|
| 119 |
+
--btb_off_path_writes 1
|
| 120 |
+
--btb_main_latency 3
|
| 121 |
+
--btb_l0_present 1
|
| 122 |
+
--btb_l0_entries 128
|
| 123 |
+
--btb_l0_assoc 4
|
| 124 |
+
--btb_l0_latency 1
|
| 125 |
+
--btb_l1_present 1
|
| 126 |
+
--btb_l1_entries 6144
|
| 127 |
+
--btb_l1_assoc 4
|
| 128 |
+
--btb_l1_latency 2
|
| 129 |
+
--enable_crs 1
|
| 130 |
+
--crs_entries 128
|
| 131 |
+
--crs_realistic 1
|
| 132 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 133 |
+
--ibtb_mech tc_tagged
|
| 134 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 135 |
+
--tc_entries 4096
|
| 136 |
+
--tc_assoc 4
|
| 137 |
+
--pref_stream_on 1
|
| 138 |
+
--stream_prefetch_n 4
|
| 139 |
+
--stream_start_dis 1
|
| 140 |
+
--stream_length 64
|
| 141 |
+
--stream_train_num 4
|
| 142 |
+
--stream_create_on_dc_miss 0
|
| 143 |
+
--stream_create_on_l1_miss 1
|
| 144 |
+
--pref_framework_on 1
|
| 145 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 146 |
+
--pref_train_on_pref_misses 0
|
| 147 |
+
--pref_oracle_train_on 0
|
| 148 |
+
--pref_throttlefb_on 1
|
| 149 |
+
--pref_acc_thresh_1 0.75
|
| 150 |
+
--pref_acc_thresh_2 0.4
|
| 151 |
+
--pref_acc_thresh_3 0.4
|
| 152 |
+
--pref_update_interval 8192
|
| 153 |
+
--pref_timely_thresh 0.01
|
| 154 |
+
--pref_polpf_thresh 0.005
|
| 155 |
+
1 1 1 1 1 1 1
|
| 156 |
+
|
| 157 |
+
--- Cut out everything below to use this file as PARAMS.in ---
|
| 158 |
+
|
| 159 |
+
Parameter status at compile time and values supplied on the command line:
|
| 160 |
+
|
| 161 |
+
SIM_MODE 0 trace_bbv_distributed
|
| 162 |
+
SIM_MODEL 0 cmp
|
| 163 |
+
FRONTEND FE_PIN_EXEC_DRIVEN memtrace
|
| 164 |
+
INST_LIMIT NULL
|
| 165 |
+
SIM_LIMIT "none" none
|
| 166 |
+
FORWARD_PROGRESS_LIMIT 100000000
|
| 167 |
+
FORWARD_PROGRESS_INTERVAL 10000
|
| 168 |
+
FAST_FORWARD 0
|
| 169 |
+
FAST_FORWARD_TRACE_INS 0
|
| 170 |
+
FAST_FORWARD_UNTIL_ADDR 0
|
| 171 |
+
MEMTRACE_ROI_BEGIN 0 10000001
|
| 172 |
+
MEMTRACE_ROI_END 0 20000000
|
| 173 |
+
FULL_WARMUP 0
|
| 174 |
+
WARMUP 0
|
| 175 |
+
HEARTBEAT_INTERVAL 1000000
|
| 176 |
+
NUM_HEARTBEATS 0
|
| 177 |
+
USE_FETCHED_COUNT FALSE 1
|
| 178 |
+
PERIODIC_DUMP FALSE
|
| 179 |
+
FILE_TAG ""
|
| 180 |
+
OUTPUT_DIR "."
|
| 181 |
+
STATUS_FILE NULL
|
| 182 |
+
BINDIR NULL
|
| 183 |
+
DUMP_PARAMS TRUE 1
|
| 184 |
+
DUMP_STATS TRUE 1
|
| 185 |
+
DUMP_TRACE FALSE 0
|
| 186 |
+
CLEAR_STATS "never"
|
| 187 |
+
STATS_TO_TRACE NULL
|
| 188 |
+
STAT_TRACE_FILE "stats.trace"
|
| 189 |
+
STAT_TRACE_INTERVAL "i:100000"
|
| 190 |
+
PIPEVIEW FALSE
|
| 191 |
+
PIPEVIEW_FILE "pipeview"
|
| 192 |
+
MEMVIEW FALSE
|
| 193 |
+
MEMVIEW_FILE "memview.out"
|
| 194 |
+
MEMVIEW_START "never"
|
| 195 |
+
INST_HASH_TABLE_SIZE 524288 const
|
| 196 |
+
STDOUT_FILE NULL
|
| 197 |
+
STDERR_FILE NULL
|
| 198 |
+
PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp"
|
| 199 |
+
PRINT_PID FALSE
|
| 200 |
+
USE_UNSURE_FREE_LISTS FALSE
|
| 201 |
+
OPTIMIZER2_MAX_NUM_SLAVES 64
|
| 202 |
+
OPTIMIZER2_PERFECT_MEMORYLESS FALSE
|
| 203 |
+
EXIT_COND 0
|
| 204 |
+
NUM_NOPS 0
|
| 205 |
+
NOPS_BB_START 0x5000000
|
| 206 |
+
IGNORE_BAR_FETCH FALSE
|
| 207 |
+
TRACE_BBV_OUTPUT NULL /dev/shm/baseline/traces/tsp/fingerprint/pieces/segment.1
|
| 208 |
+
TRACE_FOOTPRINT_OUTPUT "" /dev/shm/baseline/traces/tsp/fingerprint/footprint_pieces/segment.1
|
| 209 |
+
SEGMENT_INSTR_COUNT 0 10000000
|
| 210 |
+
ENABLE_SWPRF FALSE
|
| 211 |
+
MLC_PRESENT FALSE 1
|
| 212 |
+
MLC_SIZE (512 * 1024) 2097000
|
| 213 |
+
MLC_ASSOC 4 8
|
| 214 |
+
MLC_LINE_SIZE 64
|
| 215 |
+
MLC_CYCLES 12 16
|
| 216 |
+
PERFECT_MLC FALSE
|
| 217 |
+
MLC_READ_PORTS 1
|
| 218 |
+
MLC_WRITE_PORTS 1
|
| 219 |
+
MLC_BANKS 8
|
| 220 |
+
MLC_INTERLEAVE_FACTOR 64
|
| 221 |
+
MLC_CACHE_REPL_POLICY 0
|
| 222 |
+
MLC_WRITE_THROUGH FALSE
|
| 223 |
+
PREFETCH_UPDATE_LRU_MLC TRUE
|
| 224 |
+
FORCE_L1_MISS FALSE
|
| 225 |
+
L1_SIZE (4 * 1024 * 1024) 3145728
|
| 226 |
+
L1_ASSOC 8 16
|
| 227 |
+
L1_LINE_SIZE 64 64
|
| 228 |
+
L1_CYCLES 24 36 // just a guess
|
| 229 |
+
PERFECT_L1 FALSE
|
| 230 |
+
PRIVATE_L1 FALSE
|
| 231 |
+
L1_READ_PORTS 1
|
| 232 |
+
L1_WRITE_PORTS 1
|
| 233 |
+
L1_BANKS 8 8
|
| 234 |
+
L1_INTERLEAVE_FACTOR 64 64
|
| 235 |
+
L1_CACHE_REPL_POLICY 0
|
| 236 |
+
L1_WRITE_THROUGH FALSE
|
| 237 |
+
L1_IGNORE_WB FALSE
|
| 238 |
+
L1_USE_CORE_FREQ FALSE
|
| 239 |
+
MARK_L1_MISSES TRUE
|
| 240 |
+
PREFETCH_UPDATE_LRU_L1 TRUE
|
| 241 |
+
MEMORY_RANDOM_ADDR FALSE
|
| 242 |
+
VA_PAGE_SIZE_BYTES 4096
|
| 243 |
+
NUM_ADDR_NON_SIGN_EXTEND_BITS 48
|
| 244 |
+
ADDR_TRANSLATION 0 random
|
| 245 |
+
CONSTANT_MEMORY_LATENCY FALSE
|
| 246 |
+
MEMORY_CYCLES 100
|
| 247 |
+
STALL_MEM_REQS_ONLY FALSE
|
| 248 |
+
ICACHE_SIZE (64 * 1024) 32768
|
| 249 |
+
ICACHE_ASSOC 4 8
|
| 250 |
+
ICACHE_LINE_SIZE 64 64
|
| 251 |
+
PERFECT_ICACHE FALSE
|
| 252 |
+
ICACHE_READ_PORTS 1
|
| 253 |
+
ICACHE_WRITE_PORTS 1
|
| 254 |
+
ICACHE_BANKS 8
|
| 255 |
+
ICACHE_REPL 0
|
| 256 |
+
UOP_CACHE_ENABLE 1 1
|
| 257 |
+
UOP_CACHE_WIDTH 6 8
|
| 258 |
+
ALWAYS_LOOKUP_ICACHE 0
|
| 259 |
+
UOP_CACHE_INSERT_ONLY_ONPATH FALSE
|
| 260 |
+
UOP_CACHE_READ_PORTS 1
|
| 261 |
+
UOP_CACHE_LINES 384 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 262 |
+
UOP_CACHE_ASSOC 8 8
|
| 263 |
+
UOP_CACHE_MAX_IMM_DISP_LINE 4
|
| 264 |
+
IPRF_ON_UOP_CACHE_HIT FALSE 1
|
| 265 |
+
UOP_CACHE_REPL 0
|
| 266 |
+
PRIORITY_LINE_STICKINESS_PERCENT 50
|
| 267 |
+
PW_PRIORITY_LIST_FILEPATH "pw_priority_list.csv"
|
| 268 |
+
NUM_PRIORITY_PWS 10
|
| 269 |
+
PRIORITIZE_PWS_AFTER_FIRST_STICKY_UNTIL_BACKEND_STALL FALSE
|
| 270 |
+
NO_REPL_AFTER_QUEUE_SIZE 0
|
| 271 |
+
FDIP_UC_SIZE 0
|
| 272 |
+
FDIP_UC_ASSOC 4
|
| 273 |
+
FDIP_UC_INSERT_REPLPOL 0
|
| 274 |
+
MAP_STAGE_CONSUME_FROM_ICACHE_AND_UOC_SAME_CYCLE TRUE
|
| 275 |
+
UOP_QUEUE_LENGTH 7
|
| 276 |
+
DCACHE_SIZE (64 * 1024) 49152
|
| 277 |
+
DCACHE_ASSOC 1 12
|
| 278 |
+
DCACHE_LINE_SIZE 64 64
|
| 279 |
+
DCACHE_CYCLES 2 5
|
| 280 |
+
PERFECT_DCACHE FALSE
|
| 281 |
+
DCACHE_READ_PORTS 8 1
|
| 282 |
+
DCACHE_WRITE_PORTS 1 1
|
| 283 |
+
DCACHE_BANKS 1 8
|
| 284 |
+
DCACHE_INTERLEAVE_FACTOR 4
|
| 285 |
+
DCACHE_REPL 0
|
| 286 |
+
DCACHE_REPL_PREF_THRESH 1
|
| 287 |
+
MEM_OOO_STORES TRUE 1
|
| 288 |
+
MEM_OBEY_STORE_DEP TRUE 1
|
| 289 |
+
PREF_INSERT_LRU FALSE
|
| 290 |
+
PREF_INSERT_MIDDLE FALSE
|
| 291 |
+
PREF_INSERT_LOWQTR FALSE
|
| 292 |
+
PREF_INSERT_DYNACC FALSE
|
| 293 |
+
MEM_REQ_BUFFER_ENTRIES 32 32
|
| 294 |
+
PRIVATE_MSHR_ON TRUE
|
| 295 |
+
MEM_PRIORITY_IFETCH 0 0
|
| 296 |
+
MEM_PRIORITY_DFETCH 0 1
|
| 297 |
+
MEM_PRIORITY_DSTORE 0 2
|
| 298 |
+
MEM_PRIORITY_IPRF 9 3
|
| 299 |
+
MEM_PRIORITY_UOCPRF 9
|
| 300 |
+
MEM_PRIORITY_FDIPPRFON 8
|
| 301 |
+
MEM_PRIORITY_FDIPPRFOFF 9
|
| 302 |
+
MEM_PRIORITY_DPRF 10 4
|
| 303 |
+
MEM_PRIORITY_WB 0 5
|
| 304 |
+
MEM_PRIORITY_WB_NODIRTY 0 5
|
| 305 |
+
PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1
|
| 306 |
+
MEM_REQ_BUFFER_PREF_WATERMARK 0 4
|
| 307 |
+
MEM_REQ_BUFFER_WB_VALVE 2
|
| 308 |
+
MEM_L1_FILL_QUEUE_ENTRIES 32
|
| 309 |
+
MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE
|
| 310 |
+
MEM_MEM_QUEUE_PARTITION_ENABLE FALSE
|
| 311 |
+
MEM_BUS_OUT_QUEUE_AS_FIFO TRUE
|
| 312 |
+
OLDEST_FIRST_TO_MEM_QUEUE TRUE
|
| 313 |
+
ROUND_ROBIN_TO_MEM_QUEUE FALSE
|
| 314 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE FALSE
|
| 315 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0
|
| 316 |
+
L1_CYCLE_TIME 312500
|
| 317 |
+
MLCQ_TO_L1Q_TRANSFER_LATENCY 1
|
| 318 |
+
L1Q_TO_FSB_TRANSFER_LATENCY 1
|
| 319 |
+
PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE
|
| 320 |
+
KICKOUT_PREFETCHES FALSE
|
| 321 |
+
KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE
|
| 322 |
+
KICKOUT_OLDEST_PREFETCH FALSE
|
| 323 |
+
KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE
|
| 324 |
+
ORDER_BEYOND_BUS FALSE 1
|
| 325 |
+
ALL_FIFO_QUEUES FALSE
|
| 326 |
+
QUEUE_MLC_SIZE 0
|
| 327 |
+
QUEUE_L1_SIZE 0
|
| 328 |
+
QUEUE_BUS_OUT_SIZE 0
|
| 329 |
+
QUEUE_CORE_FILL_SIZE 0
|
| 330 |
+
ALLOW_TYPE_MATCHES FALSE
|
| 331 |
+
STREAM_PREFETCH_ON FALSE
|
| 332 |
+
DC_PREF_CACHE_ENABLE FALSE
|
| 333 |
+
DC_PREF_CACHE_CYCLE 0
|
| 334 |
+
PREF_INSERT_DCACHE_IMM TRUE
|
| 335 |
+
DC_PREF_CACHE_SIZE (64 * 1024)
|
| 336 |
+
DC_PREF_CACHE_ASSOC 4
|
| 337 |
+
DC_PREF_ONLY_L1HIT FALSE
|
| 338 |
+
PREF_CACHE_USE_RDY_CYCLE FALSE
|
| 339 |
+
IC_PREF_CACHE_ENABLE FALSE
|
| 340 |
+
IC_PREF_CACHE_SIZE (64 * 1024)
|
| 341 |
+
IC_PREF_CACHE_ASSOC 4
|
| 342 |
+
L1_PREF_CACHE_ENABLE FALSE
|
| 343 |
+
L1_PREF_CACHE_SIZE (1024 * 1024)
|
| 344 |
+
L1_PREF_CACHE_ASSOC 8
|
| 345 |
+
SET_OFF_PATH_CONFIRMED FALSE 1
|
| 346 |
+
USE_CONFIRMED_OFF FALSE
|
| 347 |
+
PREFCACHE_MOVE_OFFPATH FALSE
|
| 348 |
+
CACHE_STAT_ENABLE FALSE
|
| 349 |
+
PREF_DCACHE_HIT_FILL_L1 TRUE
|
| 350 |
+
PREF_ICACHE_HIT_FILL_L1 TRUE
|
| 351 |
+
CRITICAL_ACCESS_PLOT_ENABLE FALSE
|
| 352 |
+
CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat"
|
| 353 |
+
ROUND_ROBIN_TO_L1 FALSE
|
| 354 |
+
PREF_I_TOGETHER FALSE
|
| 355 |
+
ONE_MORE_CACHE_LINE_ENABLE FALSE
|
| 356 |
+
L1_STATIC_PARTITION_ENABLE 0
|
| 357 |
+
L1_STATIC_PARTITION NULL
|
| 358 |
+
L1_DYNAMIC_PARTITION_ENABLE FALSE
|
| 359 |
+
L1_DYNAMIC_PARTITION_POLICY 0
|
| 360 |
+
PARTITION_UMON_DSS_PREF_ENABLE FALSE
|
| 361 |
+
L1_CACHE_HIT_POSITION_COLLECT FALSE
|
| 362 |
+
L1_PART_ON FALSE
|
| 363 |
+
L1_PART_TRIGGER "c:1000000"
|
| 364 |
+
L1_PART_START "t:0"
|
| 365 |
+
L1_PART_WARMUP FALSE
|
| 366 |
+
L1_PART_SHADOW_WARMUP FALSE
|
| 367 |
+
L1_PART_METRIC 0
|
| 368 |
+
L1_PART_SEARCH 0
|
| 369 |
+
L1_PART_USE_STALLING TRUE
|
| 370 |
+
L1_PART_FILL_DELAY 0
|
| 371 |
+
L1_SHADOW_TAGS_MODULO 1
|
| 372 |
+
HIER_MSHR_ON FALSE
|
| 373 |
+
PERF_PRED_ENABLE FALSE
|
| 374 |
+
PERF_PRED_MECH PERF_PRED_CP
|
| 375 |
+
PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY
|
| 376 |
+
PERF_PRED_COUNT_ALL FALSE
|
| 377 |
+
PERF_PRED_COUNT_INST_MISSES TRUE
|
| 378 |
+
PERF_PRED_COUNT_PREFETCHES FALSE
|
| 379 |
+
PERF_PRED_COUNT_OFFPATH_REQS FALSE
|
| 380 |
+
PERF_PRED_COUNT_BW_REQS TRUE
|
| 381 |
+
PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE
|
| 382 |
+
PERF_PRED_SLACK_PERIOD_SIZE 32
|
| 383 |
+
PERF_PRED_REQS_FINISH_AT_FILL FALSE
|
| 384 |
+
PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE
|
| 385 |
+
PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE
|
| 386 |
+
DUMB_MODEL_AVG_REQ_DISTANCE 100
|
| 387 |
+
DUMB_MODEL_RANDOMIZE_DISTANCE FALSE
|
| 388 |
+
DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL
|
| 389 |
+
DUMB_MODEL_AVG_ROW_HITS 1
|
| 390 |
+
DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL
|
| 391 |
+
DUMB_MODEL_MLP 1
|
| 392 |
+
DUMB_MODEL_MLP_PER_CORE NULL
|
| 393 |
+
RAMULATOR_STANDARD "DDR4" DDR4
|
| 394 |
+
RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R
|
| 395 |
+
RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8
|
| 396 |
+
RAMULATOR_CHANNELS 1 1
|
| 397 |
+
RAMULATOR_RANKS 1 1
|
| 398 |
+
RAMULATOR_BANKGROUPS 4 4
|
| 399 |
+
RAMULATOR_BANKS 4 4
|
| 400 |
+
RAMULATOR_CHIP_WIDTH 8 8
|
| 401 |
+
BUS_WIDTH_IN_BYTES 8 8
|
| 402 |
+
RAMULATOR_ROWS 65536 65536
|
| 403 |
+
RAMULATOR_COLS 1024 1024
|
| 404 |
+
RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap
|
| 405 |
+
RAMULATOR_READQ_ENTRIES 32 32
|
| 406 |
+
RAMULATOR_WRITEQ_ENTRIES 32 32
|
| 407 |
+
RAMULATOR_REC_CMD_TRACE "off" FALSE
|
| 408 |
+
RAMULATOR_PRINT_CMD_TRACE "off" FALSE
|
| 409 |
+
RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on"
|
| 410 |
+
RAMULATOR_TCK 833333 833333
|
| 411 |
+
RAMULATOR_TCL 16 16
|
| 412 |
+
RAMULATOR_TCCD 6 6
|
| 413 |
+
RAMULATOR_TCCDS 4 4
|
| 414 |
+
RAMULATOR_TCCDL 6 6
|
| 415 |
+
RAMULATOR_TCWL 12 12
|
| 416 |
+
RAMULATOR_TBL 4 4
|
| 417 |
+
RAMULATOR_TWTR 9 9
|
| 418 |
+
RAMULATOR_TWTRS 3 3
|
| 419 |
+
RAMULATOR_TWTRL 9 9
|
| 420 |
+
RAMULATOR_TRP 16 16
|
| 421 |
+
RAMULATOR_TRPpb 16 16
|
| 422 |
+
RAMULATOR_TRPab 16 16
|
| 423 |
+
RAMULATOR_TRCD 16 16
|
| 424 |
+
RAMULATOR_TRCDR 16 16
|
| 425 |
+
RAMULATOR_TRCDW 16 16
|
| 426 |
+
RAMULATOR_TRAS 39 39
|
| 427 |
+
DRAM_TECH_IN_NM 32 32
|
| 428 |
+
DVFS_ON FALSE
|
| 429 |
+
DVFS_METRIC DVFS_METRIC_NUM_ELEMS
|
| 430 |
+
DVFS_CONFIGS NULL
|
| 431 |
+
DVFS_CONFIG_FILE NULL
|
| 432 |
+
DVFS_START "t:0"
|
| 433 |
+
DVFS_PERIOD "t:312500000000"
|
| 434 |
+
DVFS_LOG TRUE
|
| 435 |
+
DVFS_INDIVIDUAL_CORES FALSE
|
| 436 |
+
DVFS_CHIP_LEVEL FALSE
|
| 437 |
+
DVFS_STATIC NULL
|
| 438 |
+
DVFS_FORCE_CONFIG NULL
|
| 439 |
+
DVFS_REPLAY_CONFIG_TRACE NULL
|
| 440 |
+
DVFS_USE_ORACLE FALSE
|
| 441 |
+
DVFS_USE_BW_SHARING FALSE
|
| 442 |
+
DVFS_USE_DRAM_SHARING FALSE
|
| 443 |
+
DVFS_USE_STALL_TIME FALSE
|
| 444 |
+
DVFS_DRAM_SHARING_SOLVER_BIN NULL
|
| 445 |
+
DVFS_DRAM_SHARING_SOLVER_STRICT TRUE
|
| 446 |
+
DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95
|
| 447 |
+
DVFS_BW_SHARING_MAX_REQS 28.0
|
| 448 |
+
DVFS_BW_SHARING_MAX_RW_COST 0.25
|
| 449 |
+
DVFS_BW_SHARING_NO_PREF_STALL TRUE
|
| 450 |
+
DVFS_BW_SHARING_CRIT_STATS TRUE
|
| 451 |
+
DVFS_COUNT_L1_ACCESS_STALL FALSE
|
| 452 |
+
NUM_CORES 1
|
| 453 |
+
CHIP_CYCLE_TIME 312500 312500
|
| 454 |
+
CORE_0_CYCLE_TIME 312500
|
| 455 |
+
CORE_1_CYCLE_TIME 312500
|
| 456 |
+
CORE_2_CYCLE_TIME 312500
|
| 457 |
+
CORE_3_CYCLE_TIME 312500
|
| 458 |
+
CORE_4_CYCLE_TIME 312500
|
| 459 |
+
CORE_5_CYCLE_TIME 312500
|
| 460 |
+
CORE_6_CYCLE_TIME 312500
|
| 461 |
+
CORE_7_CYCLE_TIME 312500
|
| 462 |
+
CORE_8_CYCLE_TIME 312500
|
| 463 |
+
CORE_9_CYCLE_TIME 312500
|
| 464 |
+
CORE_10_CYCLE_TIME 312500
|
| 465 |
+
CORE_11_CYCLE_TIME 312500
|
| 466 |
+
CORE_12_CYCLE_TIME 312500
|
| 467 |
+
CORE_13_CYCLE_TIME 312500
|
| 468 |
+
CORE_14_CYCLE_TIME 312500
|
| 469 |
+
CORE_15_CYCLE_TIME 312500
|
| 470 |
+
CORE_16_CYCLE_TIME 312500
|
| 471 |
+
CORE_17_CYCLE_TIME 312500
|
| 472 |
+
CORE_18_CYCLE_TIME 312500
|
| 473 |
+
CORE_19_CYCLE_TIME 312500
|
| 474 |
+
CORE_20_CYCLE_TIME 312500
|
| 475 |
+
CORE_21_CYCLE_TIME 312500
|
| 476 |
+
CORE_22_CYCLE_TIME 312500
|
| 477 |
+
CORE_23_CYCLE_TIME 312500
|
| 478 |
+
CORE_24_CYCLE_TIME 312500
|
| 479 |
+
CORE_25_CYCLE_TIME 312500
|
| 480 |
+
CORE_26_CYCLE_TIME 312500
|
| 481 |
+
CORE_27_CYCLE_TIME 312500
|
| 482 |
+
CORE_28_CYCLE_TIME 312500
|
| 483 |
+
CORE_29_CYCLE_TIME 312500
|
| 484 |
+
CORE_30_CYCLE_TIME 312500
|
| 485 |
+
CORE_31_CYCLE_TIME 312500
|
| 486 |
+
CORE_32_CYCLE_TIME 312500
|
| 487 |
+
CORE_33_CYCLE_TIME 312500
|
| 488 |
+
CORE_34_CYCLE_TIME 312500
|
| 489 |
+
CORE_35_CYCLE_TIME 312500
|
| 490 |
+
CORE_36_CYCLE_TIME 312500
|
| 491 |
+
CORE_37_CYCLE_TIME 312500
|
| 492 |
+
CORE_38_CYCLE_TIME 312500
|
| 493 |
+
CORE_39_CYCLE_TIME 312500
|
| 494 |
+
CORE_40_CYCLE_TIME 312500
|
| 495 |
+
CORE_41_CYCLE_TIME 312500
|
| 496 |
+
CORE_42_CYCLE_TIME 312500
|
| 497 |
+
CORE_43_CYCLE_TIME 312500
|
| 498 |
+
CORE_44_CYCLE_TIME 312500
|
| 499 |
+
CORE_45_CYCLE_TIME 312500
|
| 500 |
+
CORE_46_CYCLE_TIME 312500
|
| 501 |
+
CORE_47_CYCLE_TIME 312500
|
| 502 |
+
CORE_48_CYCLE_TIME 312500
|
| 503 |
+
CORE_49_CYCLE_TIME 312500
|
| 504 |
+
CORE_50_CYCLE_TIME 312500
|
| 505 |
+
CORE_51_CYCLE_TIME 312500
|
| 506 |
+
CORE_52_CYCLE_TIME 312500
|
| 507 |
+
CORE_53_CYCLE_TIME 312500
|
| 508 |
+
CORE_54_CYCLE_TIME 312500
|
| 509 |
+
CORE_55_CYCLE_TIME 312500
|
| 510 |
+
CORE_56_CYCLE_TIME 312500
|
| 511 |
+
CORE_57_CYCLE_TIME 312500
|
| 512 |
+
CORE_58_CYCLE_TIME 312500
|
| 513 |
+
CORE_59_CYCLE_TIME 312500
|
| 514 |
+
CORE_60_CYCLE_TIME 312500
|
| 515 |
+
CORE_61_CYCLE_TIME 312500
|
| 516 |
+
CORE_62_CYCLE_TIME 312500
|
| 517 |
+
CORE_63_CYCLE_TIME 312500
|
| 518 |
+
TOPDOWN_FU_EXEC_FEW 0
|
| 519 |
+
ISSUE_WIDTH 4 6
|
| 520 |
+
RS_FILL_WIDTH 8 0
|
| 521 |
+
NODE_TABLE_SIZE 256 512
|
| 522 |
+
NODE_RET_WIDTH 4 8
|
| 523 |
+
NODE_RETIRE_RATE 10
|
| 524 |
+
DECODE_WIDTH 4 6
|
| 525 |
+
IDQ_SIZE 140 144
|
| 526 |
+
REG_RENAMING_SCHEME 0 1
|
| 527 |
+
REG_TABLE_INTEGER_PHYSICAL_SIZE 256 280
|
| 528 |
+
REG_TABLE_VECTOR_PHYSICAL_SIZE 256 332
|
| 529 |
+
REG_TABLE_INTEGER_VIRTUAL_SIZE 256
|
| 530 |
+
REG_TABLE_VECTOR_VIRTUAL_SIZE 256
|
| 531 |
+
REG_RENAMING_MOVE_ELIMINATE FALSE
|
| 532 |
+
NODE_ISSUE_QUEUE_DISPATCH_SCHEME 0
|
| 533 |
+
NODE_ISSUE_QUEUE_SCHEDULE_SCHEME 0
|
| 534 |
+
ISSUE_QUEUE_PARALLEL_PICK FALSE
|
| 535 |
+
RS_SIZES "256" 97 70 19
|
| 536 |
+
RS_CONNECTIONS "xF" b0100110011 b1000001100 b0011000000
|
| 537 |
+
FU_TYPES "0, 0, 0, 0" b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 538 |
+
LSQ_ENABLE TRUE
|
| 539 |
+
LOAD_QUEUE_ENTRY_NUM 128
|
| 540 |
+
STORE_QUEUE_ENTRY_NUM 72
|
| 541 |
+
DECODE_CYCLES 1 5
|
| 542 |
+
MAP_CYCLES 1 5
|
| 543 |
+
ICACHE_LATENCY 3
|
| 544 |
+
EXTRA_REDIRECT_CYCLES 0
|
| 545 |
+
EXTRA_RECOVERY_CYCLES 0
|
| 546 |
+
EXTRA_CALLSYS_CYCLES 20 const
|
| 547 |
+
DIE_ON_CALLSYS FALSE
|
| 548 |
+
DIE_ON_RET_STALL_THRESH 0
|
| 549 |
+
DIE_ON_RET_STALL_CORE 0
|
| 550 |
+
DIE_ON_MEM_BLOCK_THRESH 0
|
| 551 |
+
DIE_ON_MEM_BLOCK_CORE 0
|
| 552 |
+
ICACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 553 |
+
UOP_CACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 554 |
+
FETCH_OFF_PATH_OPS TRUE 1
|
| 555 |
+
WP_COLLECT_STATS TRUE
|
| 556 |
+
OP_INV_DELAY 1
|
| 557 |
+
OP_NOP_DELAY 1
|
| 558 |
+
OP_CF_DELAY 1
|
| 559 |
+
OP_MOV_DELAY 1
|
| 560 |
+
OP_CMOV_DELAY 1
|
| 561 |
+
OP_LDA_DELAY 1
|
| 562 |
+
OP_ILD_DELAY 1
|
| 563 |
+
OP_IST_DELAY 1
|
| 564 |
+
OP_IADD_DELAY 1
|
| 565 |
+
OP_IMUL_DELAY 3
|
| 566 |
+
OP_IDIV_DELAY -20
|
| 567 |
+
OP_ICMP_DELAY 1
|
| 568 |
+
OP_LOGIC_DELAY 1
|
| 569 |
+
OP_SHIFT_DELAY 1
|
| 570 |
+
OP_FLD_DELAY 1
|
| 571 |
+
OP_FST_DELAY 1
|
| 572 |
+
OP_FCVT_DELAY 3
|
| 573 |
+
OP_FADD_DELAY 3
|
| 574 |
+
OP_FMUL_DELAY 5
|
| 575 |
+
OP_FMA_DELAY 5
|
| 576 |
+
OP_FDIV_DELAY -20
|
| 577 |
+
OP_FCMP_DELAY 3
|
| 578 |
+
OP_FCMOV_DELAY 1
|
| 579 |
+
OP_GATHER_DELAY 12
|
| 580 |
+
OP_SCATTER_DELAY 18
|
| 581 |
+
OP_PIPELINED_FAST_DELAY 2
|
| 582 |
+
OP_PIPELINED_MEDIUM_DELAY 5
|
| 583 |
+
OP_PIPELINED_SLOW_DELAY 10
|
| 584 |
+
OP_NOTPIPELINED_MEDIUM_DELAY -5
|
| 585 |
+
OP_NOTPIPELINED_SLOW_DELAY -20
|
| 586 |
+
OP_NOTPIPELINED_VERY_SLOW_DELAY -100
|
| 587 |
+
UNIFORM_OP_DELAY 0
|
| 588 |
+
STALL_ON_WAIT_MEM TRUE
|
| 589 |
+
STORES_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 590 |
+
PREFS_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 591 |
+
OBEY_REG_DEP TRUE
|
| 592 |
+
TRACK_L1_MISS_DEPS FALSE
|
| 593 |
+
CBP_TRACE_R0 NULL /dev/shm/baseline/traces/.staging/tsp-164844/raw_trace/drmemtrace.tsp.164856.4389.dir/trace/drmemtrace.tsp.164856.1160.trace.zip
|
| 594 |
+
CBP_TRACE_R1 NULL
|
| 595 |
+
CBP_TRACE_R2 NULL
|
| 596 |
+
CBP_TRACE_R3 NULL
|
| 597 |
+
CBP_TRACE_R4 NULL
|
| 598 |
+
CBP_TRACE_R5 NULL
|
| 599 |
+
CBP_TRACE_R6 NULL
|
| 600 |
+
CBP_TRACE_R7 NULL
|
| 601 |
+
CBP_TRACE_R8 NULL
|
| 602 |
+
CBP_TRACE_R9 NULL
|
| 603 |
+
CBP_TRACE_R10 NULL
|
| 604 |
+
CBP_TRACE_R11 NULL
|
| 605 |
+
CBP_TRACE_R12 NULL
|
| 606 |
+
CBP_TRACE_R13 NULL
|
| 607 |
+
CBP_TRACE_R14 NULL
|
| 608 |
+
CBP_TRACE_R15 NULL
|
| 609 |
+
CBP_TRACE_R16 NULL
|
| 610 |
+
CBP_TRACE_R17 NULL
|
| 611 |
+
CBP_TRACE_R18 NULL
|
| 612 |
+
CBP_TRACE_R19 NULL
|
| 613 |
+
CBP_TRACE_R20 NULL
|
| 614 |
+
CBP_TRACE_R21 NULL
|
| 615 |
+
CBP_TRACE_R22 NULL
|
| 616 |
+
CBP_TRACE_R23 NULL
|
| 617 |
+
CBP_TRACE_R24 NULL
|
| 618 |
+
CBP_TRACE_R25 NULL
|
| 619 |
+
CBP_TRACE_R26 NULL
|
| 620 |
+
CBP_TRACE_R27 NULL
|
| 621 |
+
CBP_TRACE_R28 NULL
|
| 622 |
+
CBP_TRACE_R29 NULL
|
| 623 |
+
CBP_TRACE_R30 NULL
|
| 624 |
+
CBP_TRACE_R31 NULL
|
| 625 |
+
CBP_TRACE_R32 NULL
|
| 626 |
+
CBP_TRACE_R33 NULL
|
| 627 |
+
CBP_TRACE_R34 NULL
|
| 628 |
+
CBP_TRACE_R35 NULL
|
| 629 |
+
CBP_TRACE_R36 NULL
|
| 630 |
+
CBP_TRACE_R37 NULL
|
| 631 |
+
CBP_TRACE_R38 NULL
|
| 632 |
+
CBP_TRACE_R39 NULL
|
| 633 |
+
CBP_TRACE_R40 NULL
|
| 634 |
+
CBP_TRACE_R41 NULL
|
| 635 |
+
CBP_TRACE_R42 NULL
|
| 636 |
+
CBP_TRACE_R43 NULL
|
| 637 |
+
CBP_TRACE_R44 NULL
|
| 638 |
+
CBP_TRACE_R45 NULL
|
| 639 |
+
CBP_TRACE_R46 NULL
|
| 640 |
+
CBP_TRACE_R47 NULL
|
| 641 |
+
CBP_TRACE_R48 NULL
|
| 642 |
+
CBP_TRACE_R49 NULL
|
| 643 |
+
CBP_TRACE_R50 NULL
|
| 644 |
+
CBP_TRACE_R51 NULL
|
| 645 |
+
CBP_TRACE_R52 NULL
|
| 646 |
+
CBP_TRACE_R53 NULL
|
| 647 |
+
CBP_TRACE_R54 NULL
|
| 648 |
+
CBP_TRACE_R55 NULL
|
| 649 |
+
CBP_TRACE_R56 NULL
|
| 650 |
+
CBP_TRACE_R57 NULL
|
| 651 |
+
CBP_TRACE_R58 NULL
|
| 652 |
+
CBP_TRACE_R59 NULL
|
| 653 |
+
CBP_TRACE_R60 NULL
|
| 654 |
+
CBP_TRACE_R61 NULL
|
| 655 |
+
CBP_TRACE_R62 NULL
|
| 656 |
+
CBP_TRACE_R63 NULL
|
| 657 |
+
FE_FTQ_BLOCK_NUM 32
|
| 658 |
+
FE_FTQ_TAKEN_CFS_PER_CYCLE 2
|
| 659 |
+
FE_FTQ_FT_PER_CYCLE 1
|
| 660 |
+
DUMB_CORE_ON FALSE
|
| 661 |
+
DUMB_CORE 1
|
| 662 |
+
DCACHE_MISS_RATE 10
|
| 663 |
+
L1_MISS_RATE 10
|
| 664 |
+
TRACE_BUF_SIZE 0
|
| 665 |
+
PERFECT_CONFIDENCE FALSE
|
| 666 |
+
CONFIDENCE_ENABLE FALSE
|
| 667 |
+
CONFIDENCE_MECH 0
|
| 668 |
+
CONF_OFF_PATH_THRESHOLD 15
|
| 669 |
+
CONF_OFF_PATH_INC 5
|
| 670 |
+
CONF_BTB_MISS_BP_TAKEN FALSE
|
| 671 |
+
CONF_IPC_RATE_CONF FALSE
|
| 672 |
+
CONF_BTB_MISS_BP_TAKEN_THRESHOLD 0
|
| 673 |
+
CONF_BTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 674 |
+
CONF_IBTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 675 |
+
CONF_MISFETCH_RATE_CYCLES_THRESHOLD 1.0
|
| 676 |
+
CONF_MISPRED_RATE_CYCLES_THRESHOLD 1.0
|
| 677 |
+
CONF_BTB_MISS_SAMPLE_RATE 100000
|
| 678 |
+
CONF_IBTB_MISS_SAMPLE_RATE 100000
|
| 679 |
+
CONF_MISFETCH_SAMPLE_RATE 100000
|
| 680 |
+
CONF_MISPRED_SAMPLE_RATE 100000
|
| 681 |
+
CONF_IPC_SAMPLE_RATE 100000
|
| 682 |
+
CONF_BTB_MISS_RATE_WEIGHT 200
|
| 683 |
+
CONF_BTB_MISS_BP_TAKEN_CONF TRUE
|
| 684 |
+
CONF_IBTB_MISS_BP_TAKEN_CONF TRUE
|
| 685 |
+
CONF_BTB_MISS_RATE_CONF TRUE
|
| 686 |
+
CONF_IBTB_MISS_RATE_CONF TRUE
|
| 687 |
+
CONF_MISFETCH_RATE_CONF TRUE
|
| 688 |
+
CONF_MISPRED_RATE_CONF TRUE
|
| 689 |
+
CONF_INV_BP_CONF TRUE
|
| 690 |
+
CONF_PERFECT_BTB_MISS_CONF FALSE
|
| 691 |
+
CONF_PERFECT_IBTB_MISS_CONF FALSE
|
| 692 |
+
CONF_PERFECT_MISFETCH_CONF FALSE
|
| 693 |
+
CONF_PERFECT_MISPRED_CONF FALSE
|
| 694 |
+
CONF_LOG_DFE_TO_REC FALSE
|
| 695 |
+
CONF_LOG_PHASE_CYCLES FALSE
|
| 696 |
+
NUM_BPS 1
|
| 697 |
+
DFE0_TRIGGER_POLICY 0
|
| 698 |
+
DFE1_TRIGGER_POLICY 1
|
| 699 |
+
DFE2_TRIGGER_POLICY 1
|
| 700 |
+
DFE3_TRIGGER_POLICY 1
|
| 701 |
+
DFE4_TRIGGER_POLICY 1
|
| 702 |
+
DFE0_STOP_POLICY 0
|
| 703 |
+
DFE1_STOP_POLICY 1
|
| 704 |
+
DFE2_STOP_POLICY 1
|
| 705 |
+
DFE3_STOP_POLICY 1
|
| 706 |
+
DFE4_STOP_POLICY 1
|
| 707 |
+
LOOKAHEAD_BUF_SIZE 0
|
| 708 |
+
DEBUG_CYCLE_START 0 0
|
| 709 |
+
DEBUG_CYCLE_STOP 0 -1
|
| 710 |
+
DEBUG_TIME_START 0
|
| 711 |
+
DEBUG_TIME_STOP 0
|
| 712 |
+
DEBUG_INST_START 0 0
|
| 713 |
+
DEBUG_INST_STOP 0 -1
|
| 714 |
+
DEBUG_OP_START 0
|
| 715 |
+
DEBUG_OP_STOP 0
|
| 716 |
+
DEBUG_CACHE_LIB FALSE
|
| 717 |
+
DEBUG_HASH_LIB FALSE
|
| 718 |
+
DEBUG_LIST_LIB FALSE
|
| 719 |
+
DEBUG_PORT_LIB FALSE
|
| 720 |
+
DEBUG_BUS_LIB FALSE
|
| 721 |
+
DEBUG_OP_POOL FALSE
|
| 722 |
+
DEBUG_ORACLE FALSE
|
| 723 |
+
DEBUG_FRONTEND FALSE
|
| 724 |
+
DEBUG_ADDR_TRANS FALSE
|
| 725 |
+
DEBUG_BP FALSE
|
| 726 |
+
DEBUG_BP_DIR FALSE
|
| 727 |
+
DEBUG_BTB FALSE
|
| 728 |
+
DEBUG_CRS FALSE
|
| 729 |
+
DEBUG_MAP FALSE
|
| 730 |
+
DEBUG_MEMORY FALSE
|
| 731 |
+
DEBUG_REPLAY FALSE
|
| 732 |
+
DEBUG_FREQ FALSE
|
| 733 |
+
DEBUG_MODEL FALSE
|
| 734 |
+
DEBUG_THREAD FALSE
|
| 735 |
+
DEBUG_DECOUPLED_FE FALSE
|
| 736 |
+
DEBUG_CONF FALSE
|
| 737 |
+
DEBUG_ICACHE_STAGE FALSE
|
| 738 |
+
DEBUG_DECODE_STAGE FALSE
|
| 739 |
+
DEBUG_CPP_CACHE FALSE
|
| 740 |
+
DEBUG_UOP_CACHE FALSE
|
| 741 |
+
DEBUG_UOP_QUEUE_STAGE FALSE
|
| 742 |
+
DEBUG_IDQ_STAGE FALSE
|
| 743 |
+
DEBUG_MAP_STAGE FALSE
|
| 744 |
+
DEBUG_NODE_STAGE FALSE
|
| 745 |
+
DEBUG_EXEC_STAGE FALSE
|
| 746 |
+
DEBUG_DCACHE_STAGE FALSE
|
| 747 |
+
DEBUG_RETIRED_UOPS FALSE
|
| 748 |
+
DEBUG_EXC_INSERTS FALSE
|
| 749 |
+
DEBUG_BP_CONF FALSE
|
| 750 |
+
DEBUG_ONPATH_CONF FALSE
|
| 751 |
+
DEBUG_STREAM FALSE
|
| 752 |
+
DEBUG_STREAM_MEM FALSE
|
| 753 |
+
DEBUG_WAY FALSE
|
| 754 |
+
DEBUG_L2MARKV FALSE
|
| 755 |
+
DEBUG_L2L1PREF FALSE
|
| 756 |
+
DEBUG_PERF_PRED FALSE
|
| 757 |
+
DEBUG_POWER_UTILS FALSE
|
| 758 |
+
DEBUG_DVFS FALSE
|
| 759 |
+
DEBUG_TRACE_READ FALSE
|
| 760 |
+
DEBUG_INST_FIELDS FALSE
|
| 761 |
+
DEBUG_OP_FIELDS FALSE
|
| 762 |
+
DEBUG_PIN_EXEC_DRIVEN FALSE
|
| 763 |
+
DEBUG_CACHE_PART FALSE
|
| 764 |
+
DEBUG_OPTIMIZER2 FALSE
|
| 765 |
+
DEBUG_PREF FALSE
|
| 766 |
+
DEBUG_FDIP FALSE
|
| 767 |
+
DEBUG_EIP FALSE
|
| 768 |
+
DEBUG_DJOLT FALSE
|
| 769 |
+
DEBUG_FNLMMA FALSE
|
| 770 |
+
PERFECT_BP FALSE
|
| 771 |
+
PERFECT_BTB FALSE
|
| 772 |
+
PERFECT_IBP FALSE
|
| 773 |
+
PERFECT_CRS FALSE
|
| 774 |
+
PERFECT_CBR_BTB FALSE
|
| 775 |
+
PERFECT_NT_BTB FALSE 0 # deprecated, effectively always true.
|
| 776 |
+
CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle
|
| 777 |
+
UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 778 |
+
BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec.
|
| 779 |
+
BP_MECH TAGE64K_BP tage64k
|
| 780 |
+
BP_MECH_L0 BIMODAL_BP
|
| 781 |
+
BP_L0_LATENCY 1
|
| 782 |
+
BP_MAIN_LATENCY 3
|
| 783 |
+
BIMODAL_ENTRIES (4 * 1024)
|
| 784 |
+
HIST_LENGTH 16
|
| 785 |
+
PHT_CTR_BITS 2 const
|
| 786 |
+
BHT_ENTRIES (4 * 1024)
|
| 787 |
+
BHT_ASSOC 4
|
| 788 |
+
HYBRIDS_INDEX_LENGTH 16
|
| 789 |
+
HYBRIDG_HIST_LENGTH 16
|
| 790 |
+
HYBRIDP_HIST_LENGTH 16
|
| 791 |
+
FILTER_INDEX_LENGTH 16
|
| 792 |
+
USE_FILTER FALSE
|
| 793 |
+
INF_HYBRIDGP FALSE
|
| 794 |
+
BP_HASH_TOS FALSE
|
| 795 |
+
IBTB_HASH_TOS FALSE
|
| 796 |
+
BTB_MECH GENERIC_BTB generic
|
| 797 |
+
BTB_ENTRIES 12288 12288
|
| 798 |
+
BTB_ASSOC 4 4
|
| 799 |
+
BTB_NUM_BRSLOT 1
|
| 800 |
+
BTB_BLOCK_SIZE 64
|
| 801 |
+
BTB_OFF_PATH_WRITES TRUE 1
|
| 802 |
+
BTB_MAIN_LATENCY 3 3
|
| 803 |
+
BTB_L0_PRESENT FALSE 1
|
| 804 |
+
BTB_L0_ENTRIES 128 128
|
| 805 |
+
BTB_L0_ASSOC 4 4
|
| 806 |
+
BTB_L0_LATENCY 1 1
|
| 807 |
+
BTB_L1_PRESENT FALSE 1
|
| 808 |
+
BTB_L1_ENTRIES 6144 6144
|
| 809 |
+
BTB_L1_ASSOC 4 4
|
| 810 |
+
BTB_L1_LATENCY 2 2
|
| 811 |
+
ENABLE_CRS TRUE 1
|
| 812 |
+
CRS_ENTRIES 32 128
|
| 813 |
+
CRS_REALISTIC 0 1
|
| 814 |
+
ENABLE_IBP TRUE 1 # Enable the indirect branch predictor
|
| 815 |
+
USE_PAT_HIST TRUE
|
| 816 |
+
IBTB_MECH 1 tc_tagged
|
| 817 |
+
IBTB_HIST_LENGTH 16
|
| 818 |
+
IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb.
|
| 819 |
+
TARGETS_IN_HIST 4
|
| 820 |
+
TC_ENTRIES (4 * 1024) 4096
|
| 821 |
+
TC_ASSOC 4 4
|
| 822 |
+
NUM_CORR_BRANCHES 3
|
| 823 |
+
SEL_HIST_BP_ENTRIES 8192
|
| 824 |
+
SEL_HIST_LENGTH 16
|
| 825 |
+
SEL_HIST_DYN_CNT_TH 16
|
| 826 |
+
SEL_HIST_MISPRED_TH 4
|
| 827 |
+
ENABLE_BP_CONF FALSE
|
| 828 |
+
CONF_MECH 0
|
| 829 |
+
PERF_BP_CONF_PRED FALSE
|
| 830 |
+
BPC_BITS 16
|
| 831 |
+
BPC_MECH 1
|
| 832 |
+
BPC_CTR_RESET TRUE
|
| 833 |
+
BPC_CIT_BITS 8
|
| 834 |
+
BPC_CIT_TH 50
|
| 835 |
+
BPC_CTR_BITS 3
|
| 836 |
+
OPC_COUNT_ZEROS FALSE
|
| 837 |
+
OPC_COUNT_THRESH 10
|
| 838 |
+
INF_LOOP FALSE
|
| 839 |
+
INF_LOOP_BUCKETS 811
|
| 840 |
+
LOOP_ENTRIES (4 * 1024)
|
| 841 |
+
LOOP_ASSOC 4
|
| 842 |
+
LOOP_COUNT_MAX 127
|
| 843 |
+
LOOP_REPEAT_MAX 15
|
| 844 |
+
KNOB_PRINT_BRINFO FALSE
|
| 845 |
+
BR_MISPRED_FILE NULL
|
| 846 |
+
SPEC_LEVEL 3
|
| 847 |
+
RANDOM_DETERMINISTIC TRUE
|
| 848 |
+
TAGESCL64KB_SC TRUE
|
| 849 |
+
TAGESCL64KB_LOOP TRUE
|
| 850 |
+
TAGESCL64KB_ALT TRUE
|
| 851 |
+
CONF_PERCEPTRON_TH 0
|
| 852 |
+
CONF_PERCEPTRON_CTR_BITS 8
|
| 853 |
+
CONF_PERCEPTRON_ENTRIES 127
|
| 854 |
+
CONF_PERCEPTRON_THRESH_OVRD 0
|
| 855 |
+
CONF_HIST_LENGTH 32
|
| 856 |
+
PERCEPTRON_CONF_USE_CONF FALSE
|
| 857 |
+
PERCEPTRON_CONF_TRAIN_HIS FALSE
|
| 858 |
+
PERCEPTRON_CONF_TRAIN_CONF FALSE
|
| 859 |
+
PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE
|
| 860 |
+
PERCEPTRON_TRAIN_MISP_FACTOR 1
|
| 861 |
+
PERCEPTRON_TRAIN_CORR_FACTOR 1
|
| 862 |
+
PERCEPTRON_CONF_HIS_BOTH FALSE
|
| 863 |
+
PERCEPTRON_CONF_HIS_BOTH_LENGTH 4
|
| 864 |
+
MTAGE_REALISTIC_SC_40K FALSE
|
| 865 |
+
MTAGE_REALISTIC_SC_100K FALSE
|
| 866 |
+
H2P_TABLE_BUCKETS 16384
|
| 867 |
+
H2P_MIN_EXEC 5000
|
| 868 |
+
H2P_MIN_MISPRED 333
|
| 869 |
+
H2P_MISPRED_RATIO_PERMIL 10
|
| 870 |
+
H2P_TRACK_CBR TRUE
|
| 871 |
+
H2P_TRACK_REP TRUE
|
| 872 |
+
H2P_TRACK_CALL FALSE
|
| 873 |
+
H2P_TRACK_IBR FALSE
|
| 874 |
+
H2P_TRACK_ICALL FALSE
|
| 875 |
+
H2P_TRACK_RET FALSE
|
| 876 |
+
POWER_INTF_ON FALSE
|
| 877 |
+
POWER_INTF_ENABLE_SCALING FALSE
|
| 878 |
+
POWER_INTF_EXEC "power/power_intf.py"
|
| 879 |
+
POWER_INTF_REF_CHIP_TECH_NM 22
|
| 880 |
+
POWER_INTF_REF_CHIP_FREQ (3.2e9)
|
| 881 |
+
POWER_INTF_REF_MEMORY_FREQ (0.8e9)
|
| 882 |
+
POWER_OTHER (0.0)
|
| 883 |
+
PREF_STREAM_ON FALSE 1
|
| 884 |
+
PREF_STREAM_PER_CORE_ENABLE FALSE
|
| 885 |
+
STREAM_BUFFER_N 16
|
| 886 |
+
STREAM_PREFETCH_N 2 4
|
| 887 |
+
STREAM_START_DIS 5 1
|
| 888 |
+
STREAM_LENGTH 16 64
|
| 889 |
+
STREAM_FULL_N 1
|
| 890 |
+
STREAM_TRAIN_LENGTH 16
|
| 891 |
+
STREAM_TRAIN_NUM 1 4
|
| 892 |
+
PREF_ACC_USE_CACHE FALSE
|
| 893 |
+
STREAM_STALL_ON_QUEUE_FULL FALSE
|
| 894 |
+
PREF_SCHEDULE_NUM 4
|
| 895 |
+
TRAIN_FILTER_SIZE 32
|
| 896 |
+
PREF_REQ_Q_SIZE 64
|
| 897 |
+
STREAM_CREATE_ON_DC_MISS FALSE 0
|
| 898 |
+
STREAM_CREATE_ON_L1_MISS TRUE 1
|
| 899 |
+
STREAM_TRAIN_ON_WRONGPATH TRUE
|
| 900 |
+
STREAM_CREATE_ON_WRONGPATH TRUE
|
| 901 |
+
STREAM_PREF_INTO_DCACHE FALSE
|
| 902 |
+
REMOVE_REDUNDANT_STREAM FALSE
|
| 903 |
+
L2HIT_STREAM_SCHEDULE_NUM 4
|
| 904 |
+
PREF_REQ_QUEUE_FILTER_ON FALSE
|
| 905 |
+
HW_PREF_HIT_TRAIN_STREAM FALSE
|
| 906 |
+
L2HIT_STREAM_BUFFER_N 32
|
| 907 |
+
L2HIT_STREAM_PREFETCH_N 2
|
| 908 |
+
L2HIT_STREAM_START_DIS 2
|
| 909 |
+
L2HIT_STREAM_LENGTH 8
|
| 910 |
+
L2HIT_PREF_REQ_Q_SIZE 128
|
| 911 |
+
L2HIT_L2ACCESS_REQ_Q_SIZE 64
|
| 912 |
+
PREF_STREAM_ACCPERSTREAM FALSE
|
| 913 |
+
PREF_ACC_DISTANCE_10 128
|
| 914 |
+
PREF_FRAMEWORK_ON FALSE 1
|
| 915 |
+
PREF_TRACE_ON FALSE
|
| 916 |
+
PREF_UMLC_ON FALSE
|
| 917 |
+
PREF_UL1_ON TRUE
|
| 918 |
+
PREF_DL0REQ_QUEUE_SIZE 32
|
| 919 |
+
PREF_UMLC_REQ_QUEUE_SIZE 64
|
| 920 |
+
PREF_UL1REQ_QUEUE_SIZE 128
|
| 921 |
+
PREF_SHARED_QUEUES TRUE
|
| 922 |
+
PREF_DL0_MISS_ON TRUE
|
| 923 |
+
PREF_DL0_HIT_ON TRUE
|
| 924 |
+
PREF_DL0REQ_QUEUE_FILTER_ON TRUE
|
| 925 |
+
PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE
|
| 926 |
+
PREF_UL1REQ_QUEUE_FILTER_ON TRUE
|
| 927 |
+
PREF_DL0REQ_ADD_FILTER_ON TRUE
|
| 928 |
+
PREF_UMLC_REQ_ADD_FILTER_ON TRUE
|
| 929 |
+
PREF_UL1REQ_ADD_FILTER_ON TRUE
|
| 930 |
+
PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 931 |
+
PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 932 |
+
PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1
|
| 933 |
+
PREF_DL0SCHEDULE_NUM 4
|
| 934 |
+
PREF_UMLC_SCHEDULE_NUM 4
|
| 935 |
+
PREF_UL1SCHEDULE_NUM 4
|
| 936 |
+
PREF_L1Q_DEMAND_RESERVE 0
|
| 937 |
+
PREF_REPORT_PREF_MATCH_AS_MISS FALSE
|
| 938 |
+
PREF_REPORT_PREF_MATCH_AS_HIT TRUE
|
| 939 |
+
PREF_UPDATE_ON_WRONGPATH TRUE
|
| 940 |
+
PREF_TRAIN_ON_PREF_MISSES FALSE 0
|
| 941 |
+
PREF_ORACLE_TRAIN_ON FALSE 0
|
| 942 |
+
PREF_REQ_DROP FALSE
|
| 943 |
+
PREF_THROTTLE_ON FALSE
|
| 944 |
+
PREF_THROTTLEFB_ON FALSE 1
|
| 945 |
+
PREF_ACC_THRESH_1 0.90 0.75
|
| 946 |
+
PREF_ACC_THRESH_2 0.70 0.4
|
| 947 |
+
PREF_ACC_THRESH_3 0.60 0.4
|
| 948 |
+
PREF_ACC_THRESH_4 0.40
|
| 949 |
+
PREF_UPDATE_INTERVAL 0 8192
|
| 950 |
+
PREF_ANALYZE_LOAD FALSE
|
| 951 |
+
PREF_POL_THRESH_1 0.25
|
| 952 |
+
PREF_POL_THRESH_2 0.10
|
| 953 |
+
PREF_POLBV_ON FALSE
|
| 954 |
+
PREF_POLBV_SIZE 1024
|
| 955 |
+
PREF_TIMELY_THRESH 0.05 0.01
|
| 956 |
+
PREF_POLPF_THRESH 0.01 0.005
|
| 957 |
+
PREF_DEGFB_USEONLYACC FALSE
|
| 958 |
+
PREF_DEGFB_USEONLYPOL FALSE
|
| 959 |
+
PREF_DEGFB_USEONLYLATE FALSE
|
| 960 |
+
PREF_TIMELY_THRESH_2 0.005
|
| 961 |
+
PREF_DEGFB_STATPHASEFILE FALSE
|
| 962 |
+
PREF_MAX_DEGFB 4
|
| 963 |
+
PREF_DHAL FALSE
|
| 964 |
+
PREF_DHAL_SENTTHRESH 16
|
| 965 |
+
PREF_DHAL_USETHRESH_MAX 12
|
| 966 |
+
PREF_DHAL_USETHRESH_MIN2 8
|
| 967 |
+
PREF_DHAL_USETHRESH_MIN1 4
|
| 968 |
+
PREF_DHAL_MAXDEG 64
|
| 969 |
+
PREF_HFILTER_ON FALSE
|
| 970 |
+
PREF_HFILTER_INDEX_BITS 12
|
| 971 |
+
PREF_HFILTER_USE_PC FALSE
|
| 972 |
+
PREF_HFILTER_PRED_USELESS_THRES 2
|
| 973 |
+
PREF_HFILTER_RESET_ENABLE FALSE
|
| 974 |
+
PREF_HFILTER_RESET_INTERVAL 100000
|
| 975 |
+
EIP_ENABLE 0
|
| 976 |
+
L1I_ENTANGLED_TABLE_INDEX_BITS 9
|
| 977 |
+
L1I_ENTANGLED_TABLE_WAYS 16
|
| 978 |
+
DJOLT_ENABLE 0
|
| 979 |
+
FNLMMA_ENABLE 0
|
| 980 |
+
FDIP_ENABLE 1
|
| 981 |
+
FDIP_ALWAYS_PREFETCH FALSE
|
| 982 |
+
PERFECT_FDIP FALSE
|
| 983 |
+
IPRF_MAX_FTQ_ENTRY_CYC 2
|
| 984 |
+
FDIP_BLOOM_FILTER FALSE
|
| 985 |
+
FDIP_BLOOM_ENTRIES 4000
|
| 986 |
+
FDIP_BLOOM2_ENTRIES 1000
|
| 987 |
+
FDIP_BLOOM4_ENTRIES 1000
|
| 988 |
+
FDIP_BLOOM_SIZE 16384
|
| 989 |
+
FDIP_BLOOM_HASHES 6
|
| 990 |
+
FDIP_BLOOM_CLEAR_UNUSEFUL_RATIO 0.95
|
| 991 |
+
FDIP_BLOOM_CLEAR_CYC_PERIOD 10000
|
| 992 |
+
FDIP_UTILITY_HASH_ENABLE 0
|
| 993 |
+
FDIP_UTILITY_PREF_POLICY 0
|
| 994 |
+
FDIP_ADJUSTABLE_FTQ 0
|
| 995 |
+
FDIP_ADJUSTABLE_FTQ_CYC 100000
|
| 996 |
+
UTILITY_RATIO_THRESHOLD 0.58
|
| 997 |
+
TIMELINESS_RATIO_THRESHOLD 0.82
|
| 998 |
+
FDIP_PREF_NO_LATENCY FALSE
|
| 999 |
+
UDP_USEFUL_THRESHOLD 0
|
| 1000 |
+
UDP_WEIGHT_USEFUL 4
|
| 1001 |
+
UDP_WEIGHT_UNUSEFUL 1
|
| 1002 |
+
UDP_WEIGHT_POSITIVE_SATURATION 2147483647
|
| 1003 |
+
FDIP_GHIST_HASHING FALSE
|
| 1004 |
+
FDIP_UTILITY_ONLY_TRAIN_OFF_PATH FALSE
|
| 1005 |
+
FDIP_GHIST_BITS 8
|
| 1006 |
+
UFTQ_MIN_FTQ_BLOCK_NUM 4
|
| 1007 |
+
UFTQ_MAX_FTQ_BLOCK_NUM 64
|
| 1008 |
+
FDIP_SENIORITY_FTQ_HOLD_CYC 30000
|
| 1009 |
+
FDIP_PERFECT_PREFETCH FALSE
|
| 1010 |
+
FDIP_FREEZE_AT_MEM_BUF_LIMIT TRUE
|
| 1011 |
+
FDIP_DUAL_PATH_PREF_IC_ENABLE FALSE
|
| 1012 |
+
FDIP_DUAL_PATH_PREF_UOC_ENABLE FALSE
|
| 1013 |
+
TOP_MISPRED_BR_FILEPATH "br_resteer_coverage.csv"
|
| 1014 |
+
TOP_MISPRED_BR_RESTEER_COVERAGE 0
|
| 1015 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_ENABLE FALSE
|
| 1016 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_MISPRED_THRESHOLD 1
|
| 1017 |
+
FDIP_PRINT_CL_INFO FALSE
|
| 1018 |
+
BRANCH_MISPREDICTION_TABLE_SIZE 0
|
| 1019 |
+
UOC_PREF FALSE
|
| 1020 |
+
UOC_ORACLE_PREF FALSE
|
| 1021 |
+
UOC_ZERO_LATENCY_PREF FALSE
|
| 1022 |
+
L2L1PREF_ON FALSE
|
| 1023 |
+
L2WAY_PREF FALSE
|
| 1024 |
+
L2MARKV_PREF_ON FALSE
|
| 1025 |
+
L2NEXT_PREF_ON FALSE
|
| 1026 |
+
L2HIT_STREAM_PREF_ON FALSE
|
| 1027 |
+
L2L1_DC_HIT_TRAIN FALSE
|
| 1028 |
+
L1_HIT_DUMP_FILE_ON FALSE
|
| 1029 |
+
L1_HIT_DUMP_WO_TXT FALSE
|
| 1030 |
+
L1_HIT_DUMPFILE "l1hit_dump.out"
|
| 1031 |
+
IDEAL_L2_L1_PREFETCHER FALSE
|
| 1032 |
+
IDEAL_L2_ICACHE_PREFETCHER FALSE
|
| 1033 |
+
L1WAY_PREF_SEND_QUEUE 4
|
| 1034 |
+
L1PREF_REQ_QUEUE_SIZE 1024
|
| 1035 |
+
L1PREF_IMMEDIATE FALSE
|
| 1036 |
+
L1WAY_PREF_TIMER_DIS 1000
|
| 1037 |
+
L1MARKV_PREF_SEND_QUEUE 4
|
| 1038 |
+
L1PREF_MARKV_REQ_QUEUE_SIZE 1024
|
| 1039 |
+
MARKV_L2ACCESS_REQ_Q_SIZE 64
|
| 1040 |
+
L1MARKV_PREF_IMMEDIATE FALSE
|
| 1041 |
+
L1MARKV_PREF_TIMER_DIS 1
|
| 1042 |
+
L2L1_HIT_TRAIN TRUE
|
| 1043 |
+
L1MARKV_REQ_TH 1
|
| 1044 |
+
L2L1_IMMEDIATE_PREF_CACHE FALSE
|
| 1045 |
+
L2L1_FILL_PREF_CACHE FALSE
|
| 1046 |
+
L2L1_L2_HIT_STAT FALSE
|
| 1047 |
+
PREF_GHB_ON FALSE
|
| 1048 |
+
DEBUG_PREF_GHB FALSE
|
| 1049 |
+
PREF_GHB_BUFFER_N 1024
|
| 1050 |
+
PREF_GHB_INDEX_N 128
|
| 1051 |
+
PREF_GHB_CZONE_BITS 12
|
| 1052 |
+
PREF_GHB_DEGREE 16
|
| 1053 |
+
PREF_GHB_MAX_DEGREE 32
|
| 1054 |
+
PREF_STRIDE_ON FALSE
|
| 1055 |
+
DEBUG_PREF_STRIDE FALSE
|
| 1056 |
+
PREF_STRIDE_TABLE_N 1024
|
| 1057 |
+
PREF_STRIDE_REGION_BITS 16
|
| 1058 |
+
PREF_STRIDE_DEGREE 4
|
| 1059 |
+
PREF_STRIDE_DISTANCE 16
|
| 1060 |
+
PREF_STRIDE_STARTDISTANCE 1
|
| 1061 |
+
PREF_STRIDE_SINGLE_THRESH 6
|
| 1062 |
+
PREF_STRIDE_MULTI_THRESH 6
|
| 1063 |
+
PREF_STRIDE_SINGLE_STRIDE_MODE FALSE
|
| 1064 |
+
PREF_STRIDEPC_ON FALSE
|
| 1065 |
+
DEBUG_PREF_STRIDEPC FALSE
|
| 1066 |
+
PREF_STRIDEPC_TABLE_N 1024
|
| 1067 |
+
PREF_STRIDEPC_DEGREE 4
|
| 1068 |
+
PREF_STRIDEPC_DISTANCE 16
|
| 1069 |
+
PREF_STRIDEPC_USELOADADDR FALSE
|
| 1070 |
+
PREF_STRIDEPC_TRAINNUM 2
|
| 1071 |
+
PREF_STRIDEPC_STARTDIS 4
|
| 1072 |
+
PREF_PHASE_ON FALSE
|
| 1073 |
+
PREF_PHASE_STUDY FALSE
|
| 1074 |
+
DEBUG_PREF_PHASE FALSE
|
| 1075 |
+
PREF_PHASE_PRIME_HASH 16381
|
| 1076 |
+
PREF_PHASE_INFOSIZE 16384
|
| 1077 |
+
PREF_PHASE_LOG2REGIONSIZE 12
|
| 1078 |
+
PREF_PHASE_REGIONENTRIES 64
|
| 1079 |
+
PREF_PHASE_TRACKEDREGIONS 32
|
| 1080 |
+
PREF_PHASE_INTERVAL 100000
|
| 1081 |
+
PREF_PHASE_TABLE_SIZE 64
|
| 1082 |
+
PREF_PHASE_MAXDIFF_THRESH 64
|
| 1083 |
+
PREF_PHASE_MIN_MISSES 64
|
| 1084 |
+
PREF_PHASE_MISSPER 0.4
|
| 1085 |
+
PREF_2DC_ON FALSE
|
| 1086 |
+
DEBUG_PREF_2DC FALSE
|
| 1087 |
+
PREF_2DC_CACHE_SIZE (1 * 1024)
|
| 1088 |
+
PREF_2DC_CACHE_ASSOC 4
|
| 1089 |
+
PREF_2DC_CACHE_LINE_SIZE 1
|
| 1090 |
+
PREF_2DC_DEGREE 16
|
| 1091 |
+
PREF_2DC_ZONE_SHIFT 10
|
| 1092 |
+
PREF_2DC_TAG_SIZE 16
|
| 1093 |
+
PREF_2DC_NUM_REGIONS 64
|
| 1094 |
+
PREF_2DC_REGION_HASH 61
|
| 1095 |
+
PREF_MARKOV_ON FALSE
|
| 1096 |
+
DEBUG_PREF_MARKOV FALSE
|
| 1097 |
+
PREF_MARKOV_NUM_ENTRIES 65536
|
| 1098 |
+
PREF_MARKOV_NUM_NEXT_STATES 8
|
| 1099 |
+
PREF_MARKOV_SEND_ON_PREF_HIT TRUE
|
| 1100 |
+
PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE
|
| 1101 |
+
PREF_MARKOV_TABLE_UPDATE_POLICY 0
|
| 1102 |
+
PREF_MARKOV_SEND_THRESHOLD 0
|
tsp/fingerprint/run_1/sim.log
ADDED
|
@@ -0,0 +1,847 @@
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|
| 1 |
+
[0]: ad: 0x7ffff3d8e3f4, op: 315
|
| 2 |
+
new bb detected: 1
|
| 3 |
+
[1]: ad: 0x7ffff3d8e3fa, op: 427
|
| 4 |
+
[1]: ad: 0x7ffff3d8e3fd, op: 427
|
| 5 |
+
[1]: ad: 0x7ffff3d8e401, op: 427
|
| 6 |
+
[1]: ad: 0x7ffff3d8e405, op: 109
|
| 7 |
+
[1]: ad: 0x7ffff3d8e408, op: 330
|
| 8 |
+
new bb detected: 2
|
| 9 |
+
[2]: ad: 0x7ffff3d8e40e, op: 796
|
| 10 |
+
[2]: ad: 0x7ffff3d8e412, op: 316
|
| 11 |
+
new bb detected: 3
|
| 12 |
+
[3]: ad: 0x7ffff3d8e427, op: 427
|
| 13 |
+
[3]: ad: 0x7ffff3d8e42e, op: 465
|
| 14 |
+
[3]: ad: 0x7ffff3d8e431, op: 427
|
| 15 |
+
[3]: ad: 0x7ffff3d8e435, op: 427
|
| 16 |
+
[3]: ad: 0x7ffff3d8e438, op: 8
|
| 17 |
+
[3]: ad: 0x7ffff3d8e43b, op: 109
|
| 18 |
+
[3]: ad: 0x7ffff3d8e43d, op: 320
|
| 19 |
+
new bb detected: 4
|
| 20 |
+
[4]: ad: 0x7ffff3d8e418, op: 8
|
| 21 |
+
[4]: ad: 0x7ffff3d8e41c, op: 109
|
| 22 |
+
[4]: ad: 0x7ffff3d8e41f, op: 330
|
| 23 |
+
new bb detected: 5
|
| 24 |
+
[5]: ad: 0x7ffff3d8e421, op: 427
|
| 25 |
+
[5]: ad: 0x7ffff3d8e427, op: 427
|
| 26 |
+
[5]: ad: 0x7ffff3d8e42e, op: 465
|
| 27 |
+
[5]: ad: 0x7ffff3d8e431, op: 427
|
| 28 |
+
[5]: ad: 0x7ffff3d8e435, op: 427
|
| 29 |
+
[5]: ad: 0x7ffff3d8e438, op: 8
|
| 30 |
+
[5]: ad: 0x7ffff3d8e43b, op: 109
|
| 31 |
+
[5]: ad: 0x7ffff3d8e43d, op: 320
|
| 32 |
+
new bb detected: 6
|
| 33 |
+
[6]: ad: 0x7ffff3d8e49f, op: 8
|
| 34 |
+
[6]: ad: 0x7ffff3d8e4a3, op: 616
|
| 35 |
+
[6]: ad: 0x7ffff3d8e4a4, op: 616
|
| 36 |
+
[6]: ad: 0x7ffff3d8e4a5, op: 616
|
| 37 |
+
[6]: ad: 0x7ffff3d8e4a7, op: 616
|
| 38 |
+
[6]: ad: 0x7ffff3d8e4a9, op: 616
|
| 39 |
+
[6]: ad: 0x7ffff3d8e4ab, op: 616
|
| 40 |
+
[6]: ad: 0x7ffff3d8e4ad, op: 740
|
| 41 |
+
new bb detected: 7
|
| 42 |
+
[7]: ad: 0x7ffff3d8e596, op: 847
|
| 43 |
+
[7]: ad: 0x7ffff3d8e599, op: 330
|
| 44 |
+
new bb detected: 8
|
| 45 |
+
[8]: ad: 0x7ffff3d8e59b, op: 427
|
| 46 |
+
[8]: ad: 0x7ffff3d8e5a0, op: 847
|
| 47 |
+
[8]: ad: 0x7ffff3d8e5a3, op: 330
|
| 48 |
+
new bb detected: 9
|
| 49 |
+
[9]: ad: 0x7ffff3d8e5a5, op: 75
|
| 50 |
+
new bb detected: 10
|
| 51 |
+
[10]: ad: 0x7ffff3d8d270, op: 482
|
| 52 |
+
[10]: ad: 0x7ffff3d8d274, op: 316
|
| 53 |
+
new bb detected: 11
|
| 54 |
+
[11]: ad: 0x7ffff7338c10, op: 482
|
| 55 |
+
[11]: ad: 0x7ffff7338c14, op: 316
|
| 56 |
+
new bb detected: 12
|
| 57 |
+
[12]: ad: 0x7ffff732bb30, op: 482
|
| 58 |
+
[12]: ad: 0x7ffff732bb34, op: 316
|
| 59 |
+
new bb detected: 13
|
| 60 |
+
[13]: ad: 0x7ffff71083e0, op: 482
|
| 61 |
+
[13]: ad: 0x7ffff71083e4, op: 847
|
| 62 |
+
[13]: ad: 0x7ffff71083e7, op: 330
|
| 63 |
+
new bb detected: 14
|
| 64 |
+
[14]: ad: 0x7ffff71083ed, op: 671
|
| 65 |
+
[14]: ad: 0x7ffff71083ee, op: 388
|
| 66 |
+
[14]: ad: 0x7ffff71083f2, op: 671
|
| 67 |
+
[14]: ad: 0x7ffff71083f3, op: 826
|
| 68 |
+
[14]: ad: 0x7ffff71083f7, op: 427
|
| 69 |
+
[14]: ad: 0x7ffff71083fe, op: 427
|
| 70 |
+
[14]: ad: 0x7ffff7108402, op: 427
|
| 71 |
+
[14]: ad: 0x7ffff7108405, op: 847
|
| 72 |
+
[14]: ad: 0x7ffff7108407, op: 325
|
| 73 |
+
new bb detected: 15
|
| 74 |
+
[15]: ad: 0x7ffff7108409, op: 427
|
| 75 |
+
[15]: ad: 0x7ffff7108410, op: 109
|
| 76 |
+
[15]: ad: 0x7ffff7108415, op: 330
|
| 77 |
+
new bb detected: 16
|
| 78 |
+
[16]: ad: 0x7ffff710841b, op: 388
|
| 79 |
+
[16]: ad: 0x7ffff7108422, op: 847
|
| 80 |
+
[16]: ad: 0x7ffff7108424, op: 330
|
| 81 |
+
new bb detected: 17
|
| 82 |
+
[17]: ad: 0x7ffff710844c, op: 1723
|
| 83 |
+
[17]: ad: 0x7ffff710844e, op: 75
|
| 84 |
+
new bb detected: 18
|
| 85 |
+
[18]: ad: 0x7ffff71056a0, op: 671
|
| 86 |
+
[18]: ad: 0x7ffff71056a2, op: 671
|
| 87 |
+
[18]: ad: 0x7ffff71056a4, op: 671
|
| 88 |
+
[18]: ad: 0x7ffff71056a6, op: 427
|
| 89 |
+
[18]: ad: 0x7ffff71056a9, op: 671
|
| 90 |
+
[18]: ad: 0x7ffff71056ab, op: 671
|
| 91 |
+
[18]: ad: 0x7ffff71056ac, op: 671
|
| 92 |
+
[18]: ad: 0x7ffff71056ad, op: 826
|
| 93 |
+
[18]: ad: 0x7ffff71056b1, op: 427
|
| 94 |
+
[18]: ad: 0x7ffff71056b5, op: 427
|
| 95 |
+
[18]: ad: 0x7ffff71056be, op: 427
|
| 96 |
+
[18]: ad: 0x7ffff71056c3, op: 1723
|
| 97 |
+
[18]: ad: 0x7ffff71056c5, op: 427
|
| 98 |
+
[18]: ad: 0x7ffff71056c8, op: 31
|
| 99 |
+
[18]: ad: 0x7ffff71056cc, op: 427
|
| 100 |
+
[18]: ad: 0x7ffff71056cf, op: 480
|
| 101 |
+
[18]: ad: 0x7ffff71056d2, op: 109
|
| 102 |
+
[18]: ad: 0x7ffff71056d5, op: 319
|
| 103 |
+
new bb detected: 19
|
| 104 |
+
[19]: ad: 0x7ffff71056db, op: 427
|
| 105 |
+
[19]: ad: 0x7ffff71056de, op: 847
|
| 106 |
+
[19]: ad: 0x7ffff71056e2, op: 325
|
| 107 |
+
new bb detected: 20
|
| 108 |
+
[20]: ad: 0x7ffff71056e8, op: 109
|
| 109 |
+
[20]: ad: 0x7ffff71056ec, op: 311
|
| 110 |
+
new bb detected: 21
|
| 111 |
+
[21]: ad: 0x7ffff71056f2, op: 31
|
| 112 |
+
[21]: ad: 0x7ffff71056f5, op: 325
|
| 113 |
+
new bb detected: 22
|
| 114 |
+
[22]: ad: 0x7ffff71056fb, op: 427
|
| 115 |
+
[22]: ad: 0x7ffff7105702, op: 427
|
| 116 |
+
[22]: ad: 0x7ffff7105705, op: 427
|
| 117 |
+
[22]: ad: 0x7ffff7105709, op: 847
|
| 118 |
+
[22]: ad: 0x7ffff710570c, op: 330
|
| 119 |
+
new bb detected: 23
|
| 120 |
+
[23]: ad: 0x7ffff710570e, op: 388
|
| 121 |
+
[23]: ad: 0x7ffff7105712, op: 799
|
| 122 |
+
[23]: ad: 0x7ffff7105716, op: 109
|
| 123 |
+
[23]: ad: 0x7ffff710571d, op: 311
|
| 124 |
+
new bb detected: 24
|
| 125 |
+
[24]: ad: 0x7ffff710571f, op: 427
|
| 126 |
+
[24]: ad: 0x7ffff7105726, op: 427
|
| 127 |
+
[24]: ad: 0x7ffff710572d, op: 388
|
| 128 |
+
[24]: ad: 0x7ffff7105731, op: 109
|
| 129 |
+
[24]: ad: 0x7ffff7105735, op: 330
|
| 130 |
+
new bb detected: 25
|
| 131 |
+
[25]: ad: 0x7ffff710573b, op: 468
|
| 132 |
+
[25]: ad: 0x7ffff710573f, op: 427
|
| 133 |
+
[25]: ad: 0x7ffff7105742, op: 109
|
| 134 |
+
[25]: ad: 0x7ffff7105745, op: 310
|
| 135 |
+
new bb detected: 26
|
| 136 |
+
[26]: ad: 0x7ffff7105a00, op: 427
|
| 137 |
+
[26]: ad: 0x7ffff7105a07, op: 8
|
| 138 |
+
[26]: ad: 0x7ffff7105a0a, op: 427
|
| 139 |
+
[26]: ad: 0x7ffff7105a0e, op: 427
|
| 140 |
+
[26]: ad: 0x7ffff7105a11, op: 799
|
| 141 |
+
[26]: ad: 0x7ffff7105a15, op: 1723
|
| 142 |
+
[26]: ad: 0x7ffff7105a1d, op: 427
|
| 143 |
+
[26]: ad: 0x7ffff7105a21, op: 427
|
| 144 |
+
[26]: ad: 0x7ffff7105a29, op: 427
|
| 145 |
+
[26]: ad: 0x7ffff7105a2d, op: 316
|
| 146 |
+
new bb detected: 27
|
| 147 |
+
[27]: ad: 0x7ffff71057e8, op: 427
|
| 148 |
+
[27]: ad: 0x7ffff71057ed, op: 826
|
| 149 |
+
[27]: ad: 0x7ffff71057f6, op: 325
|
| 150 |
+
new bb detected: 28
|
| 151 |
+
[28]: ad: 0x7ffff71057fc, op: 8
|
| 152 |
+
[28]: ad: 0x7ffff7105800, op: 616
|
| 153 |
+
[28]: ad: 0x7ffff7105801, op: 616
|
| 154 |
+
[28]: ad: 0x7ffff7105802, op: 616
|
| 155 |
+
[28]: ad: 0x7ffff7105804, op: 616
|
| 156 |
+
[28]: ad: 0x7ffff7105806, op: 616
|
| 157 |
+
[28]: ad: 0x7ffff7105808, op: 616
|
| 158 |
+
[28]: ad: 0x7ffff710580a, op: 740
|
| 159 |
+
new bb detected: 29
|
| 160 |
+
[29]: ad: 0x7ffff7108453, op: 427
|
| 161 |
+
[29]: ad: 0x7ffff7108456, op: 8
|
| 162 |
+
[29]: ad: 0x7ffff710845a, op: 616
|
| 163 |
+
[29]: ad: 0x7ffff710845b, op: 616
|
| 164 |
+
[29]: ad: 0x7ffff710845c, op: 740
|
| 165 |
+
new bb detected: 30
|
| 166 |
+
[30]: ad: 0x7ffff3d8e5aa, op: 427
|
| 167 |
+
[30]: ad: 0x7ffff3d8e5ae, op: 847
|
| 168 |
+
[30]: ad: 0x7ffff3d8e5b1, op: 330
|
| 169 |
+
new bb detected: 31
|
| 170 |
+
[31]: ad: 0x7ffff3d8e5b3, op: 75
|
| 171 |
+
new bb detected: 32
|
| 172 |
+
[32]: ad: 0x7ffff3d8e5b8, op: 427
|
| 173 |
+
[32]: ad: 0x7ffff3d8e5bb, op: 75
|
| 174 |
+
new bb detected: 33
|
| 175 |
+
[33]: ad: 0x7ffff710574b, op: 109
|
| 176 |
+
[33]: ad: 0x7ffff7105752, op: 319
|
| 177 |
+
new bb detected: 34
|
| 178 |
+
[34]: ad: 0x7ffff7105758, op: 388
|
| 179 |
+
[34]: ad: 0x7ffff710575d, op: 427
|
| 180 |
+
[34]: ad: 0x7ffff7105761, op: 109
|
| 181 |
+
[34]: ad: 0x7ffff7105765, op: 311
|
| 182 |
+
new bb detected: 35
|
| 183 |
+
[35]: ad: 0x7ffff710576b, op: 31
|
| 184 |
+
[35]: ad: 0x7ffff710576f, op: 109
|
| 185 |
+
[35]: ad: 0x7ffff7105777, op: 318
|
| 186 |
+
new bb detected: 36
|
| 187 |
+
[36]: ad: 0x7ffff710577d, op: 427
|
| 188 |
+
[36]: ad: 0x7ffff7105783, op: 847
|
| 189 |
+
[36]: ad: 0x7ffff7105785, op: 325
|
| 190 |
+
new bb detected: 37
|
| 191 |
+
[37]: ad: 0x7ffff710578b, op: 427
|
| 192 |
+
[37]: ad: 0x7ffff7105794, op: 799
|
| 193 |
+
[37]: ad: 0x7ffff7105797, op: 388
|
| 194 |
+
[37]: ad: 0x7ffff710579a, op: 8
|
| 195 |
+
[37]: ad: 0x7ffff710579e, op: 427
|
| 196 |
+
[37]: ad: 0x7ffff71057a2, op: 427
|
| 197 |
+
[37]: ad: 0x7ffff71057aa, op: 847
|
| 198 |
+
[37]: ad: 0x7ffff71057ac, op: 325
|
| 199 |
+
new bb detected: 38
|
| 200 |
+
[38]: ad: 0x7ffff71057b2, op: 109
|
| 201 |
+
[38]: ad: 0x7ffff71057b5, op: 330
|
| 202 |
+
new bb detected: 39
|
| 203 |
+
[39]: ad: 0x7ffff71057bb, op: 388
|
| 204 |
+
[39]: ad: 0x7ffff71057bf, op: 799
|
| 205 |
+
[39]: ad: 0x7ffff71057c3, op: 1723
|
| 206 |
+
[39]: ad: 0x7ffff71057c6, op: 427
|
| 207 |
+
[39]: ad: 0x7ffff71057ca, op: 427
|
| 208 |
+
[39]: ad: 0x7ffff71057ce, op: 847
|
| 209 |
+
[39]: ad: 0x7ffff71057d1, op: 330
|
| 210 |
+
new bb detected: 40
|
| 211 |
+
[40]: ad: 0x7ffff71057d3, op: 31
|
| 212 |
+
[40]: ad: 0x7ffff71057d7, op: 330
|
| 213 |
+
new bb detected: 41
|
| 214 |
+
[41]: ad: 0x7ffff3d8e5c0, op: 427
|
| 215 |
+
[41]: ad: 0x7ffff3d8e5c3, op: 109
|
| 216 |
+
[41]: ad: 0x7ffff3d8e5c6, op: 325
|
| 217 |
+
new bb detected: 42
|
| 218 |
+
[42]: ad: 0x7ffff3d8e569, op: 427
|
| 219 |
+
[42]: ad: 0x7ffff3d8e56d, op: 826
|
| 220 |
+
[42]: ad: 0x7ffff3d8e572, op: 427
|
| 221 |
+
[42]: ad: 0x7ffff3d8e575, op: 75
|
| 222 |
+
new bb detected: 43
|
| 223 |
+
[43]: ad: 0x7ffff3d8d300, op: 482
|
| 224 |
+
[43]: ad: 0x7ffff3d8d304, op: 316
|
| 225 |
+
new bb detected: 44
|
| 226 |
+
[44]: ad: 0x7ffff734bdb0, op: 482
|
| 227 |
+
[44]: ad: 0x7ffff734bdb4, op: 427
|
| 228 |
+
[44]: ad: 0x7ffff734bdb7, op: 427
|
| 229 |
+
[44]: ad: 0x7ffff734bdbb, op: 427
|
| 230 |
+
[44]: ad: 0x7ffff734bdbe, op: 427
|
| 231 |
+
[44]: ad: 0x7ffff734bdc2, op: 740
|
| 232 |
+
new bb detected: 45
|
| 233 |
+
[45]: ad: 0x7ffff3d8e57a, op: 427
|
| 234 |
+
[45]: ad: 0x7ffff3d8e57d, op: 75
|
| 235 |
+
new bb detected: 46
|
| 236 |
+
[46]: ad: 0x7ffff3d8e582, op: 427
|
| 237 |
+
[46]: ad: 0x7ffff3d8e585, op: 427
|
| 238 |
+
[46]: ad: 0x7ffff3d8e588, op: 427
|
| 239 |
+
[46]: ad: 0x7ffff3d8e58b, op: 427
|
| 240 |
+
[46]: ad: 0x7ffff3d8e58e, op: 427
|
| 241 |
+
[46]: ad: 0x7ffff3d8e591, op: 75
|
| 242 |
+
new bb detected: 47
|
| 243 |
+
[47]: ad: 0x7ffff3d8e3c0, op: 482
|
| 244 |
+
[47]: ad: 0x7ffff3d8e3c4, op: 671
|
| 245 |
+
[47]: ad: 0x7ffff3d8e3c6, op: 671
|
| 246 |
+
[47]: ad: 0x7ffff3d8e3c8, op: 671
|
| 247 |
+
[47]: ad: 0x7ffff3d8e3ca, op: 671
|
| 248 |
+
[47]: ad: 0x7ffff3d8e3cc, op: 671
|
| 249 |
+
[47]: ad: 0x7ffff3d8e3cd, op: 427
|
| 250 |
+
[47]: ad: 0x7ffff3d8e3d0, op: 671
|
| 251 |
+
[47]: ad: 0x7ffff3d8e3d1, op: 826
|
| 252 |
+
[47]: ad: 0x7ffff3d8e3d5, op: 427
|
| 253 |
+
[47]: ad: 0x7ffff3d8e3d9, op: 427
|
| 254 |
+
[47]: ad: 0x7ffff3d8e3dd, op: 465
|
| 255 |
+
[47]: ad: 0x7ffff3d8e3e1, op: 109
|
| 256 |
+
[47]: ad: 0x7ffff3d8e3e5, op: 330
|
| 257 |
+
new bb detected: 48
|
| 258 |
+
[48]: ad: 0x7ffff3d8e3eb, op: 427
|
| 259 |
+
[48]: ad: 0x7ffff3d8e3f1, op: 109
|
| 260 |
+
[48]: ad: 0x7ffff3d8e3f4, op: 315
|
| 261 |
+
new bb detected: 49
|
| 262 |
+
[49]: ad: 0x7ffff3d8e43f, op: 427
|
| 263 |
+
[49]: ad: 0x7ffff3d8e444, op: 75
|
| 264 |
+
new bb detected: 50
|
| 265 |
+
[50]: ad: 0x7ffff3d8d280, op: 482
|
| 266 |
+
[50]: ad: 0x7ffff3d8d284, op: 316
|
| 267 |
+
new bb detected: 51
|
| 268 |
+
[51]: ad: 0x7ffff733a970, op: 482
|
| 269 |
+
[51]: ad: 0x7ffff733a974, op: 847
|
| 270 |
+
[51]: ad: 0x7ffff733a977, op: 427
|
| 271 |
+
[51]: ad: 0x7ffff733a97c, op: 671
|
| 272 |
+
[51]: ad: 0x7ffff733a97d, op: 104
|
| 273 |
+
[51]: ad: 0x7ffff733a981, op: 427
|
| 274 |
+
[51]: ad: 0x7ffff733a984, op: 427
|
| 275 |
+
[51]: ad: 0x7ffff733a987, op: 75
|
| 276 |
+
new bb detected: 52
|
| 277 |
+
[52]: ad: 0x7ffff732b0d0, op: 482
|
| 278 |
+
[52]: ad: 0x7ffff732b0d4, op: 316
|
| 279 |
+
new bb detected: 53
|
| 280 |
+
[53]: ad: 0x7ffff71080a0, op: 482
|
| 281 |
+
[53]: ad: 0x7ffff71080a4, op: 671
|
| 282 |
+
[53]: ad: 0x7ffff71080a6, op: 671
|
| 283 |
+
[53]: ad: 0x7ffff71080a7, op: 427
|
| 284 |
+
[53]: ad: 0x7ffff71080aa, op: 671
|
| 285 |
+
[53]: ad: 0x7ffff71080ab, op: 826
|
| 286 |
+
[53]: ad: 0x7ffff71080af, op: 109
|
| 287 |
+
[53]: ad: 0x7ffff71080b6, op: 330
|
| 288 |
+
new bb detected: 54
|
| 289 |
+
[54]: ad: 0x7ffff71080bc, op: 847
|
| 290 |
+
[54]: ad: 0x7ffff71080bf, op: 329
|
| 291 |
+
new bb detected: 55
|
| 292 |
+
[55]: ad: 0x7ffff71080c5, op: 388
|
| 293 |
+
[55]: ad: 0x7ffff71080c9, op: 1723
|
| 294 |
+
[55]: ad: 0x7ffff71080cc, op: 109
|
| 295 |
+
[55]: ad: 0x7ffff71080d0, op: 319
|
| 296 |
+
new bb detected: 56
|
| 297 |
+
[56]: ad: 0x7ffff71081b0, op: 31
|
| 298 |
+
[56]: ad: 0x7ffff71081b4, op: 388
|
| 299 |
+
[56]: ad: 0x7ffff71081b8, op: 799
|
| 300 |
+
[56]: ad: 0x7ffff71081bc, op: 316
|
| 301 |
+
new bb detected: 57
|
| 302 |
+
[57]: ad: 0x7ffff71080d6, op: 427
|
| 303 |
+
[57]: ad: 0x7ffff71080dd, op: 427
|
| 304 |
+
[57]: ad: 0x7ffff71080e1, op: 847
|
| 305 |
+
[57]: ad: 0x7ffff71080e4, op: 330
|
| 306 |
+
new bb detected: 58
|
| 307 |
+
[58]: ad: 0x7ffff71080ea, op: 109
|
| 308 |
+
[58]: ad: 0x7ffff71080f1, op: 319
|
| 309 |
+
new bb detected: 59
|
| 310 |
+
[59]: ad: 0x7ffff7108200, op: 468
|
| 311 |
+
[59]: ad: 0x7ffff7108205, op: 847
|
| 312 |
+
[59]: ad: 0x7ffff7108208, op: 330
|
| 313 |
+
new bb detected: 60
|
| 314 |
+
[60]: ad: 0x7ffff710820e, op: 388
|
| 315 |
+
[60]: ad: 0x7ffff7108213, op: 427
|
| 316 |
+
[60]: ad: 0x7ffff7108217, op: 847
|
| 317 |
+
[60]: ad: 0x7ffff7108219, op: 325
|
| 318 |
+
new bb detected: 61
|
| 319 |
+
[61]: ad: 0x7ffff710821f, op: 427
|
| 320 |
+
[61]: ad: 0x7ffff7108222, op: 826
|
| 321 |
+
[61]: ad: 0x7ffff7108225, op: 799
|
| 322 |
+
[61]: ad: 0x7ffff7108229, op: 1723
|
| 323 |
+
[61]: ad: 0x7ffff710822c, op: 427
|
| 324 |
+
[61]: ad: 0x7ffff7108230, op: 427
|
| 325 |
+
[61]: ad: 0x7ffff7108235, op: 427
|
| 326 |
+
[61]: ad: 0x7ffff710823d, op: 8
|
| 327 |
+
[61]: ad: 0x7ffff7108241, op: 616
|
| 328 |
+
[61]: ad: 0x7ffff7108242, op: 616
|
| 329 |
+
[61]: ad: 0x7ffff7108243, op: 616
|
| 330 |
+
[61]: ad: 0x7ffff7108245, op: 740
|
| 331 |
+
new bb detected: 62
|
| 332 |
+
[62]: ad: 0x7ffff733a98c, op: 847
|
| 333 |
+
[62]: ad: 0x7ffff733a98f, op: 330
|
| 334 |
+
new bb detected: 63
|
| 335 |
+
[63]: ad: 0x7ffff733a991, op: 616
|
| 336 |
+
[63]: ad: 0x7ffff733a992, op: 740
|
| 337 |
+
new bb detected: 64
|
| 338 |
+
[64]: ad: 0x7ffff3d8e449, op: 427
|
| 339 |
+
[64]: ad: 0x7ffff3d8e44c, op: 427
|
| 340 |
+
[64]: ad: 0x7ffff3d8e44f, op: 427
|
| 341 |
+
[64]: ad: 0x7ffff3d8e452, op: 75
|
| 342 |
+
new bb detected: 65
|
| 343 |
+
[65]: ad: 0x7ffff3d8de30, op: 482
|
| 344 |
+
[65]: ad: 0x7ffff3d8de34, op: 671
|
| 345 |
+
[65]: ad: 0x7ffff3d8de36, op: 678
|
| 346 |
+
[65]: ad: 0x7ffff3d8de3a, op: 671
|
| 347 |
+
[65]: ad: 0x7ffff3d8de3b, op: 427
|
| 348 |
+
[65]: ad: 0x7ffff3d8de3e, op: 671
|
| 349 |
+
[65]: ad: 0x7ffff3d8de3f, op: 427
|
| 350 |
+
[65]: ad: 0x7ffff3d8de43, op: 427
|
| 351 |
+
[65]: ad: 0x7ffff3d8de46, op: 826
|
| 352 |
+
[65]: ad: 0x7ffff3d8de49, op: 427
|
| 353 |
+
[65]: ad: 0x7ffff3d8de51, op: 467
|
| 354 |
+
[65]: ad: 0x7ffff3d8de54, op: 330
|
| 355 |
+
new bb detected: 66
|
| 356 |
+
[66]: ad: 0x7ffff3d8de5a, op: 427
|
| 357 |
+
[66]: ad: 0x7ffff3d8de64, op: 427
|
| 358 |
+
[66]: ad: 0x7ffff3d8de67, op: 109
|
| 359 |
+
[66]: ad: 0x7ffff3d8de6a, op: 319
|
| 360 |
+
new bb detected: 67
|
| 361 |
+
[67]: ad: 0x7ffff3d8de70, op: 427
|
| 362 |
+
[67]: ad: 0x7ffff3d8de73, op: 75
|
| 363 |
+
new bb detected: 68
|
| 364 |
+
[68]: ad: 0x7ffff3d8de78, op: 427
|
| 365 |
+
[68]: ad: 0x7ffff3d8de7b, op: 454
|
| 366 |
+
[68]: ad: 0x7ffff3d8de80, op: 8
|
| 367 |
+
[68]: ad: 0x7ffff3d8de83, op: 669
|
| 368 |
+
[68]: ad: 0x7ffff3d8de87, op: 427
|
| 369 |
+
[68]: ad: 0x7ffff3d8de8b, op: 467
|
| 370 |
+
[68]: ad: 0x7ffff3d8de8e, op: 427
|
| 371 |
+
[68]: ad: 0x7ffff3d8de92, op: 427
|
| 372 |
+
[68]: ad: 0x7ffff3d8de96, op: 427
|
| 373 |
+
[68]: ad: 0x7ffff3d8de99, op: 826
|
| 374 |
+
[68]: ad: 0x7ffff3d8de9c, op: 109
|
| 375 |
+
[68]: ad: 0x7ffff3d8de9f, op: 330
|
| 376 |
+
new bb detected: 69
|
| 377 |
+
[69]: ad: 0x7ffff3d8dea1, op: 427
|
| 378 |
+
[69]: ad: 0x7ffff3d8dea4, op: 427
|
| 379 |
+
[69]: ad: 0x7ffff3d8dea7, op: 75
|
| 380 |
+
new bb detected: 70
|
| 381 |
+
[70]: ad: 0x7ffff3d8d2f0, op: 482
|
| 382 |
+
[70]: ad: 0x7ffff3d8d2f4, op: 316
|
| 383 |
+
new bb detected: 71
|
| 384 |
+
[71]: ad: 0x7ffff72037f0, op: 482
|
| 385 |
+
[71]: ad: 0x7ffff72037f4, op: 427
|
| 386 |
+
[71]: ad: 0x7ffff72037f7, op: 109
|
| 387 |
+
[71]: ad: 0x7ffff72037fb, op: 310
|
| 388 |
+
new bb detected: 72
|
| 389 |
+
[72]: ad: 0x7ffff7203801, op: 1232
|
| 390 |
+
[72]: ad: 0x7ffff7203805, op: 109
|
| 391 |
+
[72]: ad: 0x7ffff7203809, op: 319
|
| 392 |
+
new bb detected: 73
|
| 393 |
+
[73]: ad: 0x7ffff720380f, op: 1232
|
| 394 |
+
[73]: ad: 0x7ffff7203815, op: 1232
|
| 395 |
+
[73]: ad: 0x7ffff7203819, op: 1232
|
| 396 |
+
[73]: ad: 0x7ffff720381f, op: 1704
|
| 397 |
+
[73]: ad: 0x7ffff7203822, op: 740
|
| 398 |
+
new bb detected: 74
|
| 399 |
+
[74]: ad: 0x7ffff3d8deac, op: 427
|
| 400 |
+
[74]: ad: 0x7ffff3d8deaf, op: 8
|
| 401 |
+
[74]: ad: 0x7ffff3d8deb2, op: 678
|
| 402 |
+
[74]: ad: 0x7ffff3d8deb6, op: 427
|
| 403 |
+
[74]: ad: 0x7ffff3d8deba, op: 427
|
| 404 |
+
[74]: ad: 0x7ffff3d8debe, op: 826
|
| 405 |
+
[74]: ad: 0x7ffff3d8dec2, op: 427
|
| 406 |
+
[74]: ad: 0x7ffff3d8deca, op: 467
|
| 407 |
+
[74]: ad: 0x7ffff3d8dece, op: 330
|
| 408 |
+
new bb detected: 75
|
| 409 |
+
[75]: ad: 0x7ffff3d8ded4, op: 427
|
| 410 |
+
[75]: ad: 0x7ffff3d8dede, op: 427
|
| 411 |
+
[75]: ad: 0x7ffff3d8dee1, op: 109
|
| 412 |
+
[75]: ad: 0x7ffff3d8dee4, op: 319
|
| 413 |
+
new bb detected: 76
|
| 414 |
+
[76]: ad: 0x7ffff3d8deea, op: 427
|
| 415 |
+
[76]: ad: 0x7ffff3d8deed, op: 75
|
| 416 |
+
new bb detected: 77
|
| 417 |
+
[77]: ad: 0x7ffff3d8def2, op: 427
|
| 418 |
+
[77]: ad: 0x7ffff3d8def5, op: 454
|
| 419 |
+
[77]: ad: 0x7ffff3d8defa, op: 8
|
| 420 |
+
[77]: ad: 0x7ffff3d8defd, op: 669
|
| 421 |
+
[77]: ad: 0x7ffff3d8df01, op: 427
|
| 422 |
+
[77]: ad: 0x7ffff3d8df05, op: 467
|
| 423 |
+
[77]: ad: 0x7ffff3d8df09, op: 427
|
| 424 |
+
[77]: ad: 0x7ffff3d8df0d, op: 427
|
| 425 |
+
[77]: ad: 0x7ffff3d8df11, op: 427
|
| 426 |
+
[77]: ad: 0x7ffff3d8df14, op: 826
|
| 427 |
+
[77]: ad: 0x7ffff3d8df17, op: 109
|
| 428 |
+
[77]: ad: 0x7ffff3d8df1a, op: 330
|
| 429 |
+
new bb detected: 78
|
| 430 |
+
[78]: ad: 0x7ffff3d8df1c, op: 427
|
| 431 |
+
[78]: ad: 0x7ffff3d8df1f, op: 427
|
| 432 |
+
[78]: ad: 0x7ffff3d8df22, op: 75
|
| 433 |
+
new bb detected: 79
|
| 434 |
+
[79]: ad: 0x7ffff3d8df27, op: 427
|
| 435 |
+
[79]: ad: 0x7ffff3d8df2a, op: 427
|
| 436 |
+
[79]: ad: 0x7ffff3d8df2e, op: 8
|
| 437 |
+
[79]: ad: 0x7ffff3d8df31, op: 427
|
| 438 |
+
[79]: ad: 0x7ffff3d8df35, op: 427
|
| 439 |
+
[79]: ad: 0x7ffff3d8df39, op: 616
|
| 440 |
+
[79]: ad: 0x7ffff3d8df3a, op: 616
|
| 441 |
+
[79]: ad: 0x7ffff3d8df3b, op: 616
|
| 442 |
+
[79]: ad: 0x7ffff3d8df3d, op: 740
|
| 443 |
+
new bb detected: 80
|
| 444 |
+
[80]: ad: 0x7ffff3d8e457, op: 427
|
| 445 |
+
[80]: ad: 0x7ffff3d8e45a, op: 826
|
| 446 |
+
[80]: ad: 0x7ffff3d8e45e, op: 427
|
| 447 |
+
[80]: ad: 0x7ffff3d8e461, op: 8
|
| 448 |
+
[80]: ad: 0x7ffff3d8e465, op: 756
|
| 449 |
+
[80]: ad: 0x7ffff3d8e469, op: 75
|
| 450 |
+
new bb detected: 81
|
| 451 |
+
[81]: ad: 0x7ffff3d8e2d0, op: 482
|
| 452 |
+
[81]: ad: 0x7ffff3d8e2d4, op: 671
|
| 453 |
+
[81]: ad: 0x7ffff3d8e2d5, op: 671
|
| 454 |
+
[81]: ad: 0x7ffff3d8e2d6, op: 826
|
| 455 |
+
[81]: ad: 0x7ffff3d8e2da, op: 427
|
| 456 |
+
[81]: ad: 0x7ffff3d8e2dd, op: 427
|
| 457 |
+
[81]: ad: 0x7ffff3d8e2e6, op: 427
|
| 458 |
+
[81]: ad: 0x7ffff3d8e2eb, op: 1723
|
| 459 |
+
[81]: ad: 0x7ffff3d8e2ed, op: 847
|
| 460 |
+
[81]: ad: 0x7ffff3d8e2ef, op: 315
|
| 461 |
+
new bb detected: 82
|
| 462 |
+
[82]: ad: 0x7ffff3d8e2f5, op: 427
|
| 463 |
+
[82]: ad: 0x7ffff3d8e2f9, op: 465
|
| 464 |
+
[82]: ad: 0x7ffff3d8e2fc, op: 427
|
| 465 |
+
[82]: ad: 0x7ffff3d8e2ff, op: 8
|
| 466 |
+
[82]: ad: 0x7ffff3d8e302, op: 388
|
| 467 |
+
[82]: ad: 0x7ffff3d8e30a, op: 427
|
| 468 |
+
[82]: ad: 0x7ffff3d8e30e, op: 427
|
| 469 |
+
[82]: ad: 0x7ffff3d8e315, op: 431
|
| 470 |
+
[82]: ad: 0x7ffff3d8e319, op: 465
|
| 471 |
+
[82]: ad: 0x7ffff3d8e31d, op: 8
|
| 472 |
+
[82]: ad: 0x7ffff3d8e320, op: 465
|
| 473 |
+
[82]: ad: 0x7ffff3d8e323, op: 427
|
| 474 |
+
[82]: ad: 0x7ffff3d8e327, op: 427
|
| 475 |
+
[82]: ad: 0x7ffff3d8e32a, op: 8
|
| 476 |
+
[82]: ad: 0x7ffff3d8e32e, op: 427
|
| 477 |
+
[82]: ad: 0x7ffff3d8e333, op: 431
|
| 478 |
+
[82]: ad: 0x7ffff3d8e337, op: 668
|
| 479 |
+
[82]: ad: 0x7ffff3d8e33b, op: 454
|
| 480 |
+
[82]: ad: 0x7ffff3d8e340, op: 109
|
| 481 |
+
[82]: ad: 0x7ffff3d8e344, op: 330
|
| 482 |
+
new bb detected: 83
|
| 483 |
+
[83]: ad: 0x7ffff3d8e380, op: 427
|
| 484 |
+
[83]: ad: 0x7ffff3d8e383, op: 388
|
| 485 |
+
[83]: ad: 0x7ffff3d8e388, op: 427
|
| 486 |
+
[83]: ad: 0x7ffff3d8e38b, op: 75
|
| 487 |
+
new bb detected: 84
|
| 488 |
+
[84]: ad: 0x7ffff3d8e750, op: 482
|
| 489 |
+
[84]: ad: 0x7ffff3d8e754, op: 671
|
| 490 |
+
[84]: ad: 0x7ffff3d8e756, op: 427
|
| 491 |
+
[84]: ad: 0x7ffff3d8e759, op: 427
|
| 492 |
+
[84]: ad: 0x7ffff3d8e763, op: 671
|
| 493 |
+
[84]: ad: 0x7ffff3d8e765, op: 671
|
| 494 |
+
[84]: ad: 0x7ffff3d8e767, op: 671
|
| 495 |
+
[84]: ad: 0x7ffff3d8e769, op: 671
|
| 496 |
+
[84]: ad: 0x7ffff3d8e76a, op: 671
|
| 497 |
+
[84]: ad: 0x7ffff3d8e76b, op: 826
|
| 498 |
+
[84]: ad: 0x7ffff3d8e76f, op: 427
|
| 499 |
+
[84]: ad: 0x7ffff3d8e773, op: 427
|
| 500 |
+
[84]: ad: 0x7ffff3d8e776, op: 427
|
| 501 |
+
[84]: ad: 0x7ffff3d8e779, op: 826
|
| 502 |
+
[84]: ad: 0x7ffff3d8e77c, op: 756
|
| 503 |
+
[84]: ad: 0x7ffff3d8e780, op: 109
|
| 504 |
+
[84]: ad: 0x7ffff3d8e783, op: 330
|
| 505 |
+
new bb detected: 85
|
| 506 |
+
[85]: ad: 0x7ffff3d8e789, op: 847
|
| 507 |
+
[85]: ad: 0x7ffff3d8e78c, op: 427
|
| 508 |
+
[85]: ad: 0x7ffff3d8e791, op: 427
|
| 509 |
+
[85]: ad: 0x7ffff3d8e794, op: 427
|
| 510 |
+
[85]: ad: 0x7ffff3d8e797, op: 104
|
| 511 |
+
[85]: ad: 0x7ffff3d8e79b, op: 1723
|
| 512 |
+
[85]: ad: 0x7ffff3d8e79d, op: 8
|
| 513 |
+
[85]: ad: 0x7ffff3d8e7a0, op: 427
|
| 514 |
+
[85]: ad: 0x7ffff3d8e7a3, op: 770
|
| 515 |
+
[85]: ad: 0x7ffff3d8e7a6, op: 826
|
| 516 |
+
[85]: ad: 0x7ffff3d8e7a9, op: 847
|
| 517 |
+
[85]: ad: 0x7ffff3d8e7ac, op: 325
|
| 518 |
+
new bb detected: 86
|
| 519 |
+
[86]: ad: 0x7ffff3d8e7b2, op: 847
|
| 520 |
+
[86]: ad: 0x7ffff3d8e7b5, op: 325
|
| 521 |
+
new bb detected: 87
|
| 522 |
+
[87]: ad: 0x7ffff3d8e870, op: 427
|
| 523 |
+
[87]: ad: 0x7ffff3d8e87a, op: 109
|
| 524 |
+
[87]: ad: 0x7ffff3d8e87d, op: 98
|
| 525 |
+
[87]: ad: 0x7ffff3d8e881, op: 388
|
| 526 |
+
[87]: ad: 0x7ffff3d8e889, op: 316
|
| 527 |
+
new bb detected: 88
|
| 528 |
+
[88]: ad: 0x7ffff3d8e852, op: 427
|
| 529 |
+
[88]: ad: 0x7ffff3d8e855, op: 427
|
| 530 |
+
[88]: ad: 0x7ffff3d8e859, op: 75
|
| 531 |
+
new bb detected: 89
|
| 532 |
+
[89]: ad: 0x7ffff3d8e85e, op: 427
|
| 533 |
+
[89]: ad: 0x7ffff3d8e862, op: 427
|
| 534 |
+
[89]: ad: 0x7ffff3d8e865, op: 8
|
| 535 |
+
[89]: ad: 0x7ffff3d8e868, op: 316
|
| 536 |
+
new bb detected: 90
|
| 537 |
+
[90]: ad: 0x7ffff3d8e7bf, op: 427
|
| 538 |
+
[90]: ad: 0x7ffff3d8e7c2, op: 826
|
| 539 |
+
[90]: ad: 0x7ffff3d8e7c5, op: 388
|
| 540 |
+
[90]: ad: 0x7ffff3d8e7ca, op: 454
|
| 541 |
+
[90]: ad: 0x7ffff3d8e7cf, op: 427
|
| 542 |
+
[90]: ad: 0x7ffff3d8e7d2, op: 388
|
| 543 |
+
[90]: ad: 0x7ffff3d8e7d6, op: 454
|
| 544 |
+
[90]: ad: 0x7ffff3d8e7db, op: 669
|
| 545 |
+
[90]: ad: 0x7ffff3d8e7df, op: 429
|
| 546 |
+
[90]: ad: 0x7ffff3d8e7e3, op: 847
|
| 547 |
+
[90]: ad: 0x7ffff3d8e7e6, op: 321
|
| 548 |
+
new bb detected: 91
|
| 549 |
+
[91]: ad: 0x7ffff3d8e810, op: 427
|
| 550 |
+
[91]: ad: 0x7ffff3d8e813, op: 75
|
| 551 |
+
new bb detected: 92
|
| 552 |
+
[92]: ad: 0x7ffff3d8e818, op: 847
|
| 553 |
+
[92]: ad: 0x7ffff3d8e81b, op: 321
|
| 554 |
+
new bb detected: 93
|
| 555 |
+
[93]: ad: 0x7ffff3d8e81d, op: 427
|
| 556 |
+
[93]: ad: 0x7ffff3d8e820, op: 75
|
| 557 |
+
new bb detected: 94
|
| 558 |
+
[94]: ad: 0x7ffff3d8e825, op: 316
|
| 559 |
+
new bb detected: 95
|
| 560 |
+
[95]: ad: 0x7ffff3d8e7f2, op: 436
|
| 561 |
+
[95]: ad: 0x7ffff3d8e7f7, op: 427
|
| 562 |
+
[95]: ad: 0x7ffff3d8e7fb, op: 467
|
| 563 |
+
[95]: ad: 0x7ffff3d8e7ff, op: 8
|
| 564 |
+
[95]: ad: 0x7ffff3d8e803, op: 616
|
| 565 |
+
[95]: ad: 0x7ffff3d8e804, op: 616
|
| 566 |
+
[95]: ad: 0x7ffff3d8e805, op: 616
|
| 567 |
+
[95]: ad: 0x7ffff3d8e807, op: 616
|
| 568 |
+
[95]: ad: 0x7ffff3d8e809, op: 616
|
| 569 |
+
[95]: ad: 0x7ffff3d8e80b, op: 616
|
| 570 |
+
[95]: ad: 0x7ffff3d8e80d, op: 740
|
| 571 |
+
new bb detected: 96
|
| 572 |
+
[96]: ad: 0x7ffff3d8e390, op: 427
|
| 573 |
+
[96]: ad: 0x7ffff3d8e394, op: 8
|
| 574 |
+
[96]: ad: 0x7ffff3d8e397, op: 316
|
| 575 |
+
new bb detected: 97
|
| 576 |
+
[97]: ad: 0x7ffff3d8e351, op: 427
|
| 577 |
+
[97]: ad: 0x7ffff3d8e355, op: 427
|
| 578 |
+
[97]: ad: 0x7ffff3d8e358, op: 826
|
| 579 |
+
[97]: ad: 0x7ffff3d8e35c, op: 427
|
| 580 |
+
[97]: ad: 0x7ffff3d8e35e, op: 427
|
| 581 |
+
[97]: ad: 0x7ffff3d8e362, op: 427
|
| 582 |
+
[97]: ad: 0x7ffff3d8e367, op: 826
|
| 583 |
+
[97]: ad: 0x7ffff3d8e370, op: 325
|
| 584 |
+
new bb detected: 98
|
| 585 |
+
[98]: ad: 0x7ffff3d8e372, op: 8
|
| 586 |
+
[98]: ad: 0x7ffff3d8e376, op: 616
|
| 587 |
+
[98]: ad: 0x7ffff3d8e377, op: 616
|
| 588 |
+
[98]: ad: 0x7ffff3d8e378, op: 740
|
| 589 |
+
new bb detected: 99
|
| 590 |
+
[99]: ad: 0x7ffff3d8e46e, op: 427
|
| 591 |
+
[99]: ad: 0x7ffff3d8e471, op: 427
|
| 592 |
+
[99]: ad: 0x7ffff3d8e476, op: 427
|
| 593 |
+
[99]: ad: 0x7ffff3d8e47b, op: 75
|
| 594 |
+
new bb detected: 100
|
| 595 |
+
[100]: ad: 0x7ffff3d8e480, op: 427
|
| 596 |
+
[100]: ad: 0x7ffff3d8e485, op: 427
|
| 597 |
+
[100]: ad: 0x7ffff3d8e489, op: 427
|
| 598 |
+
[100]: ad: 0x7ffff3d8e48c, op: 75
|
| 599 |
+
new bb detected: 101
|
| 600 |
+
[101]: ad: 0x7ffff3d8d1e0, op: 482
|
| 601 |
+
[101]: ad: 0x7ffff3d8d1e4, op: 316
|
| 602 |
+
new bb detected: 102
|
| 603 |
+
[102]: ad: 0x7ffff734bd80, op: 482
|
| 604 |
+
[102]: ad: 0x7ffff734bd84, op: 427
|
| 605 |
+
[102]: ad: 0x7ffff734bd88, op: 454
|
| 606 |
+
[102]: ad: 0x7ffff734bd8d, op: 454
|
| 607 |
+
[102]: ad: 0x7ffff734bd92, op: 669
|
| 608 |
+
[102]: ad: 0x7ffff734bd96, op: 467
|
| 609 |
+
[102]: ad: 0x7ffff734bd99, op: 427
|
| 610 |
+
[102]: ad: 0x7ffff734bd9c, op: 427
|
| 611 |
+
[102]: ad: 0x7ffff734bda0, op: 740
|
| 612 |
+
new bb detected: 103
|
| 613 |
+
[103]: ad: 0x7ffff3d8e491, op: 427
|
| 614 |
+
[103]: ad: 0x7ffff3d8e495, op: 8
|
| 615 |
+
[103]: ad: 0x7ffff3d8e49a, op: 109
|
| 616 |
+
[103]: ad: 0x7ffff3d8e49d, op: 325
|
| 617 |
+
new bb detected: 104
|
| 618 |
+
[104]: ad: 0x7ffff72038b0, op: 109
|
| 619 |
+
[104]: ad: 0x7ffff72038b3, op: 318
|
| 620 |
+
new bb detected: 105
|
| 621 |
+
[105]: ad: 0x7ffff72038e2, op: 1232
|
| 622 |
+
[105]: ad: 0x7ffff72038e6, op: 1232
|
| 623 |
+
[105]: ad: 0x7ffff72038ec, op: 1232
|
| 624 |
+
[105]: ad: 0x7ffff72038f0, op: 1232
|
| 625 |
+
[105]: ad: 0x7ffff72038f6, op: 740
|
| 626 |
+
new bb detected: 106
|
| 627 |
+
[106]: ad: 0x7ffff71080f7, op: 427
|
| 628 |
+
[106]: ad: 0x7ffff71080ff, op: 847
|
| 629 |
+
[106]: ad: 0x7ffff7108101, op: 330
|
| 630 |
+
new bb detected: 107
|
| 631 |
+
[107]: ad: 0x7ffff7108250, op: 388
|
| 632 |
+
[107]: ad: 0x7ffff7108257, op: 427
|
| 633 |
+
[107]: ad: 0x7ffff710825a, op: 427
|
| 634 |
+
[107]: ad: 0x7ffff710825d, op: 75
|
| 635 |
+
new bb detected: 108
|
| 636 |
+
[108]: ad: 0x7ffff71069b0, op: 847
|
| 637 |
+
[108]: ad: 0x7ffff71069b3, op: 329
|
| 638 |
+
new bb detected: 109
|
| 639 |
+
[109]: ad: 0x7ffff71069b9, op: 671
|
| 640 |
+
[109]: ad: 0x7ffff71069bb, op: 388
|
| 641 |
+
[109]: ad: 0x7ffff71069bf, op: 671
|
| 642 |
+
[109]: ad: 0x7ffff71069c1, op: 671
|
| 643 |
+
[109]: ad: 0x7ffff71069c3, op: 671
|
| 644 |
+
[109]: ad: 0x7ffff71069c5, op: 671
|
| 645 |
+
[109]: ad: 0x7ffff71069c6, op: 427
|
| 646 |
+
[109]: ad: 0x7ffff71069c9, op: 671
|
| 647 |
+
[109]: ad: 0x7ffff71069ca, op: 427
|
| 648 |
+
[109]: ad: 0x7ffff71069cd, op: 826
|
| 649 |
+
[109]: ad: 0x7ffff71069d4, op: 109
|
| 650 |
+
[109]: ad: 0x7ffff71069d8, op: 319
|
| 651 |
+
new bb detected: 110
|
| 652 |
+
[110]: ad: 0x7ffff7106af8, op: 31
|
| 653 |
+
[110]: ad: 0x7ffff7106afc, op: 427
|
| 654 |
+
[110]: ad: 0x7ffff7106aff, op: 847
|
| 655 |
+
[110]: ad: 0x7ffff7106b02, op: 330
|
| 656 |
+
new bb detected: 111
|
| 657 |
+
[111]: ad: 0x7ffff7106b08, op: 427
|
| 658 |
+
[111]: ad: 0x7ffff7106b0b, op: 799
|
| 659 |
+
[111]: ad: 0x7ffff7106b0f, op: 109
|
| 660 |
+
[111]: ad: 0x7ffff7106b16, op: 311
|
| 661 |
+
new bb detected: 112
|
| 662 |
+
[112]: ad: 0x7ffff7106d60, op: 388
|
| 663 |
+
[112]: ad: 0x7ffff7106d64, op: 388
|
| 664 |
+
[112]: ad: 0x7ffff7106d68, op: 388
|
| 665 |
+
[112]: ad: 0x7ffff7106d70, op: 427
|
| 666 |
+
[112]: ad: 0x7ffff7106d74, op: 847
|
| 667 |
+
[112]: ad: 0x7ffff7106d77, op: 325
|
| 668 |
+
new bb detected: 113
|
| 669 |
+
[113]: ad: 0x7ffff7106c04, op: 847
|
| 670 |
+
[113]: ad: 0x7ffff7106c07, op: 325
|
| 671 |
+
new bb detected: 114
|
| 672 |
+
[114]: ad: 0x7ffff7106c0d, op: 8
|
| 673 |
+
[114]: ad: 0x7ffff7106c10, op: 427
|
| 674 |
+
[114]: ad: 0x7ffff7106c18, op: 427
|
| 675 |
+
[114]: ad: 0x7ffff7106c1c, op: 847
|
| 676 |
+
[114]: ad: 0x7ffff7106c1e, op: 325
|
| 677 |
+
new bb detected: 115
|
| 678 |
+
[115]: ad: 0x7ffff7106c24, op: 388
|
| 679 |
+
[115]: ad: 0x7ffff7106c28, op: 427
|
| 680 |
+
[115]: ad: 0x7ffff7106c2b, op: 799
|
| 681 |
+
[115]: ad: 0x7ffff7106c2f, op: 1723
|
| 682 |
+
[115]: ad: 0x7ffff7106c32, op: 427
|
| 683 |
+
[115]: ad: 0x7ffff7106c36, op: 427
|
| 684 |
+
[115]: ad: 0x7ffff7106c3a, op: 799
|
| 685 |
+
[115]: ad: 0x7ffff7106c3d, op: 109
|
| 686 |
+
[115]: ad: 0x7ffff7106c40, op: 325
|
| 687 |
+
new bb detected: 116
|
| 688 |
+
[116]: ad: 0x7ffff7106c46, op: 427
|
| 689 |
+
[116]: ad: 0x7ffff7106c4d, op: 388
|
| 690 |
+
[116]: ad: 0x7ffff7106c51, op: 799
|
| 691 |
+
[116]: ad: 0x7ffff7106c55, op: 427
|
| 692 |
+
[116]: ad: 0x7ffff7106c5a, op: 847
|
| 693 |
+
[116]: ad: 0x7ffff7106c5d, op: 330
|
| 694 |
+
new bb detected: 117
|
| 695 |
+
[117]: ad: 0x7ffff7106c63, op: 109
|
| 696 |
+
[117]: ad: 0x7ffff7106c6a, op: 311
|
| 697 |
+
new bb detected: 118
|
| 698 |
+
[118]: ad: 0x7ffff7106c70, op: 468
|
| 699 |
+
[118]: ad: 0x7ffff7106c75, op: 109
|
| 700 |
+
[118]: ad: 0x7ffff7106c7c, op: 388
|
| 701 |
+
[118]: ad: 0x7ffff7106c80, op: 310
|
| 702 |
+
new bb detected: 119
|
| 703 |
+
[119]: ad: 0x7ffff7106cdb, op: 427
|
| 704 |
+
[119]: ad: 0x7ffff7106cdf, op: 847
|
| 705 |
+
[119]: ad: 0x7ffff7106ce2, op: 330
|
| 706 |
+
new bb detected: 120
|
| 707 |
+
[120]: ad: 0x7ffff7106ce8, op: 847
|
| 708 |
+
[120]: ad: 0x7ffff7106ceb, op: 325
|
| 709 |
+
new bb detected: 121
|
| 710 |
+
[121]: ad: 0x7ffff7106cf1, op: 427
|
| 711 |
+
[121]: ad: 0x7ffff7106cf9, op: 427
|
| 712 |
+
[121]: ad: 0x7ffff7106cfd, op: 847
|
| 713 |
+
[121]: ad: 0x7ffff7106cff, op: 330
|
| 714 |
+
new bb detected: 122
|
| 715 |
+
[122]: ad: 0x7ffff7106c90, op: 388
|
| 716 |
+
[122]: ad: 0x7ffff7106c94, op: 427
|
| 717 |
+
[122]: ad: 0x7ffff7106c97, op: 799
|
| 718 |
+
[122]: ad: 0x7ffff7106c9b, op: 1723
|
| 719 |
+
[122]: ad: 0x7ffff7106c9e, op: 427
|
| 720 |
+
[122]: ad: 0x7ffff7106ca2, op: 427
|
| 721 |
+
[122]: ad: 0x7ffff7106ca9, op: 427
|
| 722 |
+
[122]: ad: 0x7ffff7106cad, op: 427
|
| 723 |
+
[122]: ad: 0x7ffff7106cb2, op: 468
|
| 724 |
+
[122]: ad: 0x7ffff7106cb7, op: 1723
|
| 725 |
+
[122]: ad: 0x7ffff7106cbb, op: 427
|
| 726 |
+
[122]: ad: 0x7ffff7106cbf, op: 8
|
| 727 |
+
[122]: ad: 0x7ffff7106cc2, op: 427
|
| 728 |
+
[122]: ad: 0x7ffff7106cc6, op: 427
|
| 729 |
+
[122]: ad: 0x7ffff7106ccb, op: 468
|
| 730 |
+
[122]: ad: 0x7ffff7106cce, op: 109
|
| 731 |
+
[122]: ad: 0x7ffff7106cd5, op: 318
|
| 732 |
+
new bb detected: 123
|
| 733 |
+
[123]: ad: 0x7ffff710706c, op: 427
|
| 734 |
+
[123]: ad: 0x7ffff7107072, op: 847
|
| 735 |
+
[123]: ad: 0x7ffff7107074, op: 325
|
| 736 |
+
new bb detected: 124
|
| 737 |
+
[124]: ad: 0x7ffff7107076, op: 8
|
| 738 |
+
[124]: ad: 0x7ffff710707d, op: 427
|
| 739 |
+
[124]: ad: 0x7ffff7107080, op: 616
|
| 740 |
+
[124]: ad: 0x7ffff7107081, op: 616
|
| 741 |
+
[124]: ad: 0x7ffff7107082, op: 616
|
| 742 |
+
[124]: ad: 0x7ffff7107084, op: 616
|
| 743 |
+
[124]: ad: 0x7ffff7107086, op: 616
|
| 744 |
+
[124]: ad: 0x7ffff7107088, op: 616
|
| 745 |
+
[124]: ad: 0x7ffff710708a, op: 740
|
| 746 |
+
new bb detected: 125
|
| 747 |
+
[125]: ad: 0x7ffff7108262, op: 847
|
| 748 |
+
[125]: ad: 0x7ffff7108265, op: 330
|
| 749 |
+
new bb detected: 126
|
| 750 |
+
[126]: ad: 0x7ffff710826b, op: 427
|
| 751 |
+
[126]: ad: 0x7ffff710826f, op: 847
|
| 752 |
+
[126]: ad: 0x7ffff7108272, op: 325
|
| 753 |
+
new bb detected: 127
|
| 754 |
+
[127]: ad: 0x7ffff7108278, op: 31
|
| 755 |
+
[127]: ad: 0x7ffff710827b, op: 330
|
| 756 |
+
new bb detected: 128
|
| 757 |
+
[128]: ad: 0x7ffff71081a2, op: 8
|
| 758 |
+
[128]: ad: 0x7ffff71081a6, op: 616
|
| 759 |
+
[128]: ad: 0x7ffff71081a7, op: 616
|
| 760 |
+
[128]: ad: 0x7ffff71081a8, op: 616
|
| 761 |
+
[128]: ad: 0x7ffff71081aa, op: 740
|
| 762 |
+
new bb detected: 129
|
| 763 |
+
[129]: ad: 0x7ffff720394d, op: 109
|
| 764 |
+
[129]: ad: 0x7ffff7203954, op: 319
|
| 765 |
+
new bb detected: 130
|
| 766 |
+
[130]: ad: 0x7ffff7203956, op: 1232
|
| 767 |
+
[130]: ad: 0x7ffff720395b, op: 109
|
| 768 |
+
[130]: ad: 0x7ffff7203962, op: 311
|
| 769 |
+
new bb detected: 131
|
| 770 |
+
[131]: ad: 0x7ffff7203911, op: 1232
|
| 771 |
+
[131]: ad: 0x7ffff7203917, op: 1232
|
| 772 |
+
[131]: ad: 0x7ffff720391d, op: 1232
|
| 773 |
+
[131]: ad: 0x7ffff7203921, op: 1232
|
| 774 |
+
[131]: ad: 0x7ffff7203926, op: 1232
|
| 775 |
+
[131]: ad: 0x7ffff720392c, op: 1232
|
| 776 |
+
[131]: ad: 0x7ffff7203932, op: 1704
|
| 777 |
+
[131]: ad: 0x7ffff7203935, op: 740
|
| 778 |
+
new bb detected: 132
|
| 779 |
+
[132]: ad: 0x7ffff72038b5, op: 109
|
| 780 |
+
[132]: ad: 0x7ffff72038b8, op: 318
|
| 781 |
+
new bb detected: 133
|
| 782 |
+
[133]: ad: 0x7ffff7203900, op: 427
|
| 783 |
+
[133]: ad: 0x7ffff7203905, op: 427
|
| 784 |
+
[133]: ad: 0x7ffff7203908, op: 427
|
| 785 |
+
[133]: ad: 0x7ffff720390b, op: 427
|
| 786 |
+
[133]: ad: 0x7ffff7203910, op: 740
|
| 787 |
+
new bb detected: 134
|
| 788 |
+
Scarab gitrev: 7185dea
|
| 789 |
+
Warning: Scarab expects the trace file type to include OFFLINE_FILE_TYPE_ARCH_REGDEPS (0x20000), but got type: 0xe40
|
| 790 |
+
Scarab started at Fri Jul 17 21:08:30 2026
|
| 791 |
+
|
| 792 |
+
read from initialization: 0x7ffff3d8e3f4
|
| 793 |
+
advanceReader: ROI end reached (ordinal 20000002 > roi_end 20000000)
|
| 794 |
+
Reached end of trace (last_inst) pc=0x7ffff71080b6
|
| 795 |
+
[54]: ad: 0x7ffff71080a0, op: 482
|
| 796 |
+
[54]: ad: 0x7ffff71080a4, op: 671
|
| 797 |
+
[54]: ad: 0x7ffff71080a6, op: 671
|
| 798 |
+
[54]: ad: 0x7ffff71080a7, op: 427
|
| 799 |
+
[54]: ad: 0x7ffff71080aa, op: 671
|
| 800 |
+
[54]: ad: 0x7ffff71080ab, op: 826
|
| 801 |
+
[54]: ad: 0x7ffff71080af, op: 109
|
| 802 |
+
DUP bb detected at trace end
|
| 803 |
+
to be appened segment num 1
|
| 804 |
+
10000000
|
| 805 |
+
10000000
|
| 806 |
+
====================================
|
| 807 |
+
TRACE_INST_TAKEN_NOT_CF:0
|
| 808 |
+
TRACE_INST_TAKEN_CF_BR:159600
|
| 809 |
+
TRACE_INST_TAKEN_CF_CBR:282389
|
| 810 |
+
TRACE_INST_TAKEN_CF_REP:0
|
| 811 |
+
TRACE_INST_TAKEN_CF_CALL:238236
|
| 812 |
+
TRACE_INST_TAKEN_CF_IBR:204908
|
| 813 |
+
TRACE_INST_TAKEN_CF_ICALL:0
|
| 814 |
+
TRACE_INST_TAKEN_CF_ICO:0
|
| 815 |
+
TRACE_INST_TAKEN_CF_RET:238232
|
| 816 |
+
TRACE_INST_TAKEN_CF_SYS:0
|
| 817 |
+
====================================
|
| 818 |
+
identity within this segment
|
| 819 |
+
2 bbs with same first pc
|
| 820 |
+
[54]: size 8, freq 40988
|
| 821 |
+
7ffff71080a0: 482, 0
|
| 822 |
+
7ffff71080a4: 671, 0
|
| 823 |
+
7ffff71080a6: 671, 0
|
| 824 |
+
7ffff71080a7: 427, 0
|
| 825 |
+
7ffff71080aa: 671, 0
|
| 826 |
+
7ffff71080ab: 826, 0
|
| 827 |
+
7ffff71080af: 109, 0
|
| 828 |
+
7ffff71080b6: 330, 0
|
| 829 |
+
[54]: size 7, freq 1
|
| 830 |
+
7ffff71080a0: 482, 0
|
| 831 |
+
7ffff71080a4: 671, 0
|
| 832 |
+
7ffff71080a6: 671, 0
|
| 833 |
+
7ffff71080a7: 427, 0
|
| 834 |
+
7ffff71080aa: 671, 0
|
| 835 |
+
7ffff71080ab: 826, 0
|
| 836 |
+
7ffff71080af: 109, 0
|
| 837 |
+
1 / 134
|
| 838 |
+
========================================================
|
| 839 |
+
Number of blocks built : 134
|
| 840 |
+
Average size : 4.87 instructions
|
| 841 |
+
Number of blocks executed : 2114408
|
| 842 |
+
Average weighted size : 4.73 instructions
|
| 843 |
+
Number of total instructions : 10000000
|
| 844 |
+
Number of fetched instruction : 10000000
|
| 845 |
+
========================================================
|
| 846 |
+
Scarab finished at Fri Jul 17 21:08:37 2026
|
| 847 |
+
|
tsp/fingerprint/run_10/PARAMS.in
ADDED
|
@@ -0,0 +1,268 @@
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|
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|
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|
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|
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|
|
|
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|
|
|
|
|
|
|
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|
|
|
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|
|
|
|
|
|
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|
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|
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|
|
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|
|
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|
|
|
|
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|
|
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|
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|
|
|
|
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|
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|
|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
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|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
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|
|
|
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|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
|
|
|
|
|
|
|
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|
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|
|
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|
|
|
|
|
|
|
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|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
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|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# File : PARAMS.golden_cove
|
| 2 |
+
# Date : 02/27/25
|
| 3 |
+
# Description : Golden Cove Configuration
|
| 4 |
+
# Author : Surim Oh <[email protected]>
|
| 5 |
+
#
|
| 6 |
+
# Based on documentation found here:
|
| 7 |
+
# https://en.wikipedia.org/wiki/Golden_Cove
|
| 8 |
+
# https://en.wikichip.org/wiki/intel/microarchitectures/golden_cove
|
| 9 |
+
# https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/3
|
| 10 |
+
|
| 11 |
+
## Simulation Parameters
|
| 12 |
+
--mode full
|
| 13 |
+
--model cmp
|
| 14 |
+
--sim_limit none
|
| 15 |
+
|
| 16 |
+
## Core Parameters
|
| 17 |
+
|
| 18 |
+
# Femptoseconds, 3.2GHz, used for energy estimates.
|
| 19 |
+
--chip_cycle_time 312500
|
| 20 |
+
|
| 21 |
+
|
| 22 |
+
### Fetch Stage
|
| 23 |
+
--fetch_off_path_ops 1
|
| 24 |
+
|
| 25 |
+
#### ICache
|
| 26 |
+
--icache_size 32768
|
| 27 |
+
--icache_assoc 8
|
| 28 |
+
--icache_line_size 64
|
| 29 |
+
|
| 30 |
+
### Uop Cache
|
| 31 |
+
# inclusive w/ L1i
|
| 32 |
+
--uop_cache_enable 1
|
| 33 |
+
--uop_cache_width 8
|
| 34 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 35 |
+
--uop_cache_assoc 8
|
| 36 |
+
--iprf_on_uop_cache_hit 1
|
| 37 |
+
|
| 38 |
+
### Branch Predictor
|
| 39 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 40 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 41 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 42 |
+
--bp_mech tage64k
|
| 43 |
+
|
| 44 |
+
|
| 45 |
+
#### BTB
|
| 46 |
+
|
| 47 |
+
# TODO
|
| 48 |
+
# multi-level BTB
|
| 49 |
+
# 128 entry L0 BTB
|
| 50 |
+
# 6144 entry L1 BTB
|
| 51 |
+
# 12888 entry L2 BTB
|
| 52 |
+
# ~2 entry Return Stack
|
| 53 |
+
# roughly 2x8192 for now
|
| 54 |
+
# BTB model to use.
|
| 55 |
+
--btb_mech generic
|
| 56 |
+
--btb_entries 12288
|
| 57 |
+
--btb_assoc 4
|
| 58 |
+
--btb_main_latency 3
|
| 59 |
+
--btb_l0_present 1
|
| 60 |
+
--btb_l0_entries 128
|
| 61 |
+
--btb_l0_assoc 4
|
| 62 |
+
--btb_l0_latency 1
|
| 63 |
+
--btb_l1_present 1
|
| 64 |
+
--btb_l1_entries 6144
|
| 65 |
+
--btb_l1_assoc 4
|
| 66 |
+
--btb_l1_latency 2
|
| 67 |
+
|
| 68 |
+
# Allow the BTB to be updated by off path ops.
|
| 69 |
+
--btb_off_path_writes 1
|
| 70 |
+
|
| 71 |
+
# NT branches are not inserted in BTB, but do not trigger resteer
|
| 72 |
+
# since we continue without a control flow change
|
| 73 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 74 |
+
|
| 75 |
+
#### CRS
|
| 76 |
+
|
| 77 |
+
# Enable return stack
|
| 78 |
+
--enable_crs 1
|
| 79 |
+
--crs_entries 128
|
| 80 |
+
--crs_realistic 1
|
| 81 |
+
|
| 82 |
+
### iBP
|
| 83 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 84 |
+
--ibtb_mech tc_tagged
|
| 85 |
+
# iBTB Model. tc_tagless, tc_tagged, tc_hybrid.
|
| 86 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 87 |
+
--tc_entries 4096
|
| 88 |
+
--tc_assoc 4
|
| 89 |
+
|
| 90 |
+
### Decode Stage
|
| 91 |
+
--decode_width 6
|
| 92 |
+
--decode_cycles 5
|
| 93 |
+
|
| 94 |
+
### Instruction Decode Queue
|
| 95 |
+
--idq_size 144
|
| 96 |
+
|
| 97 |
+
### Map Stage
|
| 98 |
+
--map_cycles 5
|
| 99 |
+
|
| 100 |
+
# register renaming table
|
| 101 |
+
--reg_renaming_scheme 1
|
| 102 |
+
--reg_table_integer_physical_size 280
|
| 103 |
+
--reg_table_vector_physical_size 332
|
| 104 |
+
|
| 105 |
+
### Issue Stage
|
| 106 |
+
|
| 107 |
+
# Max number of instructions to be renamed, and issued per cycle.
|
| 108 |
+
--issue_width 6
|
| 109 |
+
|
| 110 |
+
--rs_fill_width 0
|
| 111 |
+
# rs_sizes ~205 in total, and they are split into three different reservation stations (RS1, RS2, RS3) where each has 97, 70, 38 entries respectively
|
| 112 |
+
# original architecture
|
| 113 |
+
# RS1 connected to port 0,1,5,6,10
|
| 114 |
+
# RS2 connected to port 2,3,11
|
| 115 |
+
# RS3 connected to port 7,8,4,9
|
| 116 |
+
# scarab does not split ST AGU port and ST port, merge them
|
| 117 |
+
# adjusted architecture to scarab ST AGU (port 4 and 9 removed. rs_size reduced to 186 from 205)
|
| 118 |
+
# RS1 connected to port 0,1,4,5,8
|
| 119 |
+
# RS2 connected to port 2,3,9
|
| 120 |
+
# RS3 connected to port 6,7 (port 4,9 removed, entries reduced to 19 from 38)
|
| 121 |
+
--rs_sizes 97 70 19
|
| 122 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 123 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 124 |
+
|
| 125 |
+
### Exec Stage
|
| 126 |
+
|
| 127 |
+
### DCache
|
| 128 |
+
--dcache_size 49152
|
| 129 |
+
--dcache_read_ports 1
|
| 130 |
+
--dcache_write_ports 1
|
| 131 |
+
--dcache_banks 8
|
| 132 |
+
--dcache_assoc 12
|
| 133 |
+
--dcache_line_size 64
|
| 134 |
+
--dcache_cycles 5
|
| 135 |
+
|
| 136 |
+
### Reorder/Retire Stage
|
| 137 |
+
|
| 138 |
+
# Max number of instructions to be retired per cycle.
|
| 139 |
+
--node_ret_width 8
|
| 140 |
+
--node_table_size 512
|
| 141 |
+
|
| 142 |
+
# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does
|
| 143 |
+
--stores_do_not_block_window 1
|
| 144 |
+
|
| 145 |
+
# TODO: confirm what this knob does
|
| 146 |
+
--prefs_do_not_block_window 1
|
| 147 |
+
|
| 148 |
+
|
| 149 |
+
## Uncore
|
| 150 |
+
|
| 151 |
+
### Mid-level cache
|
| 152 |
+
|
| 153 |
+
# Enable use of a midlevel cache between i/d and L1
|
| 154 |
+
# client 1.25 MiB (1310720 bytes) per core, 8-way, 15 cycles
|
| 155 |
+
# server 2 MiB (2097000 bytes) per core, 8-way, 16 cycles
|
| 156 |
+
--mlc_present 1
|
| 157 |
+
--mlc_size 2097000
|
| 158 |
+
--mlc_assoc 8
|
| 159 |
+
--mlc_cycles 16
|
| 160 |
+
|
| 161 |
+
|
| 162 |
+
### LLC
|
| 163 |
+
# 3 MiB per core, 16-way
|
| 164 |
+
--l1_size 3145728
|
| 165 |
+
--l1_banks 8
|
| 166 |
+
--l1_cycles 36 // just a guess
|
| 167 |
+
--l1_assoc 16
|
| 168 |
+
--l1_line_size 64
|
| 169 |
+
--l1_interleave_factor 64
|
| 170 |
+
|
| 171 |
+
|
| 172 |
+
### prefetcher
|
| 173 |
+
# Kept same as Kaby Lake
|
| 174 |
+
--pref_framework_on 1
|
| 175 |
+
--pref_stream_on 1
|
| 176 |
+
--pref_train_on_pref_misses 0
|
| 177 |
+
--pref_oracle_train 0
|
| 178 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 179 |
+
|
| 180 |
+
--stream_length 64
|
| 181 |
+
--stream_prefetch_n 4
|
| 182 |
+
--stream_start_dis 1
|
| 183 |
+
--stream_train_num 4
|
| 184 |
+
--stream_create_on_dc_miss 0
|
| 185 |
+
--stream_create_on_l1_miss 1
|
| 186 |
+
|
| 187 |
+
--pref_throttlefb_on=1
|
| 188 |
+
--pref_acc_thresh_1=0.75
|
| 189 |
+
--pref_acc_thresh_2=0.4
|
| 190 |
+
--pref_acc_thresh_3=0.4
|
| 191 |
+
--pref_timely_thresh=0.01
|
| 192 |
+
--pref_polpf_thresh=0.005
|
| 193 |
+
--pref_update_interval=8192
|
| 194 |
+
|
| 195 |
+
--mem_req_buffer_pref_watermark 4
|
| 196 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 197 |
+
|
| 198 |
+
### Memory
|
| 199 |
+
# Kept same as Kaby Lake
|
| 200 |
+
--addr_translation random
|
| 201 |
+
|
| 202 |
+
--mem_priority_ifetch 0
|
| 203 |
+
--mem_priority_dfetch 1
|
| 204 |
+
--mem_priority_dstore 2
|
| 205 |
+
--mem_priority_iprf 3
|
| 206 |
+
--mem_priority_dprf 4
|
| 207 |
+
--mem_priority_wb 5
|
| 208 |
+
--mem_priority_wb_nodirty 5
|
| 209 |
+
|
| 210 |
+
--mem_req_buffer_entries 32
|
| 211 |
+
--bus_width_in_bytes 8
|
| 212 |
+
|
| 213 |
+
--ramulator_standard DDR4
|
| 214 |
+
--ramulator_speed DDR4_2400R
|
| 215 |
+
--ramulator_org DDR4_8Gb_x8
|
| 216 |
+
--ramulator_channels 1
|
| 217 |
+
--ramulator_ranks 1
|
| 218 |
+
--ramulator_bankgroups 4
|
| 219 |
+
--ramulator_banks 4
|
| 220 |
+
--ramulator_chip_width 8
|
| 221 |
+
--ramulator_rows 65536
|
| 222 |
+
--ramulator_cols 1024
|
| 223 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 224 |
+
--ramulator_readq_entries 32
|
| 225 |
+
--ramulator_writeq_entries 32
|
| 226 |
+
--ramulator_record_cmd_trace FALSE
|
| 227 |
+
--ramulator_print_cmd_trace FALSE
|
| 228 |
+
--ramulator_tCK 833333
|
| 229 |
+
--ramulator_tCL 16
|
| 230 |
+
--ramulator_tCCD 6
|
| 231 |
+
--ramulator_tCCDS 4
|
| 232 |
+
--ramulator_tCCDL 6
|
| 233 |
+
--ramulator_tCWL 12
|
| 234 |
+
--ramulator_tBL 4
|
| 235 |
+
--ramulator_tWTR 9
|
| 236 |
+
--ramulator_tWTRS 3
|
| 237 |
+
--ramulator_tWTRL 9
|
| 238 |
+
--ramulator_tRP 16
|
| 239 |
+
--ramulator_tRPpb 16
|
| 240 |
+
--ramulator_tRPab 16
|
| 241 |
+
--ramulator_tRCD 16
|
| 242 |
+
--ramulator_tRCDR 16
|
| 243 |
+
--ramulator_tRCDW 16
|
| 244 |
+
--ramulator_tRAS 39
|
| 245 |
+
--dram_tech_in_nm 32
|
| 246 |
+
|
| 247 |
+
## Other
|
| 248 |
+
|
| 249 |
+
|
| 250 |
+
### Debug
|
| 251 |
+
--debug_inst_start 0
|
| 252 |
+
--debug_inst_stop -1
|
| 253 |
+
--debug_cycle_start 0
|
| 254 |
+
--debug_cycle_stop -1
|
| 255 |
+
|
| 256 |
+
|
| 257 |
+
## Stats and Params
|
| 258 |
+
--dump_params 1
|
| 259 |
+
--dump_stats 1
|
| 260 |
+
--dump_trace 0
|
| 261 |
+
|
| 262 |
+
####################################
|
| 263 |
+
--set_off_path_confirmed 1
|
| 264 |
+
|
| 265 |
+
--order_beyond_bus 1
|
| 266 |
+
|
| 267 |
+
--mem_ooo_stores 1
|
| 268 |
+
--mem_obey_store_dep 1
|
tsp/fingerprint/run_10/PARAMS.out
ADDED
|
@@ -0,0 +1,1102 @@
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|
| 1 |
+
--mode trace_bbv_distributed
|
| 2 |
+
--model cmp
|
| 3 |
+
--frontend memtrace
|
| 4 |
+
--sim_limit none
|
| 5 |
+
--memtrace_roi_begin 100000001
|
| 6 |
+
--memtrace_roi_end 110000000
|
| 7 |
+
--use_fetched_count 1
|
| 8 |
+
--dump_params 1
|
| 9 |
+
--dump_stats 1
|
| 10 |
+
--dump_trace 0
|
| 11 |
+
--trace_bbv_output /dev/shm/baseline/traces/tsp/fingerprint/pieces/segment.10
|
| 12 |
+
--trace_footprint_output /dev/shm/baseline/traces/tsp/fingerprint/footprint_pieces/segment.10
|
| 13 |
+
--segment_instr_count 10000000
|
| 14 |
+
--mlc_present 1
|
| 15 |
+
--mlc_size 2097000
|
| 16 |
+
--mlc_assoc 8
|
| 17 |
+
--mlc_cycles 16
|
| 18 |
+
--l1_size 3145728
|
| 19 |
+
--l1_assoc 16
|
| 20 |
+
--l1_line_size 64
|
| 21 |
+
--l1_cycles 36 // just a guess
|
| 22 |
+
--l1_banks 8
|
| 23 |
+
--l1_interleave_factor 64
|
| 24 |
+
--addr_translation random
|
| 25 |
+
--icache_size 32768
|
| 26 |
+
--icache_assoc 8
|
| 27 |
+
--icache_line_size 64
|
| 28 |
+
--uop_cache_enable 1
|
| 29 |
+
--uop_cache_width 8
|
| 30 |
+
--uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 31 |
+
--uop_cache_assoc 8
|
| 32 |
+
--iprf_on_uop_cache_hit 1
|
| 33 |
+
--dcache_size 49152
|
| 34 |
+
--dcache_assoc 12
|
| 35 |
+
--dcache_line_size 64
|
| 36 |
+
--dcache_cycles 5
|
| 37 |
+
--dcache_read_ports 1
|
| 38 |
+
--dcache_write_ports 1
|
| 39 |
+
--dcache_banks 8
|
| 40 |
+
--mem_ooo_stores 1
|
| 41 |
+
--mem_obey_store_dep 1
|
| 42 |
+
--mem_req_buffer_entries 32
|
| 43 |
+
--mem_priority_ifetch 0
|
| 44 |
+
--mem_priority_dfetch 1
|
| 45 |
+
--mem_priority_dstore 2
|
| 46 |
+
--mem_priority_iprf 3
|
| 47 |
+
--mem_priority_dprf 4
|
| 48 |
+
--mem_priority_wb 5
|
| 49 |
+
--mem_priority_wb_nodirty 5
|
| 50 |
+
--promote_to_higher_priority_mem_req_type 1
|
| 51 |
+
--mem_req_buffer_pref_watermark 4
|
| 52 |
+
--order_beyond_bus 1
|
| 53 |
+
--set_off_path_confirmed 1
|
| 54 |
+
--ramulator_standard DDR4
|
| 55 |
+
--ramulator_speed DDR4_2400R
|
| 56 |
+
--ramulator_org DDR4_8Gb_x8
|
| 57 |
+
--ramulator_channels 1
|
| 58 |
+
--ramulator_ranks 1
|
| 59 |
+
--ramulator_bankgroups 4
|
| 60 |
+
--ramulator_banks 4
|
| 61 |
+
--ramulator_chip_width 8
|
| 62 |
+
--bus_width_in_bytes 8
|
| 63 |
+
--ramulator_rows 65536
|
| 64 |
+
--ramulator_cols 1024
|
| 65 |
+
--ramulator_scheduling_policy FRFCFS_Cap
|
| 66 |
+
--ramulator_readq_entries 32
|
| 67 |
+
--ramulator_writeq_entries 32
|
| 68 |
+
--ramulator_record_cmd_trace FALSE
|
| 69 |
+
--ramulator_print_cmd_trace FALSE
|
| 70 |
+
--ramulator_tCK 833333
|
| 71 |
+
--ramulator_tCL 16
|
| 72 |
+
--ramulator_tCCD 6
|
| 73 |
+
--ramulator_tCCDS 4
|
| 74 |
+
--ramulator_tCCDL 6
|
| 75 |
+
--ramulator_tCWL 12
|
| 76 |
+
--ramulator_tBL 4
|
| 77 |
+
--ramulator_tWTR 9
|
| 78 |
+
--ramulator_tWTRS 3
|
| 79 |
+
--ramulator_tWTRL 9
|
| 80 |
+
--ramulator_tRP 16
|
| 81 |
+
--ramulator_tRPpb 16
|
| 82 |
+
--ramulator_tRPab 16
|
| 83 |
+
--ramulator_tRCD 16
|
| 84 |
+
--ramulator_tRCDR 16
|
| 85 |
+
--ramulator_tRCDW 16
|
| 86 |
+
--ramulator_tRAS 39
|
| 87 |
+
--dram_tech_in_nm 32
|
| 88 |
+
--chip_cycle_time 312500
|
| 89 |
+
--issue_width 6
|
| 90 |
+
--rs_fill_width 0
|
| 91 |
+
--node_table_size 512
|
| 92 |
+
--node_ret_width 8
|
| 93 |
+
--decode_width 6
|
| 94 |
+
--idq_size 144
|
| 95 |
+
--reg_renaming_scheme 1
|
| 96 |
+
--reg_table_integer_physical_size 280
|
| 97 |
+
--reg_table_vector_physical_size 332
|
| 98 |
+
--rs_sizes 97 70 19
|
| 99 |
+
--rs_connections b0100110011 b1000001100 b0011000000
|
| 100 |
+
--fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 101 |
+
--decode_cycles 5
|
| 102 |
+
--map_cycles 5
|
| 103 |
+
--fetch_off_path_ops 1
|
| 104 |
+
--stores_do_not_block_window 1
|
| 105 |
+
--prefs_do_not_block_window 1
|
| 106 |
+
--cbp_trace_r0 /dev/shm/baseline/traces/.staging/tsp-164844/raw_trace/drmemtrace.tsp.164856.4389.dir/trace/drmemtrace.tsp.164856.1160.trace.zip
|
| 107 |
+
--debug_cycle_start 0
|
| 108 |
+
--debug_cycle_stop -1
|
| 109 |
+
--debug_inst_start 0
|
| 110 |
+
--debug_inst_stop -1
|
| 111 |
+
--perfect_nt_btb 0 # deprecated, effectively always true.
|
| 112 |
+
--cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle
|
| 113 |
+
--update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 114 |
+
--bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec.
|
| 115 |
+
--bp_mech tage64k
|
| 116 |
+
--btb_mech generic
|
| 117 |
+
--btb_entries 12288
|
| 118 |
+
--btb_assoc 4
|
| 119 |
+
--btb_off_path_writes 1
|
| 120 |
+
--btb_main_latency 3
|
| 121 |
+
--btb_l0_present 1
|
| 122 |
+
--btb_l0_entries 128
|
| 123 |
+
--btb_l0_assoc 4
|
| 124 |
+
--btb_l0_latency 1
|
| 125 |
+
--btb_l1_present 1
|
| 126 |
+
--btb_l1_entries 6144
|
| 127 |
+
--btb_l1_assoc 4
|
| 128 |
+
--btb_l1_latency 2
|
| 129 |
+
--enable_crs 1
|
| 130 |
+
--crs_entries 128
|
| 131 |
+
--crs_realistic 1
|
| 132 |
+
--enable_ibp 1 # Enable the indirect branch predictor
|
| 133 |
+
--ibtb_mech tc_tagged
|
| 134 |
+
--ibtb_off_path_writes 1 # Allow off path ops to update the ibtb.
|
| 135 |
+
--tc_entries 4096
|
| 136 |
+
--tc_assoc 4
|
| 137 |
+
--pref_stream_on 1
|
| 138 |
+
--stream_prefetch_n 4
|
| 139 |
+
--stream_start_dis 1
|
| 140 |
+
--stream_length 64
|
| 141 |
+
--stream_train_num 4
|
| 142 |
+
--stream_create_on_dc_miss 0
|
| 143 |
+
--stream_create_on_l1_miss 1
|
| 144 |
+
--pref_framework_on 1
|
| 145 |
+
--pref_ul1req_queue_overwrite_on_full 1
|
| 146 |
+
--pref_train_on_pref_misses 0
|
| 147 |
+
--pref_oracle_train_on 0
|
| 148 |
+
--pref_throttlefb_on 1
|
| 149 |
+
--pref_acc_thresh_1 0.75
|
| 150 |
+
--pref_acc_thresh_2 0.4
|
| 151 |
+
--pref_acc_thresh_3 0.4
|
| 152 |
+
--pref_update_interval 8192
|
| 153 |
+
--pref_timely_thresh 0.01
|
| 154 |
+
--pref_polpf_thresh 0.005
|
| 155 |
+
1 1 1 1 1 1 1
|
| 156 |
+
|
| 157 |
+
--- Cut out everything below to use this file as PARAMS.in ---
|
| 158 |
+
|
| 159 |
+
Parameter status at compile time and values supplied on the command line:
|
| 160 |
+
|
| 161 |
+
SIM_MODE 0 trace_bbv_distributed
|
| 162 |
+
SIM_MODEL 0 cmp
|
| 163 |
+
FRONTEND FE_PIN_EXEC_DRIVEN memtrace
|
| 164 |
+
INST_LIMIT NULL
|
| 165 |
+
SIM_LIMIT "none" none
|
| 166 |
+
FORWARD_PROGRESS_LIMIT 100000000
|
| 167 |
+
FORWARD_PROGRESS_INTERVAL 10000
|
| 168 |
+
FAST_FORWARD 0
|
| 169 |
+
FAST_FORWARD_TRACE_INS 0
|
| 170 |
+
FAST_FORWARD_UNTIL_ADDR 0
|
| 171 |
+
MEMTRACE_ROI_BEGIN 0 100000001
|
| 172 |
+
MEMTRACE_ROI_END 0 110000000
|
| 173 |
+
FULL_WARMUP 0
|
| 174 |
+
WARMUP 0
|
| 175 |
+
HEARTBEAT_INTERVAL 1000000
|
| 176 |
+
NUM_HEARTBEATS 0
|
| 177 |
+
USE_FETCHED_COUNT FALSE 1
|
| 178 |
+
PERIODIC_DUMP FALSE
|
| 179 |
+
FILE_TAG ""
|
| 180 |
+
OUTPUT_DIR "."
|
| 181 |
+
STATUS_FILE NULL
|
| 182 |
+
BINDIR NULL
|
| 183 |
+
DUMP_PARAMS TRUE 1
|
| 184 |
+
DUMP_STATS TRUE 1
|
| 185 |
+
DUMP_TRACE FALSE 0
|
| 186 |
+
CLEAR_STATS "never"
|
| 187 |
+
STATS_TO_TRACE NULL
|
| 188 |
+
STAT_TRACE_FILE "stats.trace"
|
| 189 |
+
STAT_TRACE_INTERVAL "i:100000"
|
| 190 |
+
PIPEVIEW FALSE
|
| 191 |
+
PIPEVIEW_FILE "pipeview"
|
| 192 |
+
MEMVIEW FALSE
|
| 193 |
+
MEMVIEW_FILE "memview.out"
|
| 194 |
+
MEMVIEW_START "never"
|
| 195 |
+
INST_HASH_TABLE_SIZE 524288 const
|
| 196 |
+
STDOUT_FILE NULL
|
| 197 |
+
STDERR_FILE NULL
|
| 198 |
+
PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp"
|
| 199 |
+
PRINT_PID FALSE
|
| 200 |
+
USE_UNSURE_FREE_LISTS FALSE
|
| 201 |
+
OPTIMIZER2_MAX_NUM_SLAVES 64
|
| 202 |
+
OPTIMIZER2_PERFECT_MEMORYLESS FALSE
|
| 203 |
+
EXIT_COND 0
|
| 204 |
+
NUM_NOPS 0
|
| 205 |
+
NOPS_BB_START 0x5000000
|
| 206 |
+
IGNORE_BAR_FETCH FALSE
|
| 207 |
+
TRACE_BBV_OUTPUT NULL /dev/shm/baseline/traces/tsp/fingerprint/pieces/segment.10
|
| 208 |
+
TRACE_FOOTPRINT_OUTPUT "" /dev/shm/baseline/traces/tsp/fingerprint/footprint_pieces/segment.10
|
| 209 |
+
SEGMENT_INSTR_COUNT 0 10000000
|
| 210 |
+
ENABLE_SWPRF FALSE
|
| 211 |
+
MLC_PRESENT FALSE 1
|
| 212 |
+
MLC_SIZE (512 * 1024) 2097000
|
| 213 |
+
MLC_ASSOC 4 8
|
| 214 |
+
MLC_LINE_SIZE 64
|
| 215 |
+
MLC_CYCLES 12 16
|
| 216 |
+
PERFECT_MLC FALSE
|
| 217 |
+
MLC_READ_PORTS 1
|
| 218 |
+
MLC_WRITE_PORTS 1
|
| 219 |
+
MLC_BANKS 8
|
| 220 |
+
MLC_INTERLEAVE_FACTOR 64
|
| 221 |
+
MLC_CACHE_REPL_POLICY 0
|
| 222 |
+
MLC_WRITE_THROUGH FALSE
|
| 223 |
+
PREFETCH_UPDATE_LRU_MLC TRUE
|
| 224 |
+
FORCE_L1_MISS FALSE
|
| 225 |
+
L1_SIZE (4 * 1024 * 1024) 3145728
|
| 226 |
+
L1_ASSOC 8 16
|
| 227 |
+
L1_LINE_SIZE 64 64
|
| 228 |
+
L1_CYCLES 24 36 // just a guess
|
| 229 |
+
PERFECT_L1 FALSE
|
| 230 |
+
PRIVATE_L1 FALSE
|
| 231 |
+
L1_READ_PORTS 1
|
| 232 |
+
L1_WRITE_PORTS 1
|
| 233 |
+
L1_BANKS 8 8
|
| 234 |
+
L1_INTERLEAVE_FACTOR 64 64
|
| 235 |
+
L1_CACHE_REPL_POLICY 0
|
| 236 |
+
L1_WRITE_THROUGH FALSE
|
| 237 |
+
L1_IGNORE_WB FALSE
|
| 238 |
+
L1_USE_CORE_FREQ FALSE
|
| 239 |
+
MARK_L1_MISSES TRUE
|
| 240 |
+
PREFETCH_UPDATE_LRU_L1 TRUE
|
| 241 |
+
MEMORY_RANDOM_ADDR FALSE
|
| 242 |
+
VA_PAGE_SIZE_BYTES 4096
|
| 243 |
+
NUM_ADDR_NON_SIGN_EXTEND_BITS 48
|
| 244 |
+
ADDR_TRANSLATION 0 random
|
| 245 |
+
CONSTANT_MEMORY_LATENCY FALSE
|
| 246 |
+
MEMORY_CYCLES 100
|
| 247 |
+
STALL_MEM_REQS_ONLY FALSE
|
| 248 |
+
ICACHE_SIZE (64 * 1024) 32768
|
| 249 |
+
ICACHE_ASSOC 4 8
|
| 250 |
+
ICACHE_LINE_SIZE 64 64
|
| 251 |
+
PERFECT_ICACHE FALSE
|
| 252 |
+
ICACHE_READ_PORTS 1
|
| 253 |
+
ICACHE_WRITE_PORTS 1
|
| 254 |
+
ICACHE_BANKS 8
|
| 255 |
+
ICACHE_REPL 0
|
| 256 |
+
UOP_CACHE_ENABLE 1 1
|
| 257 |
+
UOP_CACHE_WIDTH 6 8
|
| 258 |
+
ALWAYS_LOOKUP_ICACHE 0
|
| 259 |
+
UOP_CACHE_INSERT_ONLY_ONPATH FALSE
|
| 260 |
+
UOP_CACHE_READ_PORTS 1
|
| 261 |
+
UOP_CACHE_LINES 384 512 # 8 x 512 = 4096 uops in total (~4K)
|
| 262 |
+
UOP_CACHE_ASSOC 8 8
|
| 263 |
+
UOP_CACHE_MAX_IMM_DISP_LINE 4
|
| 264 |
+
IPRF_ON_UOP_CACHE_HIT FALSE 1
|
| 265 |
+
UOP_CACHE_REPL 0
|
| 266 |
+
PRIORITY_LINE_STICKINESS_PERCENT 50
|
| 267 |
+
PW_PRIORITY_LIST_FILEPATH "pw_priority_list.csv"
|
| 268 |
+
NUM_PRIORITY_PWS 10
|
| 269 |
+
PRIORITIZE_PWS_AFTER_FIRST_STICKY_UNTIL_BACKEND_STALL FALSE
|
| 270 |
+
NO_REPL_AFTER_QUEUE_SIZE 0
|
| 271 |
+
FDIP_UC_SIZE 0
|
| 272 |
+
FDIP_UC_ASSOC 4
|
| 273 |
+
FDIP_UC_INSERT_REPLPOL 0
|
| 274 |
+
MAP_STAGE_CONSUME_FROM_ICACHE_AND_UOC_SAME_CYCLE TRUE
|
| 275 |
+
UOP_QUEUE_LENGTH 7
|
| 276 |
+
DCACHE_SIZE (64 * 1024) 49152
|
| 277 |
+
DCACHE_ASSOC 1 12
|
| 278 |
+
DCACHE_LINE_SIZE 64 64
|
| 279 |
+
DCACHE_CYCLES 2 5
|
| 280 |
+
PERFECT_DCACHE FALSE
|
| 281 |
+
DCACHE_READ_PORTS 8 1
|
| 282 |
+
DCACHE_WRITE_PORTS 1 1
|
| 283 |
+
DCACHE_BANKS 1 8
|
| 284 |
+
DCACHE_INTERLEAVE_FACTOR 4
|
| 285 |
+
DCACHE_REPL 0
|
| 286 |
+
DCACHE_REPL_PREF_THRESH 1
|
| 287 |
+
MEM_OOO_STORES TRUE 1
|
| 288 |
+
MEM_OBEY_STORE_DEP TRUE 1
|
| 289 |
+
PREF_INSERT_LRU FALSE
|
| 290 |
+
PREF_INSERT_MIDDLE FALSE
|
| 291 |
+
PREF_INSERT_LOWQTR FALSE
|
| 292 |
+
PREF_INSERT_DYNACC FALSE
|
| 293 |
+
MEM_REQ_BUFFER_ENTRIES 32 32
|
| 294 |
+
PRIVATE_MSHR_ON TRUE
|
| 295 |
+
MEM_PRIORITY_IFETCH 0 0
|
| 296 |
+
MEM_PRIORITY_DFETCH 0 1
|
| 297 |
+
MEM_PRIORITY_DSTORE 0 2
|
| 298 |
+
MEM_PRIORITY_IPRF 9 3
|
| 299 |
+
MEM_PRIORITY_UOCPRF 9
|
| 300 |
+
MEM_PRIORITY_FDIPPRFON 8
|
| 301 |
+
MEM_PRIORITY_FDIPPRFOFF 9
|
| 302 |
+
MEM_PRIORITY_DPRF 10 4
|
| 303 |
+
MEM_PRIORITY_WB 0 5
|
| 304 |
+
MEM_PRIORITY_WB_NODIRTY 0 5
|
| 305 |
+
PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1
|
| 306 |
+
MEM_REQ_BUFFER_PREF_WATERMARK 0 4
|
| 307 |
+
MEM_REQ_BUFFER_WB_VALVE 2
|
| 308 |
+
MEM_L1_FILL_QUEUE_ENTRIES 32
|
| 309 |
+
MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE
|
| 310 |
+
MEM_MEM_QUEUE_PARTITION_ENABLE FALSE
|
| 311 |
+
MEM_BUS_OUT_QUEUE_AS_FIFO TRUE
|
| 312 |
+
OLDEST_FIRST_TO_MEM_QUEUE TRUE
|
| 313 |
+
ROUND_ROBIN_TO_MEM_QUEUE FALSE
|
| 314 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE FALSE
|
| 315 |
+
ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0
|
| 316 |
+
L1_CYCLE_TIME 312500
|
| 317 |
+
MLCQ_TO_L1Q_TRANSFER_LATENCY 1
|
| 318 |
+
L1Q_TO_FSB_TRANSFER_LATENCY 1
|
| 319 |
+
PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE
|
| 320 |
+
KICKOUT_PREFETCHES FALSE
|
| 321 |
+
KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE
|
| 322 |
+
KICKOUT_OLDEST_PREFETCH FALSE
|
| 323 |
+
KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE
|
| 324 |
+
ORDER_BEYOND_BUS FALSE 1
|
| 325 |
+
ALL_FIFO_QUEUES FALSE
|
| 326 |
+
QUEUE_MLC_SIZE 0
|
| 327 |
+
QUEUE_L1_SIZE 0
|
| 328 |
+
QUEUE_BUS_OUT_SIZE 0
|
| 329 |
+
QUEUE_CORE_FILL_SIZE 0
|
| 330 |
+
ALLOW_TYPE_MATCHES FALSE
|
| 331 |
+
STREAM_PREFETCH_ON FALSE
|
| 332 |
+
DC_PREF_CACHE_ENABLE FALSE
|
| 333 |
+
DC_PREF_CACHE_CYCLE 0
|
| 334 |
+
PREF_INSERT_DCACHE_IMM TRUE
|
| 335 |
+
DC_PREF_CACHE_SIZE (64 * 1024)
|
| 336 |
+
DC_PREF_CACHE_ASSOC 4
|
| 337 |
+
DC_PREF_ONLY_L1HIT FALSE
|
| 338 |
+
PREF_CACHE_USE_RDY_CYCLE FALSE
|
| 339 |
+
IC_PREF_CACHE_ENABLE FALSE
|
| 340 |
+
IC_PREF_CACHE_SIZE (64 * 1024)
|
| 341 |
+
IC_PREF_CACHE_ASSOC 4
|
| 342 |
+
L1_PREF_CACHE_ENABLE FALSE
|
| 343 |
+
L1_PREF_CACHE_SIZE (1024 * 1024)
|
| 344 |
+
L1_PREF_CACHE_ASSOC 8
|
| 345 |
+
SET_OFF_PATH_CONFIRMED FALSE 1
|
| 346 |
+
USE_CONFIRMED_OFF FALSE
|
| 347 |
+
PREFCACHE_MOVE_OFFPATH FALSE
|
| 348 |
+
CACHE_STAT_ENABLE FALSE
|
| 349 |
+
PREF_DCACHE_HIT_FILL_L1 TRUE
|
| 350 |
+
PREF_ICACHE_HIT_FILL_L1 TRUE
|
| 351 |
+
CRITICAL_ACCESS_PLOT_ENABLE FALSE
|
| 352 |
+
CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat"
|
| 353 |
+
ROUND_ROBIN_TO_L1 FALSE
|
| 354 |
+
PREF_I_TOGETHER FALSE
|
| 355 |
+
ONE_MORE_CACHE_LINE_ENABLE FALSE
|
| 356 |
+
L1_STATIC_PARTITION_ENABLE 0
|
| 357 |
+
L1_STATIC_PARTITION NULL
|
| 358 |
+
L1_DYNAMIC_PARTITION_ENABLE FALSE
|
| 359 |
+
L1_DYNAMIC_PARTITION_POLICY 0
|
| 360 |
+
PARTITION_UMON_DSS_PREF_ENABLE FALSE
|
| 361 |
+
L1_CACHE_HIT_POSITION_COLLECT FALSE
|
| 362 |
+
L1_PART_ON FALSE
|
| 363 |
+
L1_PART_TRIGGER "c:1000000"
|
| 364 |
+
L1_PART_START "t:0"
|
| 365 |
+
L1_PART_WARMUP FALSE
|
| 366 |
+
L1_PART_SHADOW_WARMUP FALSE
|
| 367 |
+
L1_PART_METRIC 0
|
| 368 |
+
L1_PART_SEARCH 0
|
| 369 |
+
L1_PART_USE_STALLING TRUE
|
| 370 |
+
L1_PART_FILL_DELAY 0
|
| 371 |
+
L1_SHADOW_TAGS_MODULO 1
|
| 372 |
+
HIER_MSHR_ON FALSE
|
| 373 |
+
PERF_PRED_ENABLE FALSE
|
| 374 |
+
PERF_PRED_MECH PERF_PRED_CP
|
| 375 |
+
PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY
|
| 376 |
+
PERF_PRED_COUNT_ALL FALSE
|
| 377 |
+
PERF_PRED_COUNT_INST_MISSES TRUE
|
| 378 |
+
PERF_PRED_COUNT_PREFETCHES FALSE
|
| 379 |
+
PERF_PRED_COUNT_OFFPATH_REQS FALSE
|
| 380 |
+
PERF_PRED_COUNT_BW_REQS TRUE
|
| 381 |
+
PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE
|
| 382 |
+
PERF_PRED_SLACK_PERIOD_SIZE 32
|
| 383 |
+
PERF_PRED_REQS_FINISH_AT_FILL FALSE
|
| 384 |
+
PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE
|
| 385 |
+
PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE
|
| 386 |
+
DUMB_MODEL_AVG_REQ_DISTANCE 100
|
| 387 |
+
DUMB_MODEL_RANDOMIZE_DISTANCE FALSE
|
| 388 |
+
DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL
|
| 389 |
+
DUMB_MODEL_AVG_ROW_HITS 1
|
| 390 |
+
DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL
|
| 391 |
+
DUMB_MODEL_MLP 1
|
| 392 |
+
DUMB_MODEL_MLP_PER_CORE NULL
|
| 393 |
+
RAMULATOR_STANDARD "DDR4" DDR4
|
| 394 |
+
RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R
|
| 395 |
+
RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8
|
| 396 |
+
RAMULATOR_CHANNELS 1 1
|
| 397 |
+
RAMULATOR_RANKS 1 1
|
| 398 |
+
RAMULATOR_BANKGROUPS 4 4
|
| 399 |
+
RAMULATOR_BANKS 4 4
|
| 400 |
+
RAMULATOR_CHIP_WIDTH 8 8
|
| 401 |
+
BUS_WIDTH_IN_BYTES 8 8
|
| 402 |
+
RAMULATOR_ROWS 65536 65536
|
| 403 |
+
RAMULATOR_COLS 1024 1024
|
| 404 |
+
RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap
|
| 405 |
+
RAMULATOR_READQ_ENTRIES 32 32
|
| 406 |
+
RAMULATOR_WRITEQ_ENTRIES 32 32
|
| 407 |
+
RAMULATOR_REC_CMD_TRACE "off" FALSE
|
| 408 |
+
RAMULATOR_PRINT_CMD_TRACE "off" FALSE
|
| 409 |
+
RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on"
|
| 410 |
+
RAMULATOR_TCK 833333 833333
|
| 411 |
+
RAMULATOR_TCL 16 16
|
| 412 |
+
RAMULATOR_TCCD 6 6
|
| 413 |
+
RAMULATOR_TCCDS 4 4
|
| 414 |
+
RAMULATOR_TCCDL 6 6
|
| 415 |
+
RAMULATOR_TCWL 12 12
|
| 416 |
+
RAMULATOR_TBL 4 4
|
| 417 |
+
RAMULATOR_TWTR 9 9
|
| 418 |
+
RAMULATOR_TWTRS 3 3
|
| 419 |
+
RAMULATOR_TWTRL 9 9
|
| 420 |
+
RAMULATOR_TRP 16 16
|
| 421 |
+
RAMULATOR_TRPpb 16 16
|
| 422 |
+
RAMULATOR_TRPab 16 16
|
| 423 |
+
RAMULATOR_TRCD 16 16
|
| 424 |
+
RAMULATOR_TRCDR 16 16
|
| 425 |
+
RAMULATOR_TRCDW 16 16
|
| 426 |
+
RAMULATOR_TRAS 39 39
|
| 427 |
+
DRAM_TECH_IN_NM 32 32
|
| 428 |
+
DVFS_ON FALSE
|
| 429 |
+
DVFS_METRIC DVFS_METRIC_NUM_ELEMS
|
| 430 |
+
DVFS_CONFIGS NULL
|
| 431 |
+
DVFS_CONFIG_FILE NULL
|
| 432 |
+
DVFS_START "t:0"
|
| 433 |
+
DVFS_PERIOD "t:312500000000"
|
| 434 |
+
DVFS_LOG TRUE
|
| 435 |
+
DVFS_INDIVIDUAL_CORES FALSE
|
| 436 |
+
DVFS_CHIP_LEVEL FALSE
|
| 437 |
+
DVFS_STATIC NULL
|
| 438 |
+
DVFS_FORCE_CONFIG NULL
|
| 439 |
+
DVFS_REPLAY_CONFIG_TRACE NULL
|
| 440 |
+
DVFS_USE_ORACLE FALSE
|
| 441 |
+
DVFS_USE_BW_SHARING FALSE
|
| 442 |
+
DVFS_USE_DRAM_SHARING FALSE
|
| 443 |
+
DVFS_USE_STALL_TIME FALSE
|
| 444 |
+
DVFS_DRAM_SHARING_SOLVER_BIN NULL
|
| 445 |
+
DVFS_DRAM_SHARING_SOLVER_STRICT TRUE
|
| 446 |
+
DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95
|
| 447 |
+
DVFS_BW_SHARING_MAX_REQS 28.0
|
| 448 |
+
DVFS_BW_SHARING_MAX_RW_COST 0.25
|
| 449 |
+
DVFS_BW_SHARING_NO_PREF_STALL TRUE
|
| 450 |
+
DVFS_BW_SHARING_CRIT_STATS TRUE
|
| 451 |
+
DVFS_COUNT_L1_ACCESS_STALL FALSE
|
| 452 |
+
NUM_CORES 1
|
| 453 |
+
CHIP_CYCLE_TIME 312500 312500
|
| 454 |
+
CORE_0_CYCLE_TIME 312500
|
| 455 |
+
CORE_1_CYCLE_TIME 312500
|
| 456 |
+
CORE_2_CYCLE_TIME 312500
|
| 457 |
+
CORE_3_CYCLE_TIME 312500
|
| 458 |
+
CORE_4_CYCLE_TIME 312500
|
| 459 |
+
CORE_5_CYCLE_TIME 312500
|
| 460 |
+
CORE_6_CYCLE_TIME 312500
|
| 461 |
+
CORE_7_CYCLE_TIME 312500
|
| 462 |
+
CORE_8_CYCLE_TIME 312500
|
| 463 |
+
CORE_9_CYCLE_TIME 312500
|
| 464 |
+
CORE_10_CYCLE_TIME 312500
|
| 465 |
+
CORE_11_CYCLE_TIME 312500
|
| 466 |
+
CORE_12_CYCLE_TIME 312500
|
| 467 |
+
CORE_13_CYCLE_TIME 312500
|
| 468 |
+
CORE_14_CYCLE_TIME 312500
|
| 469 |
+
CORE_15_CYCLE_TIME 312500
|
| 470 |
+
CORE_16_CYCLE_TIME 312500
|
| 471 |
+
CORE_17_CYCLE_TIME 312500
|
| 472 |
+
CORE_18_CYCLE_TIME 312500
|
| 473 |
+
CORE_19_CYCLE_TIME 312500
|
| 474 |
+
CORE_20_CYCLE_TIME 312500
|
| 475 |
+
CORE_21_CYCLE_TIME 312500
|
| 476 |
+
CORE_22_CYCLE_TIME 312500
|
| 477 |
+
CORE_23_CYCLE_TIME 312500
|
| 478 |
+
CORE_24_CYCLE_TIME 312500
|
| 479 |
+
CORE_25_CYCLE_TIME 312500
|
| 480 |
+
CORE_26_CYCLE_TIME 312500
|
| 481 |
+
CORE_27_CYCLE_TIME 312500
|
| 482 |
+
CORE_28_CYCLE_TIME 312500
|
| 483 |
+
CORE_29_CYCLE_TIME 312500
|
| 484 |
+
CORE_30_CYCLE_TIME 312500
|
| 485 |
+
CORE_31_CYCLE_TIME 312500
|
| 486 |
+
CORE_32_CYCLE_TIME 312500
|
| 487 |
+
CORE_33_CYCLE_TIME 312500
|
| 488 |
+
CORE_34_CYCLE_TIME 312500
|
| 489 |
+
CORE_35_CYCLE_TIME 312500
|
| 490 |
+
CORE_36_CYCLE_TIME 312500
|
| 491 |
+
CORE_37_CYCLE_TIME 312500
|
| 492 |
+
CORE_38_CYCLE_TIME 312500
|
| 493 |
+
CORE_39_CYCLE_TIME 312500
|
| 494 |
+
CORE_40_CYCLE_TIME 312500
|
| 495 |
+
CORE_41_CYCLE_TIME 312500
|
| 496 |
+
CORE_42_CYCLE_TIME 312500
|
| 497 |
+
CORE_43_CYCLE_TIME 312500
|
| 498 |
+
CORE_44_CYCLE_TIME 312500
|
| 499 |
+
CORE_45_CYCLE_TIME 312500
|
| 500 |
+
CORE_46_CYCLE_TIME 312500
|
| 501 |
+
CORE_47_CYCLE_TIME 312500
|
| 502 |
+
CORE_48_CYCLE_TIME 312500
|
| 503 |
+
CORE_49_CYCLE_TIME 312500
|
| 504 |
+
CORE_50_CYCLE_TIME 312500
|
| 505 |
+
CORE_51_CYCLE_TIME 312500
|
| 506 |
+
CORE_52_CYCLE_TIME 312500
|
| 507 |
+
CORE_53_CYCLE_TIME 312500
|
| 508 |
+
CORE_54_CYCLE_TIME 312500
|
| 509 |
+
CORE_55_CYCLE_TIME 312500
|
| 510 |
+
CORE_56_CYCLE_TIME 312500
|
| 511 |
+
CORE_57_CYCLE_TIME 312500
|
| 512 |
+
CORE_58_CYCLE_TIME 312500
|
| 513 |
+
CORE_59_CYCLE_TIME 312500
|
| 514 |
+
CORE_60_CYCLE_TIME 312500
|
| 515 |
+
CORE_61_CYCLE_TIME 312500
|
| 516 |
+
CORE_62_CYCLE_TIME 312500
|
| 517 |
+
CORE_63_CYCLE_TIME 312500
|
| 518 |
+
TOPDOWN_FU_EXEC_FEW 0
|
| 519 |
+
ISSUE_WIDTH 4 6
|
| 520 |
+
RS_FILL_WIDTH 8 0
|
| 521 |
+
NODE_TABLE_SIZE 256 512
|
| 522 |
+
NODE_RET_WIDTH 4 8
|
| 523 |
+
NODE_RETIRE_RATE 10
|
| 524 |
+
DECODE_WIDTH 4 6
|
| 525 |
+
IDQ_SIZE 140 144
|
| 526 |
+
REG_RENAMING_SCHEME 0 1
|
| 527 |
+
REG_TABLE_INTEGER_PHYSICAL_SIZE 256 280
|
| 528 |
+
REG_TABLE_VECTOR_PHYSICAL_SIZE 256 332
|
| 529 |
+
REG_TABLE_INTEGER_VIRTUAL_SIZE 256
|
| 530 |
+
REG_TABLE_VECTOR_VIRTUAL_SIZE 256
|
| 531 |
+
REG_RENAMING_MOVE_ELIMINATE FALSE
|
| 532 |
+
NODE_ISSUE_QUEUE_DISPATCH_SCHEME 0
|
| 533 |
+
NODE_ISSUE_QUEUE_SCHEDULE_SCHEME 0
|
| 534 |
+
ISSUE_QUEUE_PARALLEL_PICK FALSE
|
| 535 |
+
RS_SIZES "256" 97 70 19
|
| 536 |
+
RS_CONNECTIONS "xF" b0100110011 b1000001100 b0011000000
|
| 537 |
+
FU_TYPES "0, 0, 0, 0" b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001
|
| 538 |
+
LSQ_ENABLE TRUE
|
| 539 |
+
LOAD_QUEUE_ENTRY_NUM 128
|
| 540 |
+
STORE_QUEUE_ENTRY_NUM 72
|
| 541 |
+
DECODE_CYCLES 1 5
|
| 542 |
+
MAP_CYCLES 1 5
|
| 543 |
+
ICACHE_LATENCY 3
|
| 544 |
+
EXTRA_REDIRECT_CYCLES 0
|
| 545 |
+
EXTRA_RECOVERY_CYCLES 0
|
| 546 |
+
EXTRA_CALLSYS_CYCLES 20 const
|
| 547 |
+
DIE_ON_CALLSYS FALSE
|
| 548 |
+
DIE_ON_RET_STALL_THRESH 0
|
| 549 |
+
DIE_ON_RET_STALL_CORE 0
|
| 550 |
+
DIE_ON_MEM_BLOCK_THRESH 0
|
| 551 |
+
DIE_ON_MEM_BLOCK_CORE 0
|
| 552 |
+
ICACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 553 |
+
UOP_CACHE_FETCH_ACROSS_FETCH_TARGET TRUE
|
| 554 |
+
FETCH_OFF_PATH_OPS TRUE 1
|
| 555 |
+
WP_COLLECT_STATS TRUE
|
| 556 |
+
OP_INV_DELAY 1
|
| 557 |
+
OP_NOP_DELAY 1
|
| 558 |
+
OP_CF_DELAY 1
|
| 559 |
+
OP_MOV_DELAY 1
|
| 560 |
+
OP_CMOV_DELAY 1
|
| 561 |
+
OP_LDA_DELAY 1
|
| 562 |
+
OP_ILD_DELAY 1
|
| 563 |
+
OP_IST_DELAY 1
|
| 564 |
+
OP_IADD_DELAY 1
|
| 565 |
+
OP_IMUL_DELAY 3
|
| 566 |
+
OP_IDIV_DELAY -20
|
| 567 |
+
OP_ICMP_DELAY 1
|
| 568 |
+
OP_LOGIC_DELAY 1
|
| 569 |
+
OP_SHIFT_DELAY 1
|
| 570 |
+
OP_FLD_DELAY 1
|
| 571 |
+
OP_FST_DELAY 1
|
| 572 |
+
OP_FCVT_DELAY 3
|
| 573 |
+
OP_FADD_DELAY 3
|
| 574 |
+
OP_FMUL_DELAY 5
|
| 575 |
+
OP_FMA_DELAY 5
|
| 576 |
+
OP_FDIV_DELAY -20
|
| 577 |
+
OP_FCMP_DELAY 3
|
| 578 |
+
OP_FCMOV_DELAY 1
|
| 579 |
+
OP_GATHER_DELAY 12
|
| 580 |
+
OP_SCATTER_DELAY 18
|
| 581 |
+
OP_PIPELINED_FAST_DELAY 2
|
| 582 |
+
OP_PIPELINED_MEDIUM_DELAY 5
|
| 583 |
+
OP_PIPELINED_SLOW_DELAY 10
|
| 584 |
+
OP_NOTPIPELINED_MEDIUM_DELAY -5
|
| 585 |
+
OP_NOTPIPELINED_SLOW_DELAY -20
|
| 586 |
+
OP_NOTPIPELINED_VERY_SLOW_DELAY -100
|
| 587 |
+
UNIFORM_OP_DELAY 0
|
| 588 |
+
STALL_ON_WAIT_MEM TRUE
|
| 589 |
+
STORES_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 590 |
+
PREFS_DO_NOT_BLOCK_WINDOW FALSE 1
|
| 591 |
+
OBEY_REG_DEP TRUE
|
| 592 |
+
TRACK_L1_MISS_DEPS FALSE
|
| 593 |
+
CBP_TRACE_R0 NULL /dev/shm/baseline/traces/.staging/tsp-164844/raw_trace/drmemtrace.tsp.164856.4389.dir/trace/drmemtrace.tsp.164856.1160.trace.zip
|
| 594 |
+
CBP_TRACE_R1 NULL
|
| 595 |
+
CBP_TRACE_R2 NULL
|
| 596 |
+
CBP_TRACE_R3 NULL
|
| 597 |
+
CBP_TRACE_R4 NULL
|
| 598 |
+
CBP_TRACE_R5 NULL
|
| 599 |
+
CBP_TRACE_R6 NULL
|
| 600 |
+
CBP_TRACE_R7 NULL
|
| 601 |
+
CBP_TRACE_R8 NULL
|
| 602 |
+
CBP_TRACE_R9 NULL
|
| 603 |
+
CBP_TRACE_R10 NULL
|
| 604 |
+
CBP_TRACE_R11 NULL
|
| 605 |
+
CBP_TRACE_R12 NULL
|
| 606 |
+
CBP_TRACE_R13 NULL
|
| 607 |
+
CBP_TRACE_R14 NULL
|
| 608 |
+
CBP_TRACE_R15 NULL
|
| 609 |
+
CBP_TRACE_R16 NULL
|
| 610 |
+
CBP_TRACE_R17 NULL
|
| 611 |
+
CBP_TRACE_R18 NULL
|
| 612 |
+
CBP_TRACE_R19 NULL
|
| 613 |
+
CBP_TRACE_R20 NULL
|
| 614 |
+
CBP_TRACE_R21 NULL
|
| 615 |
+
CBP_TRACE_R22 NULL
|
| 616 |
+
CBP_TRACE_R23 NULL
|
| 617 |
+
CBP_TRACE_R24 NULL
|
| 618 |
+
CBP_TRACE_R25 NULL
|
| 619 |
+
CBP_TRACE_R26 NULL
|
| 620 |
+
CBP_TRACE_R27 NULL
|
| 621 |
+
CBP_TRACE_R28 NULL
|
| 622 |
+
CBP_TRACE_R29 NULL
|
| 623 |
+
CBP_TRACE_R30 NULL
|
| 624 |
+
CBP_TRACE_R31 NULL
|
| 625 |
+
CBP_TRACE_R32 NULL
|
| 626 |
+
CBP_TRACE_R33 NULL
|
| 627 |
+
CBP_TRACE_R34 NULL
|
| 628 |
+
CBP_TRACE_R35 NULL
|
| 629 |
+
CBP_TRACE_R36 NULL
|
| 630 |
+
CBP_TRACE_R37 NULL
|
| 631 |
+
CBP_TRACE_R38 NULL
|
| 632 |
+
CBP_TRACE_R39 NULL
|
| 633 |
+
CBP_TRACE_R40 NULL
|
| 634 |
+
CBP_TRACE_R41 NULL
|
| 635 |
+
CBP_TRACE_R42 NULL
|
| 636 |
+
CBP_TRACE_R43 NULL
|
| 637 |
+
CBP_TRACE_R44 NULL
|
| 638 |
+
CBP_TRACE_R45 NULL
|
| 639 |
+
CBP_TRACE_R46 NULL
|
| 640 |
+
CBP_TRACE_R47 NULL
|
| 641 |
+
CBP_TRACE_R48 NULL
|
| 642 |
+
CBP_TRACE_R49 NULL
|
| 643 |
+
CBP_TRACE_R50 NULL
|
| 644 |
+
CBP_TRACE_R51 NULL
|
| 645 |
+
CBP_TRACE_R52 NULL
|
| 646 |
+
CBP_TRACE_R53 NULL
|
| 647 |
+
CBP_TRACE_R54 NULL
|
| 648 |
+
CBP_TRACE_R55 NULL
|
| 649 |
+
CBP_TRACE_R56 NULL
|
| 650 |
+
CBP_TRACE_R57 NULL
|
| 651 |
+
CBP_TRACE_R58 NULL
|
| 652 |
+
CBP_TRACE_R59 NULL
|
| 653 |
+
CBP_TRACE_R60 NULL
|
| 654 |
+
CBP_TRACE_R61 NULL
|
| 655 |
+
CBP_TRACE_R62 NULL
|
| 656 |
+
CBP_TRACE_R63 NULL
|
| 657 |
+
FE_FTQ_BLOCK_NUM 32
|
| 658 |
+
FE_FTQ_TAKEN_CFS_PER_CYCLE 2
|
| 659 |
+
FE_FTQ_FT_PER_CYCLE 1
|
| 660 |
+
DUMB_CORE_ON FALSE
|
| 661 |
+
DUMB_CORE 1
|
| 662 |
+
DCACHE_MISS_RATE 10
|
| 663 |
+
L1_MISS_RATE 10
|
| 664 |
+
TRACE_BUF_SIZE 0
|
| 665 |
+
PERFECT_CONFIDENCE FALSE
|
| 666 |
+
CONFIDENCE_ENABLE FALSE
|
| 667 |
+
CONFIDENCE_MECH 0
|
| 668 |
+
CONF_OFF_PATH_THRESHOLD 15
|
| 669 |
+
CONF_OFF_PATH_INC 5
|
| 670 |
+
CONF_BTB_MISS_BP_TAKEN FALSE
|
| 671 |
+
CONF_IPC_RATE_CONF FALSE
|
| 672 |
+
CONF_BTB_MISS_BP_TAKEN_THRESHOLD 0
|
| 673 |
+
CONF_BTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 674 |
+
CONF_IBTB_MISS_RATE_CYCLES_THRESHOLD 1.0
|
| 675 |
+
CONF_MISFETCH_RATE_CYCLES_THRESHOLD 1.0
|
| 676 |
+
CONF_MISPRED_RATE_CYCLES_THRESHOLD 1.0
|
| 677 |
+
CONF_BTB_MISS_SAMPLE_RATE 100000
|
| 678 |
+
CONF_IBTB_MISS_SAMPLE_RATE 100000
|
| 679 |
+
CONF_MISFETCH_SAMPLE_RATE 100000
|
| 680 |
+
CONF_MISPRED_SAMPLE_RATE 100000
|
| 681 |
+
CONF_IPC_SAMPLE_RATE 100000
|
| 682 |
+
CONF_BTB_MISS_RATE_WEIGHT 200
|
| 683 |
+
CONF_BTB_MISS_BP_TAKEN_CONF TRUE
|
| 684 |
+
CONF_IBTB_MISS_BP_TAKEN_CONF TRUE
|
| 685 |
+
CONF_BTB_MISS_RATE_CONF TRUE
|
| 686 |
+
CONF_IBTB_MISS_RATE_CONF TRUE
|
| 687 |
+
CONF_MISFETCH_RATE_CONF TRUE
|
| 688 |
+
CONF_MISPRED_RATE_CONF TRUE
|
| 689 |
+
CONF_INV_BP_CONF TRUE
|
| 690 |
+
CONF_PERFECT_BTB_MISS_CONF FALSE
|
| 691 |
+
CONF_PERFECT_IBTB_MISS_CONF FALSE
|
| 692 |
+
CONF_PERFECT_MISFETCH_CONF FALSE
|
| 693 |
+
CONF_PERFECT_MISPRED_CONF FALSE
|
| 694 |
+
CONF_LOG_DFE_TO_REC FALSE
|
| 695 |
+
CONF_LOG_PHASE_CYCLES FALSE
|
| 696 |
+
NUM_BPS 1
|
| 697 |
+
DFE0_TRIGGER_POLICY 0
|
| 698 |
+
DFE1_TRIGGER_POLICY 1
|
| 699 |
+
DFE2_TRIGGER_POLICY 1
|
| 700 |
+
DFE3_TRIGGER_POLICY 1
|
| 701 |
+
DFE4_TRIGGER_POLICY 1
|
| 702 |
+
DFE0_STOP_POLICY 0
|
| 703 |
+
DFE1_STOP_POLICY 1
|
| 704 |
+
DFE2_STOP_POLICY 1
|
| 705 |
+
DFE3_STOP_POLICY 1
|
| 706 |
+
DFE4_STOP_POLICY 1
|
| 707 |
+
LOOKAHEAD_BUF_SIZE 0
|
| 708 |
+
DEBUG_CYCLE_START 0 0
|
| 709 |
+
DEBUG_CYCLE_STOP 0 -1
|
| 710 |
+
DEBUG_TIME_START 0
|
| 711 |
+
DEBUG_TIME_STOP 0
|
| 712 |
+
DEBUG_INST_START 0 0
|
| 713 |
+
DEBUG_INST_STOP 0 -1
|
| 714 |
+
DEBUG_OP_START 0
|
| 715 |
+
DEBUG_OP_STOP 0
|
| 716 |
+
DEBUG_CACHE_LIB FALSE
|
| 717 |
+
DEBUG_HASH_LIB FALSE
|
| 718 |
+
DEBUG_LIST_LIB FALSE
|
| 719 |
+
DEBUG_PORT_LIB FALSE
|
| 720 |
+
DEBUG_BUS_LIB FALSE
|
| 721 |
+
DEBUG_OP_POOL FALSE
|
| 722 |
+
DEBUG_ORACLE FALSE
|
| 723 |
+
DEBUG_FRONTEND FALSE
|
| 724 |
+
DEBUG_ADDR_TRANS FALSE
|
| 725 |
+
DEBUG_BP FALSE
|
| 726 |
+
DEBUG_BP_DIR FALSE
|
| 727 |
+
DEBUG_BTB FALSE
|
| 728 |
+
DEBUG_CRS FALSE
|
| 729 |
+
DEBUG_MAP FALSE
|
| 730 |
+
DEBUG_MEMORY FALSE
|
| 731 |
+
DEBUG_REPLAY FALSE
|
| 732 |
+
DEBUG_FREQ FALSE
|
| 733 |
+
DEBUG_MODEL FALSE
|
| 734 |
+
DEBUG_THREAD FALSE
|
| 735 |
+
DEBUG_DECOUPLED_FE FALSE
|
| 736 |
+
DEBUG_CONF FALSE
|
| 737 |
+
DEBUG_ICACHE_STAGE FALSE
|
| 738 |
+
DEBUG_DECODE_STAGE FALSE
|
| 739 |
+
DEBUG_CPP_CACHE FALSE
|
| 740 |
+
DEBUG_UOP_CACHE FALSE
|
| 741 |
+
DEBUG_UOP_QUEUE_STAGE FALSE
|
| 742 |
+
DEBUG_IDQ_STAGE FALSE
|
| 743 |
+
DEBUG_MAP_STAGE FALSE
|
| 744 |
+
DEBUG_NODE_STAGE FALSE
|
| 745 |
+
DEBUG_EXEC_STAGE FALSE
|
| 746 |
+
DEBUG_DCACHE_STAGE FALSE
|
| 747 |
+
DEBUG_RETIRED_UOPS FALSE
|
| 748 |
+
DEBUG_EXC_INSERTS FALSE
|
| 749 |
+
DEBUG_BP_CONF FALSE
|
| 750 |
+
DEBUG_ONPATH_CONF FALSE
|
| 751 |
+
DEBUG_STREAM FALSE
|
| 752 |
+
DEBUG_STREAM_MEM FALSE
|
| 753 |
+
DEBUG_WAY FALSE
|
| 754 |
+
DEBUG_L2MARKV FALSE
|
| 755 |
+
DEBUG_L2L1PREF FALSE
|
| 756 |
+
DEBUG_PERF_PRED FALSE
|
| 757 |
+
DEBUG_POWER_UTILS FALSE
|
| 758 |
+
DEBUG_DVFS FALSE
|
| 759 |
+
DEBUG_TRACE_READ FALSE
|
| 760 |
+
DEBUG_INST_FIELDS FALSE
|
| 761 |
+
DEBUG_OP_FIELDS FALSE
|
| 762 |
+
DEBUG_PIN_EXEC_DRIVEN FALSE
|
| 763 |
+
DEBUG_CACHE_PART FALSE
|
| 764 |
+
DEBUG_OPTIMIZER2 FALSE
|
| 765 |
+
DEBUG_PREF FALSE
|
| 766 |
+
DEBUG_FDIP FALSE
|
| 767 |
+
DEBUG_EIP FALSE
|
| 768 |
+
DEBUG_DJOLT FALSE
|
| 769 |
+
DEBUG_FNLMMA FALSE
|
| 770 |
+
PERFECT_BP FALSE
|
| 771 |
+
PERFECT_BTB FALSE
|
| 772 |
+
PERFECT_IBP FALSE
|
| 773 |
+
PERFECT_CRS FALSE
|
| 774 |
+
PERFECT_CBR_BTB FALSE
|
| 775 |
+
PERFECT_NT_BTB FALSE 0 # deprecated, effectively always true.
|
| 776 |
+
CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle
|
| 777 |
+
UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
|
| 778 |
+
BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec.
|
| 779 |
+
BP_MECH TAGE64K_BP tage64k
|
| 780 |
+
BP_MECH_L0 BIMODAL_BP
|
| 781 |
+
BP_L0_LATENCY 1
|
| 782 |
+
BP_MAIN_LATENCY 3
|
| 783 |
+
BIMODAL_ENTRIES (4 * 1024)
|
| 784 |
+
HIST_LENGTH 16
|
| 785 |
+
PHT_CTR_BITS 2 const
|
| 786 |
+
BHT_ENTRIES (4 * 1024)
|
| 787 |
+
BHT_ASSOC 4
|
| 788 |
+
HYBRIDS_INDEX_LENGTH 16
|
| 789 |
+
HYBRIDG_HIST_LENGTH 16
|
| 790 |
+
HYBRIDP_HIST_LENGTH 16
|
| 791 |
+
FILTER_INDEX_LENGTH 16
|
| 792 |
+
USE_FILTER FALSE
|
| 793 |
+
INF_HYBRIDGP FALSE
|
| 794 |
+
BP_HASH_TOS FALSE
|
| 795 |
+
IBTB_HASH_TOS FALSE
|
| 796 |
+
BTB_MECH GENERIC_BTB generic
|
| 797 |
+
BTB_ENTRIES 12288 12288
|
| 798 |
+
BTB_ASSOC 4 4
|
| 799 |
+
BTB_NUM_BRSLOT 1
|
| 800 |
+
BTB_BLOCK_SIZE 64
|
| 801 |
+
BTB_OFF_PATH_WRITES TRUE 1
|
| 802 |
+
BTB_MAIN_LATENCY 3 3
|
| 803 |
+
BTB_L0_PRESENT FALSE 1
|
| 804 |
+
BTB_L0_ENTRIES 128 128
|
| 805 |
+
BTB_L0_ASSOC 4 4
|
| 806 |
+
BTB_L0_LATENCY 1 1
|
| 807 |
+
BTB_L1_PRESENT FALSE 1
|
| 808 |
+
BTB_L1_ENTRIES 6144 6144
|
| 809 |
+
BTB_L1_ASSOC 4 4
|
| 810 |
+
BTB_L1_LATENCY 2 2
|
| 811 |
+
ENABLE_CRS TRUE 1
|
| 812 |
+
CRS_ENTRIES 32 128
|
| 813 |
+
CRS_REALISTIC 0 1
|
| 814 |
+
ENABLE_IBP TRUE 1 # Enable the indirect branch predictor
|
| 815 |
+
USE_PAT_HIST TRUE
|
| 816 |
+
IBTB_MECH 1 tc_tagged
|
| 817 |
+
IBTB_HIST_LENGTH 16
|
| 818 |
+
IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb.
|
| 819 |
+
TARGETS_IN_HIST 4
|
| 820 |
+
TC_ENTRIES (4 * 1024) 4096
|
| 821 |
+
TC_ASSOC 4 4
|
| 822 |
+
NUM_CORR_BRANCHES 3
|
| 823 |
+
SEL_HIST_BP_ENTRIES 8192
|
| 824 |
+
SEL_HIST_LENGTH 16
|
| 825 |
+
SEL_HIST_DYN_CNT_TH 16
|
| 826 |
+
SEL_HIST_MISPRED_TH 4
|
| 827 |
+
ENABLE_BP_CONF FALSE
|
| 828 |
+
CONF_MECH 0
|
| 829 |
+
PERF_BP_CONF_PRED FALSE
|
| 830 |
+
BPC_BITS 16
|
| 831 |
+
BPC_MECH 1
|
| 832 |
+
BPC_CTR_RESET TRUE
|
| 833 |
+
BPC_CIT_BITS 8
|
| 834 |
+
BPC_CIT_TH 50
|
| 835 |
+
BPC_CTR_BITS 3
|
| 836 |
+
OPC_COUNT_ZEROS FALSE
|
| 837 |
+
OPC_COUNT_THRESH 10
|
| 838 |
+
INF_LOOP FALSE
|
| 839 |
+
INF_LOOP_BUCKETS 811
|
| 840 |
+
LOOP_ENTRIES (4 * 1024)
|
| 841 |
+
LOOP_ASSOC 4
|
| 842 |
+
LOOP_COUNT_MAX 127
|
| 843 |
+
LOOP_REPEAT_MAX 15
|
| 844 |
+
KNOB_PRINT_BRINFO FALSE
|
| 845 |
+
BR_MISPRED_FILE NULL
|
| 846 |
+
SPEC_LEVEL 3
|
| 847 |
+
RANDOM_DETERMINISTIC TRUE
|
| 848 |
+
TAGESCL64KB_SC TRUE
|
| 849 |
+
TAGESCL64KB_LOOP TRUE
|
| 850 |
+
TAGESCL64KB_ALT TRUE
|
| 851 |
+
CONF_PERCEPTRON_TH 0
|
| 852 |
+
CONF_PERCEPTRON_CTR_BITS 8
|
| 853 |
+
CONF_PERCEPTRON_ENTRIES 127
|
| 854 |
+
CONF_PERCEPTRON_THRESH_OVRD 0
|
| 855 |
+
CONF_HIST_LENGTH 32
|
| 856 |
+
PERCEPTRON_CONF_USE_CONF FALSE
|
| 857 |
+
PERCEPTRON_CONF_TRAIN_HIS FALSE
|
| 858 |
+
PERCEPTRON_CONF_TRAIN_CONF FALSE
|
| 859 |
+
PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE
|
| 860 |
+
PERCEPTRON_TRAIN_MISP_FACTOR 1
|
| 861 |
+
PERCEPTRON_TRAIN_CORR_FACTOR 1
|
| 862 |
+
PERCEPTRON_CONF_HIS_BOTH FALSE
|
| 863 |
+
PERCEPTRON_CONF_HIS_BOTH_LENGTH 4
|
| 864 |
+
MTAGE_REALISTIC_SC_40K FALSE
|
| 865 |
+
MTAGE_REALISTIC_SC_100K FALSE
|
| 866 |
+
H2P_TABLE_BUCKETS 16384
|
| 867 |
+
H2P_MIN_EXEC 5000
|
| 868 |
+
H2P_MIN_MISPRED 333
|
| 869 |
+
H2P_MISPRED_RATIO_PERMIL 10
|
| 870 |
+
H2P_TRACK_CBR TRUE
|
| 871 |
+
H2P_TRACK_REP TRUE
|
| 872 |
+
H2P_TRACK_CALL FALSE
|
| 873 |
+
H2P_TRACK_IBR FALSE
|
| 874 |
+
H2P_TRACK_ICALL FALSE
|
| 875 |
+
H2P_TRACK_RET FALSE
|
| 876 |
+
POWER_INTF_ON FALSE
|
| 877 |
+
POWER_INTF_ENABLE_SCALING FALSE
|
| 878 |
+
POWER_INTF_EXEC "power/power_intf.py"
|
| 879 |
+
POWER_INTF_REF_CHIP_TECH_NM 22
|
| 880 |
+
POWER_INTF_REF_CHIP_FREQ (3.2e9)
|
| 881 |
+
POWER_INTF_REF_MEMORY_FREQ (0.8e9)
|
| 882 |
+
POWER_OTHER (0.0)
|
| 883 |
+
PREF_STREAM_ON FALSE 1
|
| 884 |
+
PREF_STREAM_PER_CORE_ENABLE FALSE
|
| 885 |
+
STREAM_BUFFER_N 16
|
| 886 |
+
STREAM_PREFETCH_N 2 4
|
| 887 |
+
STREAM_START_DIS 5 1
|
| 888 |
+
STREAM_LENGTH 16 64
|
| 889 |
+
STREAM_FULL_N 1
|
| 890 |
+
STREAM_TRAIN_LENGTH 16
|
| 891 |
+
STREAM_TRAIN_NUM 1 4
|
| 892 |
+
PREF_ACC_USE_CACHE FALSE
|
| 893 |
+
STREAM_STALL_ON_QUEUE_FULL FALSE
|
| 894 |
+
PREF_SCHEDULE_NUM 4
|
| 895 |
+
TRAIN_FILTER_SIZE 32
|
| 896 |
+
PREF_REQ_Q_SIZE 64
|
| 897 |
+
STREAM_CREATE_ON_DC_MISS FALSE 0
|
| 898 |
+
STREAM_CREATE_ON_L1_MISS TRUE 1
|
| 899 |
+
STREAM_TRAIN_ON_WRONGPATH TRUE
|
| 900 |
+
STREAM_CREATE_ON_WRONGPATH TRUE
|
| 901 |
+
STREAM_PREF_INTO_DCACHE FALSE
|
| 902 |
+
REMOVE_REDUNDANT_STREAM FALSE
|
| 903 |
+
L2HIT_STREAM_SCHEDULE_NUM 4
|
| 904 |
+
PREF_REQ_QUEUE_FILTER_ON FALSE
|
| 905 |
+
HW_PREF_HIT_TRAIN_STREAM FALSE
|
| 906 |
+
L2HIT_STREAM_BUFFER_N 32
|
| 907 |
+
L2HIT_STREAM_PREFETCH_N 2
|
| 908 |
+
L2HIT_STREAM_START_DIS 2
|
| 909 |
+
L2HIT_STREAM_LENGTH 8
|
| 910 |
+
L2HIT_PREF_REQ_Q_SIZE 128
|
| 911 |
+
L2HIT_L2ACCESS_REQ_Q_SIZE 64
|
| 912 |
+
PREF_STREAM_ACCPERSTREAM FALSE
|
| 913 |
+
PREF_ACC_DISTANCE_10 128
|
| 914 |
+
PREF_FRAMEWORK_ON FALSE 1
|
| 915 |
+
PREF_TRACE_ON FALSE
|
| 916 |
+
PREF_UMLC_ON FALSE
|
| 917 |
+
PREF_UL1_ON TRUE
|
| 918 |
+
PREF_DL0REQ_QUEUE_SIZE 32
|
| 919 |
+
PREF_UMLC_REQ_QUEUE_SIZE 64
|
| 920 |
+
PREF_UL1REQ_QUEUE_SIZE 128
|
| 921 |
+
PREF_SHARED_QUEUES TRUE
|
| 922 |
+
PREF_DL0_MISS_ON TRUE
|
| 923 |
+
PREF_DL0_HIT_ON TRUE
|
| 924 |
+
PREF_DL0REQ_QUEUE_FILTER_ON TRUE
|
| 925 |
+
PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE
|
| 926 |
+
PREF_UL1REQ_QUEUE_FILTER_ON TRUE
|
| 927 |
+
PREF_DL0REQ_ADD_FILTER_ON TRUE
|
| 928 |
+
PREF_UMLC_REQ_ADD_FILTER_ON TRUE
|
| 929 |
+
PREF_UL1REQ_ADD_FILTER_ON TRUE
|
| 930 |
+
PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 931 |
+
PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE
|
| 932 |
+
PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1
|
| 933 |
+
PREF_DL0SCHEDULE_NUM 4
|
| 934 |
+
PREF_UMLC_SCHEDULE_NUM 4
|
| 935 |
+
PREF_UL1SCHEDULE_NUM 4
|
| 936 |
+
PREF_L1Q_DEMAND_RESERVE 0
|
| 937 |
+
PREF_REPORT_PREF_MATCH_AS_MISS FALSE
|
| 938 |
+
PREF_REPORT_PREF_MATCH_AS_HIT TRUE
|
| 939 |
+
PREF_UPDATE_ON_WRONGPATH TRUE
|
| 940 |
+
PREF_TRAIN_ON_PREF_MISSES FALSE 0
|
| 941 |
+
PREF_ORACLE_TRAIN_ON FALSE 0
|
| 942 |
+
PREF_REQ_DROP FALSE
|
| 943 |
+
PREF_THROTTLE_ON FALSE
|
| 944 |
+
PREF_THROTTLEFB_ON FALSE 1
|
| 945 |
+
PREF_ACC_THRESH_1 0.90 0.75
|
| 946 |
+
PREF_ACC_THRESH_2 0.70 0.4
|
| 947 |
+
PREF_ACC_THRESH_3 0.60 0.4
|
| 948 |
+
PREF_ACC_THRESH_4 0.40
|
| 949 |
+
PREF_UPDATE_INTERVAL 0 8192
|
| 950 |
+
PREF_ANALYZE_LOAD FALSE
|
| 951 |
+
PREF_POL_THRESH_1 0.25
|
| 952 |
+
PREF_POL_THRESH_2 0.10
|
| 953 |
+
PREF_POLBV_ON FALSE
|
| 954 |
+
PREF_POLBV_SIZE 1024
|
| 955 |
+
PREF_TIMELY_THRESH 0.05 0.01
|
| 956 |
+
PREF_POLPF_THRESH 0.01 0.005
|
| 957 |
+
PREF_DEGFB_USEONLYACC FALSE
|
| 958 |
+
PREF_DEGFB_USEONLYPOL FALSE
|
| 959 |
+
PREF_DEGFB_USEONLYLATE FALSE
|
| 960 |
+
PREF_TIMELY_THRESH_2 0.005
|
| 961 |
+
PREF_DEGFB_STATPHASEFILE FALSE
|
| 962 |
+
PREF_MAX_DEGFB 4
|
| 963 |
+
PREF_DHAL FALSE
|
| 964 |
+
PREF_DHAL_SENTTHRESH 16
|
| 965 |
+
PREF_DHAL_USETHRESH_MAX 12
|
| 966 |
+
PREF_DHAL_USETHRESH_MIN2 8
|
| 967 |
+
PREF_DHAL_USETHRESH_MIN1 4
|
| 968 |
+
PREF_DHAL_MAXDEG 64
|
| 969 |
+
PREF_HFILTER_ON FALSE
|
| 970 |
+
PREF_HFILTER_INDEX_BITS 12
|
| 971 |
+
PREF_HFILTER_USE_PC FALSE
|
| 972 |
+
PREF_HFILTER_PRED_USELESS_THRES 2
|
| 973 |
+
PREF_HFILTER_RESET_ENABLE FALSE
|
| 974 |
+
PREF_HFILTER_RESET_INTERVAL 100000
|
| 975 |
+
EIP_ENABLE 0
|
| 976 |
+
L1I_ENTANGLED_TABLE_INDEX_BITS 9
|
| 977 |
+
L1I_ENTANGLED_TABLE_WAYS 16
|
| 978 |
+
DJOLT_ENABLE 0
|
| 979 |
+
FNLMMA_ENABLE 0
|
| 980 |
+
FDIP_ENABLE 1
|
| 981 |
+
FDIP_ALWAYS_PREFETCH FALSE
|
| 982 |
+
PERFECT_FDIP FALSE
|
| 983 |
+
IPRF_MAX_FTQ_ENTRY_CYC 2
|
| 984 |
+
FDIP_BLOOM_FILTER FALSE
|
| 985 |
+
FDIP_BLOOM_ENTRIES 4000
|
| 986 |
+
FDIP_BLOOM2_ENTRIES 1000
|
| 987 |
+
FDIP_BLOOM4_ENTRIES 1000
|
| 988 |
+
FDIP_BLOOM_SIZE 16384
|
| 989 |
+
FDIP_BLOOM_HASHES 6
|
| 990 |
+
FDIP_BLOOM_CLEAR_UNUSEFUL_RATIO 0.95
|
| 991 |
+
FDIP_BLOOM_CLEAR_CYC_PERIOD 10000
|
| 992 |
+
FDIP_UTILITY_HASH_ENABLE 0
|
| 993 |
+
FDIP_UTILITY_PREF_POLICY 0
|
| 994 |
+
FDIP_ADJUSTABLE_FTQ 0
|
| 995 |
+
FDIP_ADJUSTABLE_FTQ_CYC 100000
|
| 996 |
+
UTILITY_RATIO_THRESHOLD 0.58
|
| 997 |
+
TIMELINESS_RATIO_THRESHOLD 0.82
|
| 998 |
+
FDIP_PREF_NO_LATENCY FALSE
|
| 999 |
+
UDP_USEFUL_THRESHOLD 0
|
| 1000 |
+
UDP_WEIGHT_USEFUL 4
|
| 1001 |
+
UDP_WEIGHT_UNUSEFUL 1
|
| 1002 |
+
UDP_WEIGHT_POSITIVE_SATURATION 2147483647
|
| 1003 |
+
FDIP_GHIST_HASHING FALSE
|
| 1004 |
+
FDIP_UTILITY_ONLY_TRAIN_OFF_PATH FALSE
|
| 1005 |
+
FDIP_GHIST_BITS 8
|
| 1006 |
+
UFTQ_MIN_FTQ_BLOCK_NUM 4
|
| 1007 |
+
UFTQ_MAX_FTQ_BLOCK_NUM 64
|
| 1008 |
+
FDIP_SENIORITY_FTQ_HOLD_CYC 30000
|
| 1009 |
+
FDIP_PERFECT_PREFETCH FALSE
|
| 1010 |
+
FDIP_FREEZE_AT_MEM_BUF_LIMIT TRUE
|
| 1011 |
+
FDIP_DUAL_PATH_PREF_IC_ENABLE FALSE
|
| 1012 |
+
FDIP_DUAL_PATH_PREF_UOC_ENABLE FALSE
|
| 1013 |
+
TOP_MISPRED_BR_FILEPATH "br_resteer_coverage.csv"
|
| 1014 |
+
TOP_MISPRED_BR_RESTEER_COVERAGE 0
|
| 1015 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_ENABLE FALSE
|
| 1016 |
+
FDIP_DUAL_PATH_PREF_UOC_ONLINE_MISPRED_THRESHOLD 1
|
| 1017 |
+
FDIP_PRINT_CL_INFO FALSE
|
| 1018 |
+
BRANCH_MISPREDICTION_TABLE_SIZE 0
|
| 1019 |
+
UOC_PREF FALSE
|
| 1020 |
+
UOC_ORACLE_PREF FALSE
|
| 1021 |
+
UOC_ZERO_LATENCY_PREF FALSE
|
| 1022 |
+
L2L1PREF_ON FALSE
|
| 1023 |
+
L2WAY_PREF FALSE
|
| 1024 |
+
L2MARKV_PREF_ON FALSE
|
| 1025 |
+
L2NEXT_PREF_ON FALSE
|
| 1026 |
+
L2HIT_STREAM_PREF_ON FALSE
|
| 1027 |
+
L2L1_DC_HIT_TRAIN FALSE
|
| 1028 |
+
L1_HIT_DUMP_FILE_ON FALSE
|
| 1029 |
+
L1_HIT_DUMP_WO_TXT FALSE
|
| 1030 |
+
L1_HIT_DUMPFILE "l1hit_dump.out"
|
| 1031 |
+
IDEAL_L2_L1_PREFETCHER FALSE
|
| 1032 |
+
IDEAL_L2_ICACHE_PREFETCHER FALSE
|
| 1033 |
+
L1WAY_PREF_SEND_QUEUE 4
|
| 1034 |
+
L1PREF_REQ_QUEUE_SIZE 1024
|
| 1035 |
+
L1PREF_IMMEDIATE FALSE
|
| 1036 |
+
L1WAY_PREF_TIMER_DIS 1000
|
| 1037 |
+
L1MARKV_PREF_SEND_QUEUE 4
|
| 1038 |
+
L1PREF_MARKV_REQ_QUEUE_SIZE 1024
|
| 1039 |
+
MARKV_L2ACCESS_REQ_Q_SIZE 64
|
| 1040 |
+
L1MARKV_PREF_IMMEDIATE FALSE
|
| 1041 |
+
L1MARKV_PREF_TIMER_DIS 1
|
| 1042 |
+
L2L1_HIT_TRAIN TRUE
|
| 1043 |
+
L1MARKV_REQ_TH 1
|
| 1044 |
+
L2L1_IMMEDIATE_PREF_CACHE FALSE
|
| 1045 |
+
L2L1_FILL_PREF_CACHE FALSE
|
| 1046 |
+
L2L1_L2_HIT_STAT FALSE
|
| 1047 |
+
PREF_GHB_ON FALSE
|
| 1048 |
+
DEBUG_PREF_GHB FALSE
|
| 1049 |
+
PREF_GHB_BUFFER_N 1024
|
| 1050 |
+
PREF_GHB_INDEX_N 128
|
| 1051 |
+
PREF_GHB_CZONE_BITS 12
|
| 1052 |
+
PREF_GHB_DEGREE 16
|
| 1053 |
+
PREF_GHB_MAX_DEGREE 32
|
| 1054 |
+
PREF_STRIDE_ON FALSE
|
| 1055 |
+
DEBUG_PREF_STRIDE FALSE
|
| 1056 |
+
PREF_STRIDE_TABLE_N 1024
|
| 1057 |
+
PREF_STRIDE_REGION_BITS 16
|
| 1058 |
+
PREF_STRIDE_DEGREE 4
|
| 1059 |
+
PREF_STRIDE_DISTANCE 16
|
| 1060 |
+
PREF_STRIDE_STARTDISTANCE 1
|
| 1061 |
+
PREF_STRIDE_SINGLE_THRESH 6
|
| 1062 |
+
PREF_STRIDE_MULTI_THRESH 6
|
| 1063 |
+
PREF_STRIDE_SINGLE_STRIDE_MODE FALSE
|
| 1064 |
+
PREF_STRIDEPC_ON FALSE
|
| 1065 |
+
DEBUG_PREF_STRIDEPC FALSE
|
| 1066 |
+
PREF_STRIDEPC_TABLE_N 1024
|
| 1067 |
+
PREF_STRIDEPC_DEGREE 4
|
| 1068 |
+
PREF_STRIDEPC_DISTANCE 16
|
| 1069 |
+
PREF_STRIDEPC_USELOADADDR FALSE
|
| 1070 |
+
PREF_STRIDEPC_TRAINNUM 2
|
| 1071 |
+
PREF_STRIDEPC_STARTDIS 4
|
| 1072 |
+
PREF_PHASE_ON FALSE
|
| 1073 |
+
PREF_PHASE_STUDY FALSE
|
| 1074 |
+
DEBUG_PREF_PHASE FALSE
|
| 1075 |
+
PREF_PHASE_PRIME_HASH 16381
|
| 1076 |
+
PREF_PHASE_INFOSIZE 16384
|
| 1077 |
+
PREF_PHASE_LOG2REGIONSIZE 12
|
| 1078 |
+
PREF_PHASE_REGIONENTRIES 64
|
| 1079 |
+
PREF_PHASE_TRACKEDREGIONS 32
|
| 1080 |
+
PREF_PHASE_INTERVAL 100000
|
| 1081 |
+
PREF_PHASE_TABLE_SIZE 64
|
| 1082 |
+
PREF_PHASE_MAXDIFF_THRESH 64
|
| 1083 |
+
PREF_PHASE_MIN_MISSES 64
|
| 1084 |
+
PREF_PHASE_MISSPER 0.4
|
| 1085 |
+
PREF_2DC_ON FALSE
|
| 1086 |
+
DEBUG_PREF_2DC FALSE
|
| 1087 |
+
PREF_2DC_CACHE_SIZE (1 * 1024)
|
| 1088 |
+
PREF_2DC_CACHE_ASSOC 4
|
| 1089 |
+
PREF_2DC_CACHE_LINE_SIZE 1
|
| 1090 |
+
PREF_2DC_DEGREE 16
|
| 1091 |
+
PREF_2DC_ZONE_SHIFT 10
|
| 1092 |
+
PREF_2DC_TAG_SIZE 16
|
| 1093 |
+
PREF_2DC_NUM_REGIONS 64
|
| 1094 |
+
PREF_2DC_REGION_HASH 61
|
| 1095 |
+
PREF_MARKOV_ON FALSE
|
| 1096 |
+
DEBUG_PREF_MARKOV FALSE
|
| 1097 |
+
PREF_MARKOV_NUM_ENTRIES 65536
|
| 1098 |
+
PREF_MARKOV_NUM_NEXT_STATES 8
|
| 1099 |
+
PREF_MARKOV_SEND_ON_PREF_HIT TRUE
|
| 1100 |
+
PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE
|
| 1101 |
+
PREF_MARKOV_TABLE_UPDATE_POLICY 0
|
| 1102 |
+
PREF_MARKOV_SEND_THRESHOLD 0
|
tsp/fingerprint/run_10/sim.log
ADDED
|
@@ -0,0 +1,857 @@
|
|
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|
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|
|
|
|
|
|
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|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
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|
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| 1 |
+
[0]: ad: 0x7ffff7108409, op: 427
|
| 2 |
+
[0]: ad: 0x7ffff7108410, op: 109
|
| 3 |
+
[0]: ad: 0x7ffff7108415, op: 330
|
| 4 |
+
new bb detected: 1
|
| 5 |
+
[1]: ad: 0x7ffff710841b, op: 388
|
| 6 |
+
[1]: ad: 0x7ffff7108422, op: 847
|
| 7 |
+
[1]: ad: 0x7ffff7108424, op: 330
|
| 8 |
+
new bb detected: 2
|
| 9 |
+
[2]: ad: 0x7ffff710844c, op: 1723
|
| 10 |
+
[2]: ad: 0x7ffff710844e, op: 75
|
| 11 |
+
new bb detected: 3
|
| 12 |
+
[3]: ad: 0x7ffff71056a0, op: 671
|
| 13 |
+
[3]: ad: 0x7ffff71056a2, op: 671
|
| 14 |
+
[3]: ad: 0x7ffff71056a4, op: 671
|
| 15 |
+
[3]: ad: 0x7ffff71056a6, op: 427
|
| 16 |
+
[3]: ad: 0x7ffff71056a9, op: 671
|
| 17 |
+
[3]: ad: 0x7ffff71056ab, op: 671
|
| 18 |
+
[3]: ad: 0x7ffff71056ac, op: 671
|
| 19 |
+
[3]: ad: 0x7ffff71056ad, op: 826
|
| 20 |
+
[3]: ad: 0x7ffff71056b1, op: 427
|
| 21 |
+
[3]: ad: 0x7ffff71056b5, op: 427
|
| 22 |
+
[3]: ad: 0x7ffff71056be, op: 427
|
| 23 |
+
[3]: ad: 0x7ffff71056c3, op: 1723
|
| 24 |
+
[3]: ad: 0x7ffff71056c5, op: 427
|
| 25 |
+
[3]: ad: 0x7ffff71056c8, op: 31
|
| 26 |
+
[3]: ad: 0x7ffff71056cc, op: 427
|
| 27 |
+
[3]: ad: 0x7ffff71056cf, op: 480
|
| 28 |
+
[3]: ad: 0x7ffff71056d2, op: 109
|
| 29 |
+
[3]: ad: 0x7ffff71056d5, op: 319
|
| 30 |
+
new bb detected: 4
|
| 31 |
+
[4]: ad: 0x7ffff71056db, op: 427
|
| 32 |
+
[4]: ad: 0x7ffff71056de, op: 847
|
| 33 |
+
[4]: ad: 0x7ffff71056e2, op: 325
|
| 34 |
+
new bb detected: 5
|
| 35 |
+
[5]: ad: 0x7ffff71056e8, op: 109
|
| 36 |
+
[5]: ad: 0x7ffff71056ec, op: 311
|
| 37 |
+
new bb detected: 6
|
| 38 |
+
[6]: ad: 0x7ffff71056f2, op: 31
|
| 39 |
+
[6]: ad: 0x7ffff71056f5, op: 325
|
| 40 |
+
new bb detected: 7
|
| 41 |
+
[7]: ad: 0x7ffff71056fb, op: 427
|
| 42 |
+
[7]: ad: 0x7ffff7105702, op: 427
|
| 43 |
+
[7]: ad: 0x7ffff7105705, op: 427
|
| 44 |
+
[7]: ad: 0x7ffff7105709, op: 847
|
| 45 |
+
[7]: ad: 0x7ffff710570c, op: 330
|
| 46 |
+
new bb detected: 8
|
| 47 |
+
[8]: ad: 0x7ffff710570e, op: 388
|
| 48 |
+
[8]: ad: 0x7ffff7105712, op: 799
|
| 49 |
+
[8]: ad: 0x7ffff7105716, op: 109
|
| 50 |
+
[8]: ad: 0x7ffff710571d, op: 311
|
| 51 |
+
new bb detected: 9
|
| 52 |
+
[9]: ad: 0x7ffff710571f, op: 427
|
| 53 |
+
[9]: ad: 0x7ffff7105726, op: 427
|
| 54 |
+
[9]: ad: 0x7ffff710572d, op: 388
|
| 55 |
+
[9]: ad: 0x7ffff7105731, op: 109
|
| 56 |
+
[9]: ad: 0x7ffff7105735, op: 330
|
| 57 |
+
new bb detected: 10
|
| 58 |
+
[10]: ad: 0x7ffff710573b, op: 468
|
| 59 |
+
[10]: ad: 0x7ffff710573f, op: 427
|
| 60 |
+
[10]: ad: 0x7ffff7105742, op: 109
|
| 61 |
+
[10]: ad: 0x7ffff7105745, op: 310
|
| 62 |
+
new bb detected: 11
|
| 63 |
+
[11]: ad: 0x7ffff7105a00, op: 427
|
| 64 |
+
[11]: ad: 0x7ffff7105a07, op: 8
|
| 65 |
+
[11]: ad: 0x7ffff7105a0a, op: 427
|
| 66 |
+
[11]: ad: 0x7ffff7105a0e, op: 427
|
| 67 |
+
[11]: ad: 0x7ffff7105a11, op: 799
|
| 68 |
+
[11]: ad: 0x7ffff7105a15, op: 1723
|
| 69 |
+
[11]: ad: 0x7ffff7105a1d, op: 427
|
| 70 |
+
[11]: ad: 0x7ffff7105a21, op: 427
|
| 71 |
+
[11]: ad: 0x7ffff7105a29, op: 427
|
| 72 |
+
[11]: ad: 0x7ffff7105a2d, op: 316
|
| 73 |
+
new bb detected: 12
|
| 74 |
+
[12]: ad: 0x7ffff71057e8, op: 427
|
| 75 |
+
[12]: ad: 0x7ffff71057ed, op: 826
|
| 76 |
+
[12]: ad: 0x7ffff71057f6, op: 325
|
| 77 |
+
new bb detected: 13
|
| 78 |
+
[13]: ad: 0x7ffff71057fc, op: 8
|
| 79 |
+
[13]: ad: 0x7ffff7105800, op: 616
|
| 80 |
+
[13]: ad: 0x7ffff7105801, op: 616
|
| 81 |
+
[13]: ad: 0x7ffff7105802, op: 616
|
| 82 |
+
[13]: ad: 0x7ffff7105804, op: 616
|
| 83 |
+
[13]: ad: 0x7ffff7105806, op: 616
|
| 84 |
+
[13]: ad: 0x7ffff7105808, op: 616
|
| 85 |
+
[13]: ad: 0x7ffff710580a, op: 740
|
| 86 |
+
new bb detected: 14
|
| 87 |
+
[14]: ad: 0x7ffff7108453, op: 427
|
| 88 |
+
[14]: ad: 0x7ffff7108456, op: 8
|
| 89 |
+
[14]: ad: 0x7ffff710845a, op: 616
|
| 90 |
+
[14]: ad: 0x7ffff710845b, op: 616
|
| 91 |
+
[14]: ad: 0x7ffff710845c, op: 740
|
| 92 |
+
new bb detected: 15
|
| 93 |
+
[15]: ad: 0x7ffff3d8e582, op: 427
|
| 94 |
+
[15]: ad: 0x7ffff3d8e585, op: 427
|
| 95 |
+
[15]: ad: 0x7ffff3d8e588, op: 427
|
| 96 |
+
[15]: ad: 0x7ffff3d8e58b, op: 427
|
| 97 |
+
[15]: ad: 0x7ffff3d8e58e, op: 427
|
| 98 |
+
[15]: ad: 0x7ffff3d8e591, op: 75
|
| 99 |
+
new bb detected: 16
|
| 100 |
+
[16]: ad: 0x7ffff3d8e3c0, op: 482
|
| 101 |
+
[16]: ad: 0x7ffff3d8e3c4, op: 671
|
| 102 |
+
[16]: ad: 0x7ffff3d8e3c6, op: 671
|
| 103 |
+
[16]: ad: 0x7ffff3d8e3c8, op: 671
|
| 104 |
+
[16]: ad: 0x7ffff3d8e3ca, op: 671
|
| 105 |
+
[16]: ad: 0x7ffff3d8e3cc, op: 671
|
| 106 |
+
[16]: ad: 0x7ffff3d8e3cd, op: 427
|
| 107 |
+
[16]: ad: 0x7ffff3d8e3d0, op: 671
|
| 108 |
+
[16]: ad: 0x7ffff3d8e3d1, op: 826
|
| 109 |
+
[16]: ad: 0x7ffff3d8e3d5, op: 427
|
| 110 |
+
[16]: ad: 0x7ffff3d8e3d9, op: 427
|
| 111 |
+
[16]: ad: 0x7ffff3d8e3dd, op: 465
|
| 112 |
+
[16]: ad: 0x7ffff3d8e3e1, op: 109
|
| 113 |
+
[16]: ad: 0x7ffff3d8e3e5, op: 330
|
| 114 |
+
new bb detected: 17
|
| 115 |
+
[17]: ad: 0x7ffff3d8e3eb, op: 427
|
| 116 |
+
[17]: ad: 0x7ffff3d8e3f1, op: 109
|
| 117 |
+
[17]: ad: 0x7ffff3d8e3f4, op: 315
|
| 118 |
+
new bb detected: 18
|
| 119 |
+
[18]: ad: 0x7ffff3d8e3fa, op: 427
|
| 120 |
+
[18]: ad: 0x7ffff3d8e3fd, op: 427
|
| 121 |
+
[18]: ad: 0x7ffff3d8e401, op: 427
|
| 122 |
+
[18]: ad: 0x7ffff3d8e405, op: 109
|
| 123 |
+
[18]: ad: 0x7ffff3d8e408, op: 330
|
| 124 |
+
new bb detected: 19
|
| 125 |
+
[19]: ad: 0x7ffff3d8e40e, op: 796
|
| 126 |
+
[19]: ad: 0x7ffff3d8e412, op: 316
|
| 127 |
+
new bb detected: 20
|
| 128 |
+
[20]: ad: 0x7ffff3d8e427, op: 427
|
| 129 |
+
[20]: ad: 0x7ffff3d8e42e, op: 465
|
| 130 |
+
[20]: ad: 0x7ffff3d8e431, op: 427
|
| 131 |
+
[20]: ad: 0x7ffff3d8e435, op: 427
|
| 132 |
+
[20]: ad: 0x7ffff3d8e438, op: 8
|
| 133 |
+
[20]: ad: 0x7ffff3d8e43b, op: 109
|
| 134 |
+
[20]: ad: 0x7ffff3d8e43d, op: 320
|
| 135 |
+
new bb detected: 21
|
| 136 |
+
[21]: ad: 0x7ffff3d8e418, op: 8
|
| 137 |
+
[21]: ad: 0x7ffff3d8e41c, op: 109
|
| 138 |
+
[21]: ad: 0x7ffff3d8e41f, op: 330
|
| 139 |
+
new bb detected: 22
|
| 140 |
+
[22]: ad: 0x7ffff3d8e421, op: 427
|
| 141 |
+
[22]: ad: 0x7ffff3d8e427, op: 427
|
| 142 |
+
[22]: ad: 0x7ffff3d8e42e, op: 465
|
| 143 |
+
[22]: ad: 0x7ffff3d8e431, op: 427
|
| 144 |
+
[22]: ad: 0x7ffff3d8e435, op: 427
|
| 145 |
+
[22]: ad: 0x7ffff3d8e438, op: 8
|
| 146 |
+
[22]: ad: 0x7ffff3d8e43b, op: 109
|
| 147 |
+
[22]: ad: 0x7ffff3d8e43d, op: 320
|
| 148 |
+
new bb detected: 23
|
| 149 |
+
[23]: ad: 0x7ffff3d8e49f, op: 8
|
| 150 |
+
[23]: ad: 0x7ffff3d8e4a3, op: 616
|
| 151 |
+
[23]: ad: 0x7ffff3d8e4a4, op: 616
|
| 152 |
+
[23]: ad: 0x7ffff3d8e4a5, op: 616
|
| 153 |
+
[23]: ad: 0x7ffff3d8e4a7, op: 616
|
| 154 |
+
[23]: ad: 0x7ffff3d8e4a9, op: 616
|
| 155 |
+
[23]: ad: 0x7ffff3d8e4ab, op: 616
|
| 156 |
+
[23]: ad: 0x7ffff3d8e4ad, op: 740
|
| 157 |
+
new bb detected: 24
|
| 158 |
+
[24]: ad: 0x7ffff3d8e596, op: 847
|
| 159 |
+
[24]: ad: 0x7ffff3d8e599, op: 330
|
| 160 |
+
new bb detected: 25
|
| 161 |
+
[25]: ad: 0x7ffff3d8e59b, op: 427
|
| 162 |
+
[25]: ad: 0x7ffff3d8e5a0, op: 847
|
| 163 |
+
[25]: ad: 0x7ffff3d8e5a3, op: 330
|
| 164 |
+
new bb detected: 26
|
| 165 |
+
[26]: ad: 0x7ffff3d8e5a5, op: 75
|
| 166 |
+
new bb detected: 27
|
| 167 |
+
[27]: ad: 0x7ffff3d8d270, op: 482
|
| 168 |
+
[27]: ad: 0x7ffff3d8d274, op: 316
|
| 169 |
+
new bb detected: 28
|
| 170 |
+
[28]: ad: 0x7ffff7338c10, op: 482
|
| 171 |
+
[28]: ad: 0x7ffff7338c14, op: 316
|
| 172 |
+
new bb detected: 29
|
| 173 |
+
[29]: ad: 0x7ffff732bb30, op: 482
|
| 174 |
+
[29]: ad: 0x7ffff732bb34, op: 316
|
| 175 |
+
new bb detected: 30
|
| 176 |
+
[30]: ad: 0x7ffff71083e0, op: 482
|
| 177 |
+
[30]: ad: 0x7ffff71083e4, op: 847
|
| 178 |
+
[30]: ad: 0x7ffff71083e7, op: 330
|
| 179 |
+
new bb detected: 31
|
| 180 |
+
[31]: ad: 0x7ffff71083ed, op: 671
|
| 181 |
+
[31]: ad: 0x7ffff71083ee, op: 388
|
| 182 |
+
[31]: ad: 0x7ffff71083f2, op: 671
|
| 183 |
+
[31]: ad: 0x7ffff71083f3, op: 826
|
| 184 |
+
[31]: ad: 0x7ffff71083f7, op: 427
|
| 185 |
+
[31]: ad: 0x7ffff71083fe, op: 427
|
| 186 |
+
[31]: ad: 0x7ffff7108402, op: 427
|
| 187 |
+
[31]: ad: 0x7ffff7108405, op: 847
|
| 188 |
+
[31]: ad: 0x7ffff7108407, op: 325
|
| 189 |
+
new bb detected: 32
|
| 190 |
+
[32]: ad: 0x7ffff3d8e5aa, op: 427
|
| 191 |
+
[32]: ad: 0x7ffff3d8e5ae, op: 847
|
| 192 |
+
[32]: ad: 0x7ffff3d8e5b1, op: 330
|
| 193 |
+
new bb detected: 33
|
| 194 |
+
[33]: ad: 0x7ffff3d8e5b3, op: 75
|
| 195 |
+
new bb detected: 34
|
| 196 |
+
[34]: ad: 0x7ffff3d8e5b8, op: 427
|
| 197 |
+
[34]: ad: 0x7ffff3d8e5bb, op: 75
|
| 198 |
+
new bb detected: 35
|
| 199 |
+
[35]: ad: 0x7ffff3d8e5c0, op: 427
|
| 200 |
+
[35]: ad: 0x7ffff3d8e5c3, op: 109
|
| 201 |
+
[35]: ad: 0x7ffff3d8e5c6, op: 325
|
| 202 |
+
new bb detected: 36
|
| 203 |
+
[36]: ad: 0x7ffff3d8e569, op: 427
|
| 204 |
+
[36]: ad: 0x7ffff3d8e56d, op: 826
|
| 205 |
+
[36]: ad: 0x7ffff3d8e572, op: 427
|
| 206 |
+
[36]: ad: 0x7ffff3d8e575, op: 75
|
| 207 |
+
new bb detected: 37
|
| 208 |
+
[37]: ad: 0x7ffff3d8d300, op: 482
|
| 209 |
+
[37]: ad: 0x7ffff3d8d304, op: 316
|
| 210 |
+
new bb detected: 38
|
| 211 |
+
[38]: ad: 0x7ffff734bdb0, op: 482
|
| 212 |
+
[38]: ad: 0x7ffff734bdb4, op: 427
|
| 213 |
+
[38]: ad: 0x7ffff734bdb7, op: 427
|
| 214 |
+
[38]: ad: 0x7ffff734bdbb, op: 427
|
| 215 |
+
[38]: ad: 0x7ffff734bdbe, op: 427
|
| 216 |
+
[38]: ad: 0x7ffff734bdc2, op: 740
|
| 217 |
+
new bb detected: 39
|
| 218 |
+
[39]: ad: 0x7ffff3d8e57a, op: 427
|
| 219 |
+
[39]: ad: 0x7ffff3d8e57d, op: 75
|
| 220 |
+
new bb detected: 40
|
| 221 |
+
[40]: ad: 0x7ffff3d8e43f, op: 427
|
| 222 |
+
[40]: ad: 0x7ffff3d8e444, op: 75
|
| 223 |
+
new bb detected: 41
|
| 224 |
+
[41]: ad: 0x7ffff3d8d280, op: 482
|
| 225 |
+
[41]: ad: 0x7ffff3d8d284, op: 316
|
| 226 |
+
new bb detected: 42
|
| 227 |
+
[42]: ad: 0x7ffff733a970, op: 482
|
| 228 |
+
[42]: ad: 0x7ffff733a974, op: 847
|
| 229 |
+
[42]: ad: 0x7ffff733a977, op: 427
|
| 230 |
+
[42]: ad: 0x7ffff733a97c, op: 671
|
| 231 |
+
[42]: ad: 0x7ffff733a97d, op: 104
|
| 232 |
+
[42]: ad: 0x7ffff733a981, op: 427
|
| 233 |
+
[42]: ad: 0x7ffff733a984, op: 427
|
| 234 |
+
[42]: ad: 0x7ffff733a987, op: 75
|
| 235 |
+
new bb detected: 43
|
| 236 |
+
[43]: ad: 0x7ffff732b0d0, op: 482
|
| 237 |
+
[43]: ad: 0x7ffff732b0d4, op: 316
|
| 238 |
+
new bb detected: 44
|
| 239 |
+
[44]: ad: 0x7ffff71080a0, op: 482
|
| 240 |
+
[44]: ad: 0x7ffff71080a4, op: 671
|
| 241 |
+
[44]: ad: 0x7ffff71080a6, op: 671
|
| 242 |
+
[44]: ad: 0x7ffff71080a7, op: 427
|
| 243 |
+
[44]: ad: 0x7ffff71080aa, op: 671
|
| 244 |
+
[44]: ad: 0x7ffff71080ab, op: 826
|
| 245 |
+
[44]: ad: 0x7ffff71080af, op: 109
|
| 246 |
+
[44]: ad: 0x7ffff71080b6, op: 330
|
| 247 |
+
new bb detected: 45
|
| 248 |
+
[45]: ad: 0x7ffff71080bc, op: 847
|
| 249 |
+
[45]: ad: 0x7ffff71080bf, op: 329
|
| 250 |
+
new bb detected: 46
|
| 251 |
+
[46]: ad: 0x7ffff71080c5, op: 388
|
| 252 |
+
[46]: ad: 0x7ffff71080c9, op: 1723
|
| 253 |
+
[46]: ad: 0x7ffff71080cc, op: 109
|
| 254 |
+
[46]: ad: 0x7ffff71080d0, op: 319
|
| 255 |
+
new bb detected: 47
|
| 256 |
+
[47]: ad: 0x7ffff71081b0, op: 31
|
| 257 |
+
[47]: ad: 0x7ffff71081b4, op: 388
|
| 258 |
+
[47]: ad: 0x7ffff71081b8, op: 799
|
| 259 |
+
[47]: ad: 0x7ffff71081bc, op: 316
|
| 260 |
+
new bb detected: 48
|
| 261 |
+
[48]: ad: 0x7ffff71080d6, op: 427
|
| 262 |
+
[48]: ad: 0x7ffff71080dd, op: 427
|
| 263 |
+
[48]: ad: 0x7ffff71080e1, op: 847
|
| 264 |
+
[48]: ad: 0x7ffff71080e4, op: 330
|
| 265 |
+
new bb detected: 49
|
| 266 |
+
[49]: ad: 0x7ffff71080ea, op: 109
|
| 267 |
+
[49]: ad: 0x7ffff71080f1, op: 319
|
| 268 |
+
new bb detected: 50
|
| 269 |
+
[50]: ad: 0x7ffff7108200, op: 468
|
| 270 |
+
[50]: ad: 0x7ffff7108205, op: 847
|
| 271 |
+
[50]: ad: 0x7ffff7108208, op: 330
|
| 272 |
+
new bb detected: 51
|
| 273 |
+
[51]: ad: 0x7ffff710820e, op: 388
|
| 274 |
+
[51]: ad: 0x7ffff7108213, op: 427
|
| 275 |
+
[51]: ad: 0x7ffff7108217, op: 847
|
| 276 |
+
[51]: ad: 0x7ffff7108219, op: 325
|
| 277 |
+
new bb detected: 52
|
| 278 |
+
[52]: ad: 0x7ffff710821f, op: 427
|
| 279 |
+
[52]: ad: 0x7ffff7108222, op: 826
|
| 280 |
+
[52]: ad: 0x7ffff7108225, op: 799
|
| 281 |
+
[52]: ad: 0x7ffff7108229, op: 1723
|
| 282 |
+
[52]: ad: 0x7ffff710822c, op: 427
|
| 283 |
+
[52]: ad: 0x7ffff7108230, op: 427
|
| 284 |
+
[52]: ad: 0x7ffff7108235, op: 427
|
| 285 |
+
[52]: ad: 0x7ffff710823d, op: 8
|
| 286 |
+
[52]: ad: 0x7ffff7108241, op: 616
|
| 287 |
+
[52]: ad: 0x7ffff7108242, op: 616
|
| 288 |
+
[52]: ad: 0x7ffff7108243, op: 616
|
| 289 |
+
[52]: ad: 0x7ffff7108245, op: 740
|
| 290 |
+
new bb detected: 53
|
| 291 |
+
[53]: ad: 0x7ffff733a98c, op: 847
|
| 292 |
+
[53]: ad: 0x7ffff733a98f, op: 330
|
| 293 |
+
new bb detected: 54
|
| 294 |
+
[54]: ad: 0x7ffff733a991, op: 616
|
| 295 |
+
[54]: ad: 0x7ffff733a992, op: 740
|
| 296 |
+
new bb detected: 55
|
| 297 |
+
[55]: ad: 0x7ffff3d8e449, op: 427
|
| 298 |
+
[55]: ad: 0x7ffff3d8e44c, op: 427
|
| 299 |
+
[55]: ad: 0x7ffff3d8e44f, op: 427
|
| 300 |
+
[55]: ad: 0x7ffff3d8e452, op: 75
|
| 301 |
+
new bb detected: 56
|
| 302 |
+
[56]: ad: 0x7ffff3d8de30, op: 482
|
| 303 |
+
[56]: ad: 0x7ffff3d8de34, op: 671
|
| 304 |
+
[56]: ad: 0x7ffff3d8de36, op: 678
|
| 305 |
+
[56]: ad: 0x7ffff3d8de3a, op: 671
|
| 306 |
+
[56]: ad: 0x7ffff3d8de3b, op: 427
|
| 307 |
+
[56]: ad: 0x7ffff3d8de3e, op: 671
|
| 308 |
+
[56]: ad: 0x7ffff3d8de3f, op: 427
|
| 309 |
+
[56]: ad: 0x7ffff3d8de43, op: 427
|
| 310 |
+
[56]: ad: 0x7ffff3d8de46, op: 826
|
| 311 |
+
[56]: ad: 0x7ffff3d8de49, op: 427
|
| 312 |
+
[56]: ad: 0x7ffff3d8de51, op: 467
|
| 313 |
+
[56]: ad: 0x7ffff3d8de54, op: 330
|
| 314 |
+
new bb detected: 57
|
| 315 |
+
[57]: ad: 0x7ffff3d8de5a, op: 427
|
| 316 |
+
[57]: ad: 0x7ffff3d8de64, op: 427
|
| 317 |
+
[57]: ad: 0x7ffff3d8de67, op: 109
|
| 318 |
+
[57]: ad: 0x7ffff3d8de6a, op: 319
|
| 319 |
+
new bb detected: 58
|
| 320 |
+
[58]: ad: 0x7ffff3d8de70, op: 427
|
| 321 |
+
[58]: ad: 0x7ffff3d8de73, op: 75
|
| 322 |
+
new bb detected: 59
|
| 323 |
+
[59]: ad: 0x7ffff3d8de78, op: 427
|
| 324 |
+
[59]: ad: 0x7ffff3d8de7b, op: 454
|
| 325 |
+
[59]: ad: 0x7ffff3d8de80, op: 8
|
| 326 |
+
[59]: ad: 0x7ffff3d8de83, op: 669
|
| 327 |
+
[59]: ad: 0x7ffff3d8de87, op: 427
|
| 328 |
+
[59]: ad: 0x7ffff3d8de8b, op: 467
|
| 329 |
+
[59]: ad: 0x7ffff3d8de8e, op: 427
|
| 330 |
+
[59]: ad: 0x7ffff3d8de92, op: 427
|
| 331 |
+
[59]: ad: 0x7ffff3d8de96, op: 427
|
| 332 |
+
[59]: ad: 0x7ffff3d8de99, op: 826
|
| 333 |
+
[59]: ad: 0x7ffff3d8de9c, op: 109
|
| 334 |
+
[59]: ad: 0x7ffff3d8de9f, op: 330
|
| 335 |
+
new bb detected: 60
|
| 336 |
+
[60]: ad: 0x7ffff3d8dea1, op: 427
|
| 337 |
+
[60]: ad: 0x7ffff3d8dea4, op: 427
|
| 338 |
+
[60]: ad: 0x7ffff3d8dea7, op: 75
|
| 339 |
+
new bb detected: 61
|
| 340 |
+
[61]: ad: 0x7ffff3d8d2f0, op: 482
|
| 341 |
+
[61]: ad: 0x7ffff3d8d2f4, op: 316
|
| 342 |
+
new bb detected: 62
|
| 343 |
+
[62]: ad: 0x7ffff72037f0, op: 482
|
| 344 |
+
[62]: ad: 0x7ffff72037f4, op: 427
|
| 345 |
+
[62]: ad: 0x7ffff72037f7, op: 109
|
| 346 |
+
[62]: ad: 0x7ffff72037fb, op: 310
|
| 347 |
+
new bb detected: 63
|
| 348 |
+
[63]: ad: 0x7ffff7203801, op: 1232
|
| 349 |
+
[63]: ad: 0x7ffff7203805, op: 109
|
| 350 |
+
[63]: ad: 0x7ffff7203809, op: 319
|
| 351 |
+
new bb detected: 64
|
| 352 |
+
[64]: ad: 0x7ffff720380f, op: 1232
|
| 353 |
+
[64]: ad: 0x7ffff7203815, op: 1232
|
| 354 |
+
[64]: ad: 0x7ffff7203819, op: 1232
|
| 355 |
+
[64]: ad: 0x7ffff720381f, op: 1704
|
| 356 |
+
[64]: ad: 0x7ffff7203822, op: 740
|
| 357 |
+
new bb detected: 65
|
| 358 |
+
[65]: ad: 0x7ffff3d8deac, op: 427
|
| 359 |
+
[65]: ad: 0x7ffff3d8deaf, op: 8
|
| 360 |
+
[65]: ad: 0x7ffff3d8deb2, op: 678
|
| 361 |
+
[65]: ad: 0x7ffff3d8deb6, op: 427
|
| 362 |
+
[65]: ad: 0x7ffff3d8deba, op: 427
|
| 363 |
+
[65]: ad: 0x7ffff3d8debe, op: 826
|
| 364 |
+
[65]: ad: 0x7ffff3d8dec2, op: 427
|
| 365 |
+
[65]: ad: 0x7ffff3d8deca, op: 467
|
| 366 |
+
[65]: ad: 0x7ffff3d8dece, op: 330
|
| 367 |
+
new bb detected: 66
|
| 368 |
+
[66]: ad: 0x7ffff3d8ded4, op: 427
|
| 369 |
+
[66]: ad: 0x7ffff3d8dede, op: 427
|
| 370 |
+
[66]: ad: 0x7ffff3d8dee1, op: 109
|
| 371 |
+
[66]: ad: 0x7ffff3d8dee4, op: 319
|
| 372 |
+
new bb detected: 67
|
| 373 |
+
[67]: ad: 0x7ffff3d8deea, op: 427
|
| 374 |
+
[67]: ad: 0x7ffff3d8deed, op: 75
|
| 375 |
+
new bb detected: 68
|
| 376 |
+
[68]: ad: 0x7ffff3d8def2, op: 427
|
| 377 |
+
[68]: ad: 0x7ffff3d8def5, op: 454
|
| 378 |
+
[68]: ad: 0x7ffff3d8defa, op: 8
|
| 379 |
+
[68]: ad: 0x7ffff3d8defd, op: 669
|
| 380 |
+
[68]: ad: 0x7ffff3d8df01, op: 427
|
| 381 |
+
[68]: ad: 0x7ffff3d8df05, op: 467
|
| 382 |
+
[68]: ad: 0x7ffff3d8df09, op: 427
|
| 383 |
+
[68]: ad: 0x7ffff3d8df0d, op: 427
|
| 384 |
+
[68]: ad: 0x7ffff3d8df11, op: 427
|
| 385 |
+
[68]: ad: 0x7ffff3d8df14, op: 826
|
| 386 |
+
[68]: ad: 0x7ffff3d8df17, op: 109
|
| 387 |
+
[68]: ad: 0x7ffff3d8df1a, op: 330
|
| 388 |
+
new bb detected: 69
|
| 389 |
+
[69]: ad: 0x7ffff3d8df1c, op: 427
|
| 390 |
+
[69]: ad: 0x7ffff3d8df1f, op: 427
|
| 391 |
+
[69]: ad: 0x7ffff3d8df22, op: 75
|
| 392 |
+
new bb detected: 70
|
| 393 |
+
[70]: ad: 0x7ffff72038b0, op: 109
|
| 394 |
+
[70]: ad: 0x7ffff72038b3, op: 318
|
| 395 |
+
new bb detected: 71
|
| 396 |
+
[71]: ad: 0x7ffff72038e2, op: 1232
|
| 397 |
+
[71]: ad: 0x7ffff72038e6, op: 1232
|
| 398 |
+
[71]: ad: 0x7ffff72038ec, op: 1232
|
| 399 |
+
[71]: ad: 0x7ffff72038f0, op: 1232
|
| 400 |
+
[71]: ad: 0x7ffff72038f6, op: 740
|
| 401 |
+
new bb detected: 72
|
| 402 |
+
[72]: ad: 0x7ffff3d8df27, op: 427
|
| 403 |
+
[72]: ad: 0x7ffff3d8df2a, op: 427
|
| 404 |
+
[72]: ad: 0x7ffff3d8df2e, op: 8
|
| 405 |
+
[72]: ad: 0x7ffff3d8df31, op: 427
|
| 406 |
+
[72]: ad: 0x7ffff3d8df35, op: 427
|
| 407 |
+
[72]: ad: 0x7ffff3d8df39, op: 616
|
| 408 |
+
[72]: ad: 0x7ffff3d8df3a, op: 616
|
| 409 |
+
[72]: ad: 0x7ffff3d8df3b, op: 616
|
| 410 |
+
[72]: ad: 0x7ffff3d8df3d, op: 740
|
| 411 |
+
new bb detected: 73
|
| 412 |
+
[73]: ad: 0x7ffff3d8e457, op: 427
|
| 413 |
+
[73]: ad: 0x7ffff3d8e45a, op: 826
|
| 414 |
+
[73]: ad: 0x7ffff3d8e45e, op: 427
|
| 415 |
+
[73]: ad: 0x7ffff3d8e461, op: 8
|
| 416 |
+
[73]: ad: 0x7ffff3d8e465, op: 756
|
| 417 |
+
[73]: ad: 0x7ffff3d8e469, op: 75
|
| 418 |
+
new bb detected: 74
|
| 419 |
+
[74]: ad: 0x7ffff3d8e2d0, op: 482
|
| 420 |
+
[74]: ad: 0x7ffff3d8e2d4, op: 671
|
| 421 |
+
[74]: ad: 0x7ffff3d8e2d5, op: 671
|
| 422 |
+
[74]: ad: 0x7ffff3d8e2d6, op: 826
|
| 423 |
+
[74]: ad: 0x7ffff3d8e2da, op: 427
|
| 424 |
+
[74]: ad: 0x7ffff3d8e2dd, op: 427
|
| 425 |
+
[74]: ad: 0x7ffff3d8e2e6, op: 427
|
| 426 |
+
[74]: ad: 0x7ffff3d8e2eb, op: 1723
|
| 427 |
+
[74]: ad: 0x7ffff3d8e2ed, op: 847
|
| 428 |
+
[74]: ad: 0x7ffff3d8e2ef, op: 315
|
| 429 |
+
new bb detected: 75
|
| 430 |
+
[75]: ad: 0x7ffff3d8e2f5, op: 427
|
| 431 |
+
[75]: ad: 0x7ffff3d8e2f9, op: 465
|
| 432 |
+
[75]: ad: 0x7ffff3d8e2fc, op: 427
|
| 433 |
+
[75]: ad: 0x7ffff3d8e2ff, op: 8
|
| 434 |
+
[75]: ad: 0x7ffff3d8e302, op: 388
|
| 435 |
+
[75]: ad: 0x7ffff3d8e30a, op: 427
|
| 436 |
+
[75]: ad: 0x7ffff3d8e30e, op: 427
|
| 437 |
+
[75]: ad: 0x7ffff3d8e315, op: 431
|
| 438 |
+
[75]: ad: 0x7ffff3d8e319, op: 465
|
| 439 |
+
[75]: ad: 0x7ffff3d8e31d, op: 8
|
| 440 |
+
[75]: ad: 0x7ffff3d8e320, op: 465
|
| 441 |
+
[75]: ad: 0x7ffff3d8e323, op: 427
|
| 442 |
+
[75]: ad: 0x7ffff3d8e327, op: 427
|
| 443 |
+
[75]: ad: 0x7ffff3d8e32a, op: 8
|
| 444 |
+
[75]: ad: 0x7ffff3d8e32e, op: 427
|
| 445 |
+
[75]: ad: 0x7ffff3d8e333, op: 431
|
| 446 |
+
[75]: ad: 0x7ffff3d8e337, op: 668
|
| 447 |
+
[75]: ad: 0x7ffff3d8e33b, op: 454
|
| 448 |
+
[75]: ad: 0x7ffff3d8e340, op: 109
|
| 449 |
+
[75]: ad: 0x7ffff3d8e344, op: 330
|
| 450 |
+
new bb detected: 76
|
| 451 |
+
[76]: ad: 0x7ffff3d8e380, op: 427
|
| 452 |
+
[76]: ad: 0x7ffff3d8e383, op: 388
|
| 453 |
+
[76]: ad: 0x7ffff3d8e388, op: 427
|
| 454 |
+
[76]: ad: 0x7ffff3d8e38b, op: 75
|
| 455 |
+
new bb detected: 77
|
| 456 |
+
[77]: ad: 0x7ffff3d8e750, op: 482
|
| 457 |
+
[77]: ad: 0x7ffff3d8e754, op: 671
|
| 458 |
+
[77]: ad: 0x7ffff3d8e756, op: 427
|
| 459 |
+
[77]: ad: 0x7ffff3d8e759, op: 427
|
| 460 |
+
[77]: ad: 0x7ffff3d8e763, op: 671
|
| 461 |
+
[77]: ad: 0x7ffff3d8e765, op: 671
|
| 462 |
+
[77]: ad: 0x7ffff3d8e767, op: 671
|
| 463 |
+
[77]: ad: 0x7ffff3d8e769, op: 671
|
| 464 |
+
[77]: ad: 0x7ffff3d8e76a, op: 671
|
| 465 |
+
[77]: ad: 0x7ffff3d8e76b, op: 826
|
| 466 |
+
[77]: ad: 0x7ffff3d8e76f, op: 427
|
| 467 |
+
[77]: ad: 0x7ffff3d8e773, op: 427
|
| 468 |
+
[77]: ad: 0x7ffff3d8e776, op: 427
|
| 469 |
+
[77]: ad: 0x7ffff3d8e779, op: 826
|
| 470 |
+
[77]: ad: 0x7ffff3d8e77c, op: 756
|
| 471 |
+
[77]: ad: 0x7ffff3d8e780, op: 109
|
| 472 |
+
[77]: ad: 0x7ffff3d8e783, op: 330
|
| 473 |
+
new bb detected: 78
|
| 474 |
+
[78]: ad: 0x7ffff3d8e789, op: 847
|
| 475 |
+
[78]: ad: 0x7ffff3d8e78c, op: 427
|
| 476 |
+
[78]: ad: 0x7ffff3d8e791, op: 427
|
| 477 |
+
[78]: ad: 0x7ffff3d8e794, op: 427
|
| 478 |
+
[78]: ad: 0x7ffff3d8e797, op: 104
|
| 479 |
+
[78]: ad: 0x7ffff3d8e79b, op: 1723
|
| 480 |
+
[78]: ad: 0x7ffff3d8e79d, op: 8
|
| 481 |
+
[78]: ad: 0x7ffff3d8e7a0, op: 427
|
| 482 |
+
[78]: ad: 0x7ffff3d8e7a3, op: 770
|
| 483 |
+
[78]: ad: 0x7ffff3d8e7a6, op: 826
|
| 484 |
+
[78]: ad: 0x7ffff3d8e7a9, op: 847
|
| 485 |
+
[78]: ad: 0x7ffff3d8e7ac, op: 325
|
| 486 |
+
new bb detected: 79
|
| 487 |
+
[79]: ad: 0x7ffff3d8e7b2, op: 847
|
| 488 |
+
[79]: ad: 0x7ffff3d8e7b5, op: 325
|
| 489 |
+
new bb detected: 80
|
| 490 |
+
[80]: ad: 0x7ffff3d8e870, op: 427
|
| 491 |
+
[80]: ad: 0x7ffff3d8e87a, op: 109
|
| 492 |
+
[80]: ad: 0x7ffff3d8e87d, op: 98
|
| 493 |
+
[80]: ad: 0x7ffff3d8e881, op: 388
|
| 494 |
+
[80]: ad: 0x7ffff3d8e889, op: 316
|
| 495 |
+
new bb detected: 81
|
| 496 |
+
[81]: ad: 0x7ffff3d8e852, op: 427
|
| 497 |
+
[81]: ad: 0x7ffff3d8e855, op: 427
|
| 498 |
+
[81]: ad: 0x7ffff3d8e859, op: 75
|
| 499 |
+
new bb detected: 82
|
| 500 |
+
[82]: ad: 0x7ffff3d8e85e, op: 427
|
| 501 |
+
[82]: ad: 0x7ffff3d8e862, op: 427
|
| 502 |
+
[82]: ad: 0x7ffff3d8e865, op: 8
|
| 503 |
+
[82]: ad: 0x7ffff3d8e868, op: 316
|
| 504 |
+
new bb detected: 83
|
| 505 |
+
[83]: ad: 0x7ffff3d8e7bf, op: 427
|
| 506 |
+
[83]: ad: 0x7ffff3d8e7c2, op: 826
|
| 507 |
+
[83]: ad: 0x7ffff3d8e7c5, op: 388
|
| 508 |
+
[83]: ad: 0x7ffff3d8e7ca, op: 454
|
| 509 |
+
[83]: ad: 0x7ffff3d8e7cf, op: 427
|
| 510 |
+
[83]: ad: 0x7ffff3d8e7d2, op: 388
|
| 511 |
+
[83]: ad: 0x7ffff3d8e7d6, op: 454
|
| 512 |
+
[83]: ad: 0x7ffff3d8e7db, op: 669
|
| 513 |
+
[83]: ad: 0x7ffff3d8e7df, op: 429
|
| 514 |
+
[83]: ad: 0x7ffff3d8e7e3, op: 847
|
| 515 |
+
[83]: ad: 0x7ffff3d8e7e6, op: 321
|
| 516 |
+
new bb detected: 84
|
| 517 |
+
[84]: ad: 0x7ffff3d8e810, op: 427
|
| 518 |
+
[84]: ad: 0x7ffff3d8e813, op: 75
|
| 519 |
+
new bb detected: 85
|
| 520 |
+
[85]: ad: 0x7ffff3d8e818, op: 847
|
| 521 |
+
[85]: ad: 0x7ffff3d8e81b, op: 321
|
| 522 |
+
new bb detected: 86
|
| 523 |
+
[86]: ad: 0x7ffff3d8e81d, op: 427
|
| 524 |
+
[86]: ad: 0x7ffff3d8e820, op: 75
|
| 525 |
+
new bb detected: 87
|
| 526 |
+
[87]: ad: 0x7ffff3d8e825, op: 316
|
| 527 |
+
new bb detected: 88
|
| 528 |
+
[88]: ad: 0x7ffff3d8e7f2, op: 436
|
| 529 |
+
[88]: ad: 0x7ffff3d8e7f7, op: 427
|
| 530 |
+
[88]: ad: 0x7ffff3d8e7fb, op: 467
|
| 531 |
+
[88]: ad: 0x7ffff3d8e7ff, op: 8
|
| 532 |
+
[88]: ad: 0x7ffff3d8e803, op: 616
|
| 533 |
+
[88]: ad: 0x7ffff3d8e804, op: 616
|
| 534 |
+
[88]: ad: 0x7ffff3d8e805, op: 616
|
| 535 |
+
[88]: ad: 0x7ffff3d8e807, op: 616
|
| 536 |
+
[88]: ad: 0x7ffff3d8e809, op: 616
|
| 537 |
+
[88]: ad: 0x7ffff3d8e80b, op: 616
|
| 538 |
+
[88]: ad: 0x7ffff3d8e80d, op: 740
|
| 539 |
+
new bb detected: 89
|
| 540 |
+
[89]: ad: 0x7ffff3d8e390, op: 427
|
| 541 |
+
[89]: ad: 0x7ffff3d8e394, op: 8
|
| 542 |
+
[89]: ad: 0x7ffff3d8e397, op: 316
|
| 543 |
+
new bb detected: 90
|
| 544 |
+
[90]: ad: 0x7ffff3d8e351, op: 427
|
| 545 |
+
[90]: ad: 0x7ffff3d8e355, op: 427
|
| 546 |
+
[90]: ad: 0x7ffff3d8e358, op: 826
|
| 547 |
+
[90]: ad: 0x7ffff3d8e35c, op: 427
|
| 548 |
+
[90]: ad: 0x7ffff3d8e35e, op: 427
|
| 549 |
+
[90]: ad: 0x7ffff3d8e362, op: 427
|
| 550 |
+
[90]: ad: 0x7ffff3d8e367, op: 826
|
| 551 |
+
[90]: ad: 0x7ffff3d8e370, op: 325
|
| 552 |
+
new bb detected: 91
|
| 553 |
+
[91]: ad: 0x7ffff3d8e372, op: 8
|
| 554 |
+
[91]: ad: 0x7ffff3d8e376, op: 616
|
| 555 |
+
[91]: ad: 0x7ffff3d8e377, op: 616
|
| 556 |
+
[91]: ad: 0x7ffff3d8e378, op: 740
|
| 557 |
+
new bb detected: 92
|
| 558 |
+
[92]: ad: 0x7ffff3d8e46e, op: 427
|
| 559 |
+
[92]: ad: 0x7ffff3d8e471, op: 427
|
| 560 |
+
[92]: ad: 0x7ffff3d8e476, op: 427
|
| 561 |
+
[92]: ad: 0x7ffff3d8e47b, op: 75
|
| 562 |
+
new bb detected: 93
|
| 563 |
+
[93]: ad: 0x7ffff3d8e480, op: 427
|
| 564 |
+
[93]: ad: 0x7ffff3d8e485, op: 427
|
| 565 |
+
[93]: ad: 0x7ffff3d8e489, op: 427
|
| 566 |
+
[93]: ad: 0x7ffff3d8e48c, op: 75
|
| 567 |
+
new bb detected: 94
|
| 568 |
+
[94]: ad: 0x7ffff3d8d1e0, op: 482
|
| 569 |
+
[94]: ad: 0x7ffff3d8d1e4, op: 316
|
| 570 |
+
new bb detected: 95
|
| 571 |
+
[95]: ad: 0x7ffff734bd80, op: 482
|
| 572 |
+
[95]: ad: 0x7ffff734bd84, op: 427
|
| 573 |
+
[95]: ad: 0x7ffff734bd88, op: 454
|
| 574 |
+
[95]: ad: 0x7ffff734bd8d, op: 454
|
| 575 |
+
[95]: ad: 0x7ffff734bd92, op: 669
|
| 576 |
+
[95]: ad: 0x7ffff734bd96, op: 467
|
| 577 |
+
[95]: ad: 0x7ffff734bd99, op: 427
|
| 578 |
+
[95]: ad: 0x7ffff734bd9c, op: 427
|
| 579 |
+
[95]: ad: 0x7ffff734bda0, op: 740
|
| 580 |
+
new bb detected: 96
|
| 581 |
+
[96]: ad: 0x7ffff3d8e491, op: 427
|
| 582 |
+
[96]: ad: 0x7ffff3d8e495, op: 8
|
| 583 |
+
[96]: ad: 0x7ffff3d8e49a, op: 109
|
| 584 |
+
[96]: ad: 0x7ffff3d8e49d, op: 325
|
| 585 |
+
new bb detected: 97
|
| 586 |
+
[97]: ad: 0x7ffff720394d, op: 109
|
| 587 |
+
[97]: ad: 0x7ffff7203954, op: 319
|
| 588 |
+
new bb detected: 98
|
| 589 |
+
[98]: ad: 0x7ffff7203956, op: 1232
|
| 590 |
+
[98]: ad: 0x7ffff720395b, op: 109
|
| 591 |
+
[98]: ad: 0x7ffff7203962, op: 311
|
| 592 |
+
new bb detected: 99
|
| 593 |
+
[99]: ad: 0x7ffff7203911, op: 1232
|
| 594 |
+
[99]: ad: 0x7ffff7203917, op: 1232
|
| 595 |
+
[99]: ad: 0x7ffff720391d, op: 1232
|
| 596 |
+
[99]: ad: 0x7ffff7203921, op: 1232
|
| 597 |
+
[99]: ad: 0x7ffff7203926, op: 1232
|
| 598 |
+
[99]: ad: 0x7ffff720392c, op: 1232
|
| 599 |
+
[99]: ad: 0x7ffff7203932, op: 1704
|
| 600 |
+
[99]: ad: 0x7ffff7203935, op: 740
|
| 601 |
+
new bb detected: 100
|
| 602 |
+
[100]: ad: 0x7ffff710574b, op: 109
|
| 603 |
+
[100]: ad: 0x7ffff7105752, op: 319
|
| 604 |
+
new bb detected: 101
|
| 605 |
+
[101]: ad: 0x7ffff7105758, op: 388
|
| 606 |
+
[101]: ad: 0x7ffff710575d, op: 427
|
| 607 |
+
[101]: ad: 0x7ffff7105761, op: 109
|
| 608 |
+
[101]: ad: 0x7ffff7105765, op: 311
|
| 609 |
+
new bb detected: 102
|
| 610 |
+
[102]: ad: 0x7ffff710576b, op: 31
|
| 611 |
+
[102]: ad: 0x7ffff710576f, op: 109
|
| 612 |
+
[102]: ad: 0x7ffff7105777, op: 318
|
| 613 |
+
new bb detected: 103
|
| 614 |
+
[103]: ad: 0x7ffff710577d, op: 427
|
| 615 |
+
[103]: ad: 0x7ffff7105783, op: 847
|
| 616 |
+
[103]: ad: 0x7ffff7105785, op: 325
|
| 617 |
+
new bb detected: 104
|
| 618 |
+
[104]: ad: 0x7ffff710578b, op: 427
|
| 619 |
+
[104]: ad: 0x7ffff7105794, op: 799
|
| 620 |
+
[104]: ad: 0x7ffff7105797, op: 388
|
| 621 |
+
[104]: ad: 0x7ffff710579a, op: 8
|
| 622 |
+
[104]: ad: 0x7ffff710579e, op: 427
|
| 623 |
+
[104]: ad: 0x7ffff71057a2, op: 427
|
| 624 |
+
[104]: ad: 0x7ffff71057aa, op: 847
|
| 625 |
+
[104]: ad: 0x7ffff71057ac, op: 325
|
| 626 |
+
new bb detected: 105
|
| 627 |
+
[105]: ad: 0x7ffff71057b2, op: 109
|
| 628 |
+
[105]: ad: 0x7ffff71057b5, op: 330
|
| 629 |
+
new bb detected: 106
|
| 630 |
+
[106]: ad: 0x7ffff71057bb, op: 388
|
| 631 |
+
[106]: ad: 0x7ffff71057bf, op: 799
|
| 632 |
+
[106]: ad: 0x7ffff71057c3, op: 1723
|
| 633 |
+
[106]: ad: 0x7ffff71057c6, op: 427
|
| 634 |
+
[106]: ad: 0x7ffff71057ca, op: 427
|
| 635 |
+
[106]: ad: 0x7ffff71057ce, op: 847
|
| 636 |
+
[106]: ad: 0x7ffff71057d1, op: 330
|
| 637 |
+
new bb detected: 107
|
| 638 |
+
[107]: ad: 0x7ffff71057d3, op: 31
|
| 639 |
+
[107]: ad: 0x7ffff71057d7, op: 330
|
| 640 |
+
new bb detected: 108
|
| 641 |
+
[108]: ad: 0x7ffff71080f7, op: 427
|
| 642 |
+
[108]: ad: 0x7ffff71080ff, op: 847
|
| 643 |
+
[108]: ad: 0x7ffff7108101, op: 330
|
| 644 |
+
new bb detected: 109
|
| 645 |
+
[109]: ad: 0x7ffff7108250, op: 388
|
| 646 |
+
[109]: ad: 0x7ffff7108257, op: 427
|
| 647 |
+
[109]: ad: 0x7ffff710825a, op: 427
|
| 648 |
+
[109]: ad: 0x7ffff710825d, op: 75
|
| 649 |
+
new bb detected: 110
|
| 650 |
+
[110]: ad: 0x7ffff71069b0, op: 847
|
| 651 |
+
[110]: ad: 0x7ffff71069b3, op: 329
|
| 652 |
+
new bb detected: 111
|
| 653 |
+
[111]: ad: 0x7ffff71069b9, op: 671
|
| 654 |
+
[111]: ad: 0x7ffff71069bb, op: 388
|
| 655 |
+
[111]: ad: 0x7ffff71069bf, op: 671
|
| 656 |
+
[111]: ad: 0x7ffff71069c1, op: 671
|
| 657 |
+
[111]: ad: 0x7ffff71069c3, op: 671
|
| 658 |
+
[111]: ad: 0x7ffff71069c5, op: 671
|
| 659 |
+
[111]: ad: 0x7ffff71069c6, op: 427
|
| 660 |
+
[111]: ad: 0x7ffff71069c9, op: 671
|
| 661 |
+
[111]: ad: 0x7ffff71069ca, op: 427
|
| 662 |
+
[111]: ad: 0x7ffff71069cd, op: 826
|
| 663 |
+
[111]: ad: 0x7ffff71069d4, op: 109
|
| 664 |
+
[111]: ad: 0x7ffff71069d8, op: 319
|
| 665 |
+
new bb detected: 112
|
| 666 |
+
[112]: ad: 0x7ffff7106af8, op: 31
|
| 667 |
+
[112]: ad: 0x7ffff7106afc, op: 427
|
| 668 |
+
[112]: ad: 0x7ffff7106aff, op: 847
|
| 669 |
+
[112]: ad: 0x7ffff7106b02, op: 330
|
| 670 |
+
new bb detected: 113
|
| 671 |
+
[113]: ad: 0x7ffff7106b08, op: 427
|
| 672 |
+
[113]: ad: 0x7ffff7106b0b, op: 799
|
| 673 |
+
[113]: ad: 0x7ffff7106b0f, op: 109
|
| 674 |
+
[113]: ad: 0x7ffff7106b16, op: 311
|
| 675 |
+
new bb detected: 114
|
| 676 |
+
[114]: ad: 0x7ffff7106d60, op: 388
|
| 677 |
+
[114]: ad: 0x7ffff7106d64, op: 388
|
| 678 |
+
[114]: ad: 0x7ffff7106d68, op: 388
|
| 679 |
+
[114]: ad: 0x7ffff7106d70, op: 427
|
| 680 |
+
[114]: ad: 0x7ffff7106d74, op: 847
|
| 681 |
+
[114]: ad: 0x7ffff7106d77, op: 325
|
| 682 |
+
new bb detected: 115
|
| 683 |
+
[115]: ad: 0x7ffff7106c04, op: 847
|
| 684 |
+
[115]: ad: 0x7ffff7106c07, op: 325
|
| 685 |
+
new bb detected: 116
|
| 686 |
+
[116]: ad: 0x7ffff7106c0d, op: 8
|
| 687 |
+
[116]: ad: 0x7ffff7106c10, op: 427
|
| 688 |
+
[116]: ad: 0x7ffff7106c18, op: 427
|
| 689 |
+
[116]: ad: 0x7ffff7106c1c, op: 847
|
| 690 |
+
[116]: ad: 0x7ffff7106c1e, op: 325
|
| 691 |
+
new bb detected: 117
|
| 692 |
+
[117]: ad: 0x7ffff7106c24, op: 388
|
| 693 |
+
[117]: ad: 0x7ffff7106c28, op: 427
|
| 694 |
+
[117]: ad: 0x7ffff7106c2b, op: 799
|
| 695 |
+
[117]: ad: 0x7ffff7106c2f, op: 1723
|
| 696 |
+
[117]: ad: 0x7ffff7106c32, op: 427
|
| 697 |
+
[117]: ad: 0x7ffff7106c36, op: 427
|
| 698 |
+
[117]: ad: 0x7ffff7106c3a, op: 799
|
| 699 |
+
[117]: ad: 0x7ffff7106c3d, op: 109
|
| 700 |
+
[117]: ad: 0x7ffff7106c40, op: 325
|
| 701 |
+
new bb detected: 118
|
| 702 |
+
[118]: ad: 0x7ffff7106c46, op: 427
|
| 703 |
+
[118]: ad: 0x7ffff7106c4d, op: 388
|
| 704 |
+
[118]: ad: 0x7ffff7106c51, op: 799
|
| 705 |
+
[118]: ad: 0x7ffff7106c55, op: 427
|
| 706 |
+
[118]: ad: 0x7ffff7106c5a, op: 847
|
| 707 |
+
[118]: ad: 0x7ffff7106c5d, op: 330
|
| 708 |
+
new bb detected: 119
|
| 709 |
+
[119]: ad: 0x7ffff7106c63, op: 109
|
| 710 |
+
[119]: ad: 0x7ffff7106c6a, op: 311
|
| 711 |
+
new bb detected: 120
|
| 712 |
+
[120]: ad: 0x7ffff7106c70, op: 468
|
| 713 |
+
[120]: ad: 0x7ffff7106c75, op: 109
|
| 714 |
+
[120]: ad: 0x7ffff7106c7c, op: 388
|
| 715 |
+
[120]: ad: 0x7ffff7106c80, op: 310
|
| 716 |
+
new bb detected: 121
|
| 717 |
+
[121]: ad: 0x7ffff7106cdb, op: 427
|
| 718 |
+
[121]: ad: 0x7ffff7106cdf, op: 847
|
| 719 |
+
[121]: ad: 0x7ffff7106ce2, op: 330
|
| 720 |
+
new bb detected: 122
|
| 721 |
+
[122]: ad: 0x7ffff7106ce8, op: 847
|
| 722 |
+
[122]: ad: 0x7ffff7106ceb, op: 325
|
| 723 |
+
new bb detected: 123
|
| 724 |
+
[123]: ad: 0x7ffff7106cf1, op: 427
|
| 725 |
+
[123]: ad: 0x7ffff7106cf9, op: 427
|
| 726 |
+
[123]: ad: 0x7ffff7106cfd, op: 847
|
| 727 |
+
[123]: ad: 0x7ffff7106cff, op: 330
|
| 728 |
+
new bb detected: 124
|
| 729 |
+
[124]: ad: 0x7ffff7106c90, op: 388
|
| 730 |
+
[124]: ad: 0x7ffff7106c94, op: 427
|
| 731 |
+
[124]: ad: 0x7ffff7106c97, op: 799
|
| 732 |
+
[124]: ad: 0x7ffff7106c9b, op: 1723
|
| 733 |
+
[124]: ad: 0x7ffff7106c9e, op: 427
|
| 734 |
+
[124]: ad: 0x7ffff7106ca2, op: 427
|
| 735 |
+
[124]: ad: 0x7ffff7106ca9, op: 427
|
| 736 |
+
[124]: ad: 0x7ffff7106cad, op: 427
|
| 737 |
+
[124]: ad: 0x7ffff7106cb2, op: 468
|
| 738 |
+
[124]: ad: 0x7ffff7106cb7, op: 1723
|
| 739 |
+
[124]: ad: 0x7ffff7106cbb, op: 427
|
| 740 |
+
[124]: ad: 0x7ffff7106cbf, op: 8
|
| 741 |
+
[124]: ad: 0x7ffff7106cc2, op: 427
|
| 742 |
+
[124]: ad: 0x7ffff7106cc6, op: 427
|
| 743 |
+
[124]: ad: 0x7ffff7106ccb, op: 468
|
| 744 |
+
[124]: ad: 0x7ffff7106cce, op: 109
|
| 745 |
+
[124]: ad: 0x7ffff7106cd5, op: 318
|
| 746 |
+
new bb detected: 125
|
| 747 |
+
[125]: ad: 0x7ffff710706c, op: 427
|
| 748 |
+
[125]: ad: 0x7ffff7107072, op: 847
|
| 749 |
+
[125]: ad: 0x7ffff7107074, op: 325
|
| 750 |
+
new bb detected: 126
|
| 751 |
+
[126]: ad: 0x7ffff7107076, op: 8
|
| 752 |
+
[126]: ad: 0x7ffff710707d, op: 427
|
| 753 |
+
[126]: ad: 0x7ffff7107080, op: 616
|
| 754 |
+
[126]: ad: 0x7ffff7107081, op: 616
|
| 755 |
+
[126]: ad: 0x7ffff7107082, op: 616
|
| 756 |
+
[126]: ad: 0x7ffff7107084, op: 616
|
| 757 |
+
[126]: ad: 0x7ffff7107086, op: 616
|
| 758 |
+
[126]: ad: 0x7ffff7107088, op: 616
|
| 759 |
+
[126]: ad: 0x7ffff710708a, op: 740
|
| 760 |
+
new bb detected: 127
|
| 761 |
+
[127]: ad: 0x7ffff7108262, op: 847
|
| 762 |
+
[127]: ad: 0x7ffff7108265, op: 330
|
| 763 |
+
new bb detected: 128
|
| 764 |
+
[128]: ad: 0x7ffff710826b, op: 427
|
| 765 |
+
[128]: ad: 0x7ffff710826f, op: 847
|
| 766 |
+
[128]: ad: 0x7ffff7108272, op: 325
|
| 767 |
+
new bb detected: 129
|
| 768 |
+
[129]: ad: 0x7ffff7108278, op: 31
|
| 769 |
+
[129]: ad: 0x7ffff710827b, op: 330
|
| 770 |
+
new bb detected: 130
|
| 771 |
+
[130]: ad: 0x7ffff71081a2, op: 8
|
| 772 |
+
[130]: ad: 0x7ffff71081a6, op: 616
|
| 773 |
+
[130]: ad: 0x7ffff71081a7, op: 616
|
| 774 |
+
[130]: ad: 0x7ffff71081a8, op: 616
|
| 775 |
+
[130]: ad: 0x7ffff71081aa, op: 740
|
| 776 |
+
new bb detected: 131
|
| 777 |
+
[131]: ad: 0x7ffff72038b5, op: 109
|
| 778 |
+
[131]: ad: 0x7ffff72038b8, op: 318
|
| 779 |
+
new bb detected: 132
|
| 780 |
+
[132]: ad: 0x7ffff7203900, op: 427
|
| 781 |
+
[132]: ad: 0x7ffff7203905, op: 427
|
| 782 |
+
[132]: ad: 0x7ffff7203908, op: 427
|
| 783 |
+
[132]: ad: 0x7ffff720390b, op: 427
|
| 784 |
+
[132]: ad: 0x7ffff7203910, op: 740
|
| 785 |
+
new bb detected: 133
|
| 786 |
+
Scarab gitrev: 7185dea
|
| 787 |
+
Warning: Scarab expects the trace file type to include OFFLINE_FILE_TYPE_ARCH_REGDEPS (0x20000), but got type: 0xe40
|
| 788 |
+
Scarab started at Fri Jul 17 21:08:30 2026
|
| 789 |
+
|
| 790 |
+
read from initialization: 0x7ffff7108409
|
| 791 |
+
advanceReader: ROI end reached (ordinal 110000002 > roi_end 110000000)
|
| 792 |
+
Reached end of trace (last_inst) pc=0x7ffff3d8de9f
|
| 793 |
+
[60]: ad: 0x7ffff3d8de78, op: 427
|
| 794 |
+
[60]: ad: 0x7ffff3d8de7b, op: 454
|
| 795 |
+
[60]: ad: 0x7ffff3d8de80, op: 8
|
| 796 |
+
[60]: ad: 0x7ffff3d8de83, op: 669
|
| 797 |
+
[60]: ad: 0x7ffff3d8de87, op: 427
|
| 798 |
+
[60]: ad: 0x7ffff3d8de8b, op: 467
|
| 799 |
+
[60]: ad: 0x7ffff3d8de8e, op: 427
|
| 800 |
+
[60]: ad: 0x7ffff3d8de92, op: 427
|
| 801 |
+
[60]: ad: 0x7ffff3d8de96, op: 427
|
| 802 |
+
[60]: ad: 0x7ffff3d8de99, op: 826
|
| 803 |
+
[60]: ad: 0x7ffff3d8de9c, op: 109
|
| 804 |
+
DUP bb detected at trace end
|
| 805 |
+
to be appened segment num 1
|
| 806 |
+
10000000
|
| 807 |
+
10000000
|
| 808 |
+
====================================
|
| 809 |
+
TRACE_INST_TAKEN_NOT_CF:0
|
| 810 |
+
TRACE_INST_TAKEN_CF_BR:159172
|
| 811 |
+
TRACE_INST_TAKEN_CF_CBR:281835
|
| 812 |
+
TRACE_INST_TAKEN_CF_REP:0
|
| 813 |
+
TRACE_INST_TAKEN_CF_CALL:239388
|
| 814 |
+
TRACE_INST_TAKEN_CF_IBR:205779
|
| 815 |
+
TRACE_INST_TAKEN_CF_ICALL:0
|
| 816 |
+
TRACE_INST_TAKEN_CF_ICO:0
|
| 817 |
+
TRACE_INST_TAKEN_CF_RET:239387
|
| 818 |
+
TRACE_INST_TAKEN_CF_SYS:0
|
| 819 |
+
====================================
|
| 820 |
+
identity within this segment
|
| 821 |
+
2 bbs with same first pc
|
| 822 |
+
[60]: size 12, freq 8231
|
| 823 |
+
7ffff3d8de78: 427, 0
|
| 824 |
+
7ffff3d8de7b: 454, 0
|
| 825 |
+
7ffff3d8de80: 8, 0
|
| 826 |
+
7ffff3d8de83: 669, 0
|
| 827 |
+
7ffff3d8de87: 427, 0
|
| 828 |
+
7ffff3d8de8b: 467, 0
|
| 829 |
+
7ffff3d8de8e: 427, 0
|
| 830 |
+
7ffff3d8de92: 427, 0
|
| 831 |
+
7ffff3d8de96: 427, 0
|
| 832 |
+
7ffff3d8de99: 826, 0
|
| 833 |
+
7ffff3d8de9c: 109, 0
|
| 834 |
+
7ffff3d8de9f: 330, 0
|
| 835 |
+
[60]: size 11, freq 1
|
| 836 |
+
7ffff3d8de78: 427, 0
|
| 837 |
+
7ffff3d8de7b: 454, 0
|
| 838 |
+
7ffff3d8de80: 8, 0
|
| 839 |
+
7ffff3d8de83: 669, 0
|
| 840 |
+
7ffff3d8de87: 427, 0
|
| 841 |
+
7ffff3d8de8b: 467, 0
|
| 842 |
+
7ffff3d8de8e: 427, 0
|
| 843 |
+
7ffff3d8de92: 427, 0
|
| 844 |
+
7ffff3d8de96: 427, 0
|
| 845 |
+
7ffff3d8de99: 826, 0
|
| 846 |
+
7ffff3d8de9c: 109, 0
|
| 847 |
+
1 / 133
|
| 848 |
+
========================================================
|
| 849 |
+
Number of blocks built : 133
|
| 850 |
+
Average size : 4.90 instructions
|
| 851 |
+
Number of blocks executed : 2120156
|
| 852 |
+
Average weighted size : 4.72 instructions
|
| 853 |
+
Number of total instructions : 10000000
|
| 854 |
+
Number of fetched instruction : 10000000
|
| 855 |
+
========================================================
|
| 856 |
+
Scarab finished at Fri Jul 17 21:08:35 2026
|
| 857 |
+
|