--mode trace_bbv_distributed --model cmp --frontend memtrace --sim_limit none --memtrace_roi_begin 100000001 --memtrace_roi_end 110000000 --use_fetched_count 1 --dump_params 1 --dump_stats 1 --dump_trace 0 --trace_bbv_output /dev/shm/baseline/traces/pagerank-web-Google/fingerprint/pieces/segment.10 --trace_footprint_output /dev/shm/baseline/traces/pagerank-web-Google/fingerprint/footprint_pieces/segment.10 --segment_instr_count 10000000 --mlc_present 1 --mlc_size 2097000 --mlc_assoc 8 --mlc_cycles 16 --l1_size 3145728 --l1_assoc 16 --l1_line_size 64 --l1_cycles 36 // just a guess --l1_banks 8 --l1_interleave_factor 64 --addr_translation random --icache_size 32768 --icache_assoc 8 --icache_line_size 64 --uop_cache_enable 1 --uop_cache_width 8 --uop_cache_lines 512 # 8 x 512 = 4096 uops in total (~4K) --uop_cache_assoc 8 --iprf_on_uop_cache_hit 1 --dcache_size 49152 --dcache_assoc 12 --dcache_line_size 64 --dcache_cycles 5 --dcache_read_ports 1 --dcache_write_ports 1 --dcache_banks 8 --mem_ooo_stores 1 --mem_obey_store_dep 1 --mem_req_buffer_entries 32 --mem_priority_ifetch 0 --mem_priority_dfetch 1 --mem_priority_dstore 2 --mem_priority_iprf 3 --mem_priority_dprf 4 --mem_priority_wb 5 --mem_priority_wb_nodirty 5 --promote_to_higher_priority_mem_req_type 1 --mem_req_buffer_pref_watermark 4 --order_beyond_bus 1 --set_off_path_confirmed 1 --ramulator_standard DDR4 --ramulator_speed DDR4_2400R --ramulator_org DDR4_8Gb_x8 --ramulator_channels 1 --ramulator_ranks 1 --ramulator_bankgroups 4 --ramulator_banks 4 --ramulator_chip_width 8 --bus_width_in_bytes 8 --ramulator_rows 65536 --ramulator_cols 1024 --ramulator_scheduling_policy FRFCFS_Cap --ramulator_readq_entries 32 --ramulator_writeq_entries 32 --ramulator_record_cmd_trace FALSE --ramulator_print_cmd_trace FALSE --ramulator_tCK 833333 --ramulator_tCL 16 --ramulator_tCCD 6 --ramulator_tCCDS 4 --ramulator_tCCDL 6 --ramulator_tCWL 12 --ramulator_tBL 4 --ramulator_tWTR 9 --ramulator_tWTRS 3 --ramulator_tWTRL 9 --ramulator_tRP 16 --ramulator_tRPpb 16 --ramulator_tRPab 16 --ramulator_tRCD 16 --ramulator_tRCDR 16 --ramulator_tRCDW 16 --ramulator_tRAS 39 --dram_tech_in_nm 32 --chip_cycle_time 312500 --issue_width 6 --rs_fill_width 0 --node_table_size 512 --node_ret_width 8 --decode_width 6 --idq_size 144 --reg_renaming_scheme 1 --reg_table_integer_physical_size 280 --reg_table_vector_physical_size 332 --rs_sizes 97 70 19 --rs_connections b0100110011 b1000001100 b0011000000 --fu_types b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001 --decode_cycles 5 --map_cycles 5 --fetch_off_path_ops 1 --stores_do_not_block_window 1 --prefs_do_not_block_window 1 --cbp_trace_r0 /dev/shm/baseline/traces/.staging/pagerank-web-Google-173917/raw_trace/drmemtrace.pagerank.173929.4303.dir/trace/drmemtrace.pagerank.173929.7791.trace.zip --debug_cycle_start 0 --debug_cycle_stop -1 --debug_inst_start 0 --debug_inst_stop -1 --perfect_nt_btb 0 # deprecated, effectively always true. --cfs_per_cycle 6 # Number of branches that can be predicted in a single cycle --update_bp_off_path 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). --bp_update_at_retire 0 # Update the BP at retire. If false, update at the end of exec. --bp_mech tage64k --btb_mech generic --btb_entries 12288 --btb_assoc 4 --btb_off_path_writes 1 --btb_main_latency 3 --btb_l0_present 1 --btb_l0_entries 128 --btb_l0_assoc 4 --btb_l0_latency 1 --btb_l1_present 1 --btb_l1_entries 6144 --btb_l1_assoc 4 --btb_l1_latency 2 --enable_crs 1 --crs_entries 128 --crs_realistic 1 --enable_ibp 1 # Enable the indirect branch predictor --ibtb_mech tc_tagged --ibtb_off_path_writes 1 # Allow off path ops to update the ibtb. --tc_entries 4096 --tc_assoc 4 --pref_stream_on 1 --stream_prefetch_n 4 --stream_start_dis 1 --stream_length 64 --stream_train_num 4 --stream_create_on_dc_miss 0 --stream_create_on_l1_miss 1 --pref_framework_on 1 --pref_ul1req_queue_overwrite_on_full 1 --pref_train_on_pref_misses 0 --pref_oracle_train_on 0 --pref_throttlefb_on 1 --pref_acc_thresh_1 0.75 --pref_acc_thresh_2 0.4 --pref_acc_thresh_3 0.4 --pref_update_interval 8192 --pref_timely_thresh 0.01 --pref_polpf_thresh 0.005 1 1 1 1 1 1 1 --- Cut out everything below to use this file as PARAMS.in --- Parameter status at compile time and values supplied on the command line: SIM_MODE 0 trace_bbv_distributed SIM_MODEL 0 cmp FRONTEND FE_PIN_EXEC_DRIVEN memtrace INST_LIMIT NULL SIM_LIMIT "none" none FORWARD_PROGRESS_LIMIT 100000000 FORWARD_PROGRESS_INTERVAL 10000 FAST_FORWARD 0 FAST_FORWARD_TRACE_INS 0 FAST_FORWARD_UNTIL_ADDR 0 MEMTRACE_ROI_BEGIN 0 100000001 MEMTRACE_ROI_END 0 110000000 FULL_WARMUP 0 WARMUP 0 HEARTBEAT_INTERVAL 1000000 NUM_HEARTBEATS 0 USE_FETCHED_COUNT FALSE 1 PERIODIC_DUMP FALSE FILE_TAG "" OUTPUT_DIR "." STATUS_FILE NULL BINDIR NULL DUMP_PARAMS TRUE 1 DUMP_STATS TRUE 1 DUMP_TRACE FALSE 0 CLEAR_STATS "never" STATS_TO_TRACE NULL STAT_TRACE_FILE "stats.trace" STAT_TRACE_INTERVAL "i:100000" PIPEVIEW FALSE PIPEVIEW_FILE "pipeview" MEMVIEW FALSE MEMVIEW_FILE "memview.out" MEMVIEW_START "never" INST_HASH_TABLE_SIZE 524288 const STDOUT_FILE NULL STDERR_FILE NULL PIN_EXEC_DRIVEN_FE_SOCKET "./pin_exec_driven_fe_socket.temp" PRINT_PID FALSE USE_UNSURE_FREE_LISTS FALSE OPTIMIZER2_MAX_NUM_SLAVES 64 OPTIMIZER2_PERFECT_MEMORYLESS FALSE EXIT_COND 0 NUM_NOPS 0 NOPS_BB_START 0x5000000 IGNORE_BAR_FETCH FALSE TRACE_BBV_OUTPUT NULL /dev/shm/baseline/traces/pagerank-web-Google/fingerprint/pieces/segment.10 TRACE_FOOTPRINT_OUTPUT "" /dev/shm/baseline/traces/pagerank-web-Google/fingerprint/footprint_pieces/segment.10 SEGMENT_INSTR_COUNT 0 10000000 ENABLE_SWPRF FALSE MLC_PRESENT FALSE 1 MLC_SIZE (512 * 1024) 2097000 MLC_ASSOC 4 8 MLC_LINE_SIZE 64 MLC_CYCLES 12 16 PERFECT_MLC FALSE MLC_READ_PORTS 1 MLC_WRITE_PORTS 1 MLC_BANKS 8 MLC_INTERLEAVE_FACTOR 64 MLC_CACHE_REPL_POLICY 0 MLC_WRITE_THROUGH FALSE PREFETCH_UPDATE_LRU_MLC TRUE FORCE_L1_MISS FALSE L1_SIZE (4 * 1024 * 1024) 3145728 L1_ASSOC 8 16 L1_LINE_SIZE 64 64 L1_CYCLES 24 36 // just a guess PERFECT_L1 FALSE PRIVATE_L1 FALSE L1_READ_PORTS 1 L1_WRITE_PORTS 1 L1_BANKS 8 8 L1_INTERLEAVE_FACTOR 64 64 L1_CACHE_REPL_POLICY 0 L1_WRITE_THROUGH FALSE L1_IGNORE_WB FALSE L1_USE_CORE_FREQ FALSE MARK_L1_MISSES TRUE PREFETCH_UPDATE_LRU_L1 TRUE MEMORY_RANDOM_ADDR FALSE VA_PAGE_SIZE_BYTES 4096 NUM_ADDR_NON_SIGN_EXTEND_BITS 48 ADDR_TRANSLATION 0 random CONSTANT_MEMORY_LATENCY FALSE MEMORY_CYCLES 100 STALL_MEM_REQS_ONLY FALSE ICACHE_SIZE (64 * 1024) 32768 ICACHE_ASSOC 4 8 ICACHE_LINE_SIZE 64 64 PERFECT_ICACHE FALSE ICACHE_READ_PORTS 1 ICACHE_WRITE_PORTS 1 ICACHE_BANKS 8 ICACHE_REPL 0 UOP_CACHE_ENABLE 1 1 UOP_CACHE_WIDTH 6 8 ALWAYS_LOOKUP_ICACHE 0 UOP_CACHE_INSERT_ONLY_ONPATH FALSE UOP_CACHE_READ_PORTS 1 UOP_CACHE_LINES 384 512 # 8 x 512 = 4096 uops in total (~4K) UOP_CACHE_ASSOC 8 8 UOP_CACHE_MAX_IMM_DISP_LINE 4 IPRF_ON_UOP_CACHE_HIT FALSE 1 UOP_CACHE_REPL 0 PRIORITY_LINE_STICKINESS_PERCENT 50 PW_PRIORITY_LIST_FILEPATH "pw_priority_list.csv" NUM_PRIORITY_PWS 10 PRIORITIZE_PWS_AFTER_FIRST_STICKY_UNTIL_BACKEND_STALL FALSE NO_REPL_AFTER_QUEUE_SIZE 0 FDIP_UC_SIZE 0 FDIP_UC_ASSOC 4 FDIP_UC_INSERT_REPLPOL 0 MAP_STAGE_CONSUME_FROM_ICACHE_AND_UOC_SAME_CYCLE TRUE UOP_QUEUE_LENGTH 7 DCACHE_SIZE (64 * 1024) 49152 DCACHE_ASSOC 1 12 DCACHE_LINE_SIZE 64 64 DCACHE_CYCLES 2 5 PERFECT_DCACHE FALSE DCACHE_READ_PORTS 8 1 DCACHE_WRITE_PORTS 1 1 DCACHE_BANKS 1 8 DCACHE_INTERLEAVE_FACTOR 4 DCACHE_REPL 0 DCACHE_REPL_PREF_THRESH 1 MEM_OOO_STORES TRUE 1 MEM_OBEY_STORE_DEP TRUE 1 PREF_INSERT_LRU FALSE PREF_INSERT_MIDDLE FALSE PREF_INSERT_LOWQTR FALSE PREF_INSERT_DYNACC FALSE MEM_REQ_BUFFER_ENTRIES 32 32 PRIVATE_MSHR_ON TRUE MEM_PRIORITY_IFETCH 0 0 MEM_PRIORITY_DFETCH 0 1 MEM_PRIORITY_DSTORE 0 2 MEM_PRIORITY_IPRF 9 3 MEM_PRIORITY_UOCPRF 9 MEM_PRIORITY_FDIPPRFON 8 MEM_PRIORITY_FDIPPRFOFF 9 MEM_PRIORITY_DPRF 10 4 MEM_PRIORITY_WB 0 5 MEM_PRIORITY_WB_NODIRTY 0 5 PROMOTE_TO_HIGHER_PRIORITY_MEM_REQ_TYPE FALSE 1 MEM_REQ_BUFFER_PREF_WATERMARK 0 4 MEM_REQ_BUFFER_WB_VALVE 2 MEM_L1_FILL_QUEUE_ENTRIES 32 MEM_BUS_OUT_QUEUE_PARTITION_ENABLE FALSE MEM_MEM_QUEUE_PARTITION_ENABLE FALSE MEM_BUS_OUT_QUEUE_AS_FIFO TRUE OLDEST_FIRST_TO_MEM_QUEUE TRUE ROUND_ROBIN_TO_MEM_QUEUE FALSE ONE_CORE_FIRST_TO_MEM_QUEUE FALSE ONE_CORE_FIRST_TO_MEM_QUEUE_TH 0 L1_CYCLE_TIME 312500 MLCQ_TO_L1Q_TRANSFER_LATENCY 1 L1Q_TO_FSB_TRANSFER_LATENCY 1 PRIORITIZE_PREFETCHES_WITH_UNIQUE FALSE KICKOUT_PREFETCHES FALSE KICKOUT_LOOK_FOR_OLDEST_FIRST FALSE KICKOUT_OLDEST_PREFETCH FALSE KICKOUT_OLDEST_PREFETCH_WITHIN_BANK FALSE ORDER_BEYOND_BUS FALSE 1 ALL_FIFO_QUEUES FALSE QUEUE_MLC_SIZE 0 QUEUE_L1_SIZE 0 QUEUE_BUS_OUT_SIZE 0 QUEUE_CORE_FILL_SIZE 0 ALLOW_TYPE_MATCHES FALSE STREAM_PREFETCH_ON FALSE DC_PREF_CACHE_ENABLE FALSE DC_PREF_CACHE_CYCLE 0 PREF_INSERT_DCACHE_IMM TRUE DC_PREF_CACHE_SIZE (64 * 1024) DC_PREF_CACHE_ASSOC 4 DC_PREF_ONLY_L1HIT FALSE PREF_CACHE_USE_RDY_CYCLE FALSE IC_PREF_CACHE_ENABLE FALSE IC_PREF_CACHE_SIZE (64 * 1024) IC_PREF_CACHE_ASSOC 4 L1_PREF_CACHE_ENABLE FALSE L1_PREF_CACHE_SIZE (1024 * 1024) L1_PREF_CACHE_ASSOC 8 SET_OFF_PATH_CONFIRMED FALSE 1 USE_CONFIRMED_OFF FALSE PREFCACHE_MOVE_OFFPATH FALSE CACHE_STAT_ENABLE FALSE PREF_DCACHE_HIT_FILL_L1 TRUE PREF_ICACHE_HIT_FILL_L1 TRUE CRITICAL_ACCESS_PLOT_ENABLE FALSE CRITICAL_ACCESS_PLOT_FILE "critical_access_plot.dat" ROUND_ROBIN_TO_L1 FALSE PREF_I_TOGETHER FALSE ONE_MORE_CACHE_LINE_ENABLE FALSE L1_STATIC_PARTITION_ENABLE 0 L1_STATIC_PARTITION NULL L1_DYNAMIC_PARTITION_ENABLE FALSE L1_DYNAMIC_PARTITION_POLICY 0 PARTITION_UMON_DSS_PREF_ENABLE FALSE L1_CACHE_HIT_POSITION_COLLECT FALSE L1_PART_ON FALSE L1_PART_TRIGGER "c:1000000" L1_PART_START "t:0" L1_PART_WARMUP FALSE L1_PART_SHADOW_WARMUP FALSE L1_PART_METRIC 0 L1_PART_SEARCH 0 L1_PART_USE_STALLING TRUE L1_PART_FILL_DELAY 0 L1_SHADOW_TAGS_MODULO 1 HIER_MSHR_ON FALSE PERF_PRED_ENABLE FALSE PERF_PRED_MECH PERF_PRED_CP PERF_PRED_REQ_LATENCY_MECH PERF_PRED_REQ_LATENCY_MECH_REQ_LATENCY PERF_PRED_COUNT_ALL FALSE PERF_PRED_COUNT_INST_MISSES TRUE PERF_PRED_COUNT_PREFETCHES FALSE PERF_PRED_COUNT_OFFPATH_REQS FALSE PERF_PRED_COUNT_BW_REQS TRUE PERF_PRED_UPDATE_MEM_REQ_TYPE FALSE PERF_PRED_SLACK_PERIOD_SIZE 32 PERF_PRED_REQS_FINISH_AT_FILL FALSE PERF_PRED_MEM_UTIL_VIA_BUS_BW FALSE PERF_PRED_CHIP_UTIL_VIA_MEM_STALL FALSE DUMB_MODEL_AVG_REQ_DISTANCE 100 DUMB_MODEL_RANDOMIZE_DISTANCE FALSE DUMB_MODEL_AVG_REQ_DISTANCE_PER_CORE NULL DUMB_MODEL_AVG_ROW_HITS 1 DUMB_MODEL_AVG_ROW_HITS_PER_CORE NULL DUMB_MODEL_MLP 1 DUMB_MODEL_MLP_PER_CORE NULL RAMULATOR_STANDARD "DDR4" DDR4 RAMULATOR_SPEED "DDR4_2400R" DDR4_2400R RAMULATOR_ORG "DDR4_8Gb_x8" DDR4_8Gb_x8 RAMULATOR_CHANNELS 1 1 RAMULATOR_RANKS 1 1 RAMULATOR_BANKGROUPS 4 4 RAMULATOR_BANKS 4 4 RAMULATOR_CHIP_WIDTH 8 8 BUS_WIDTH_IN_BYTES 8 8 RAMULATOR_ROWS 65536 65536 RAMULATOR_COLS 1024 1024 RAMULATOR_SCHEDULING_POLICY "FRFCFS_Cap" FRFCFS_Cap RAMULATOR_READQ_ENTRIES 32 32 RAMULATOR_WRITEQ_ENTRIES 32 32 RAMULATOR_REC_CMD_TRACE "off" FALSE RAMULATOR_PRINT_CMD_TRACE "off" FALSE RAMULATOR_USE_REST_OF_ADDR_AS_ROW_ADDR "on" RAMULATOR_TCK 833333 833333 RAMULATOR_TCL 16 16 RAMULATOR_TCCD 6 6 RAMULATOR_TCCDS 4 4 RAMULATOR_TCCDL 6 6 RAMULATOR_TCWL 12 12 RAMULATOR_TBL 4 4 RAMULATOR_TWTR 9 9 RAMULATOR_TWTRS 3 3 RAMULATOR_TWTRL 9 9 RAMULATOR_TRP 16 16 RAMULATOR_TRPpb 16 16 RAMULATOR_TRPab 16 16 RAMULATOR_TRCD 16 16 RAMULATOR_TRCDR 16 16 RAMULATOR_TRCDW 16 16 RAMULATOR_TRAS 39 39 DRAM_TECH_IN_NM 32 32 DVFS_ON FALSE DVFS_METRIC DVFS_METRIC_NUM_ELEMS DVFS_CONFIGS NULL DVFS_CONFIG_FILE NULL DVFS_START "t:0" DVFS_PERIOD "t:312500000000" DVFS_LOG TRUE DVFS_INDIVIDUAL_CORES FALSE DVFS_CHIP_LEVEL FALSE DVFS_STATIC NULL DVFS_FORCE_CONFIG NULL DVFS_REPLAY_CONFIG_TRACE NULL DVFS_USE_ORACLE FALSE DVFS_USE_BW_SHARING FALSE DVFS_USE_DRAM_SHARING FALSE DVFS_USE_STALL_TIME FALSE DVFS_DRAM_SHARING_SOLVER_BIN NULL DVFS_DRAM_SHARING_SOLVER_STRICT TRUE DVFS_BW_SHARING_BUS_UTIL_THRESH 0.95 DVFS_BW_SHARING_MAX_REQS 28.0 DVFS_BW_SHARING_MAX_RW_COST 0.25 DVFS_BW_SHARING_NO_PREF_STALL TRUE DVFS_BW_SHARING_CRIT_STATS TRUE DVFS_COUNT_L1_ACCESS_STALL FALSE NUM_CORES 1 CHIP_CYCLE_TIME 312500 312500 CORE_0_CYCLE_TIME 312500 CORE_1_CYCLE_TIME 312500 CORE_2_CYCLE_TIME 312500 CORE_3_CYCLE_TIME 312500 CORE_4_CYCLE_TIME 312500 CORE_5_CYCLE_TIME 312500 CORE_6_CYCLE_TIME 312500 CORE_7_CYCLE_TIME 312500 CORE_8_CYCLE_TIME 312500 CORE_9_CYCLE_TIME 312500 CORE_10_CYCLE_TIME 312500 CORE_11_CYCLE_TIME 312500 CORE_12_CYCLE_TIME 312500 CORE_13_CYCLE_TIME 312500 CORE_14_CYCLE_TIME 312500 CORE_15_CYCLE_TIME 312500 CORE_16_CYCLE_TIME 312500 CORE_17_CYCLE_TIME 312500 CORE_18_CYCLE_TIME 312500 CORE_19_CYCLE_TIME 312500 CORE_20_CYCLE_TIME 312500 CORE_21_CYCLE_TIME 312500 CORE_22_CYCLE_TIME 312500 CORE_23_CYCLE_TIME 312500 CORE_24_CYCLE_TIME 312500 CORE_25_CYCLE_TIME 312500 CORE_26_CYCLE_TIME 312500 CORE_27_CYCLE_TIME 312500 CORE_28_CYCLE_TIME 312500 CORE_29_CYCLE_TIME 312500 CORE_30_CYCLE_TIME 312500 CORE_31_CYCLE_TIME 312500 CORE_32_CYCLE_TIME 312500 CORE_33_CYCLE_TIME 312500 CORE_34_CYCLE_TIME 312500 CORE_35_CYCLE_TIME 312500 CORE_36_CYCLE_TIME 312500 CORE_37_CYCLE_TIME 312500 CORE_38_CYCLE_TIME 312500 CORE_39_CYCLE_TIME 312500 CORE_40_CYCLE_TIME 312500 CORE_41_CYCLE_TIME 312500 CORE_42_CYCLE_TIME 312500 CORE_43_CYCLE_TIME 312500 CORE_44_CYCLE_TIME 312500 CORE_45_CYCLE_TIME 312500 CORE_46_CYCLE_TIME 312500 CORE_47_CYCLE_TIME 312500 CORE_48_CYCLE_TIME 312500 CORE_49_CYCLE_TIME 312500 CORE_50_CYCLE_TIME 312500 CORE_51_CYCLE_TIME 312500 CORE_52_CYCLE_TIME 312500 CORE_53_CYCLE_TIME 312500 CORE_54_CYCLE_TIME 312500 CORE_55_CYCLE_TIME 312500 CORE_56_CYCLE_TIME 312500 CORE_57_CYCLE_TIME 312500 CORE_58_CYCLE_TIME 312500 CORE_59_CYCLE_TIME 312500 CORE_60_CYCLE_TIME 312500 CORE_61_CYCLE_TIME 312500 CORE_62_CYCLE_TIME 312500 CORE_63_CYCLE_TIME 312500 TOPDOWN_FU_EXEC_FEW 0 ISSUE_WIDTH 4 6 RS_FILL_WIDTH 8 0 NODE_TABLE_SIZE 256 512 NODE_RET_WIDTH 4 8 NODE_RETIRE_RATE 10 DECODE_WIDTH 4 6 IDQ_SIZE 140 144 REG_RENAMING_SCHEME 0 1 REG_TABLE_INTEGER_PHYSICAL_SIZE 256 280 REG_TABLE_VECTOR_PHYSICAL_SIZE 256 332 REG_TABLE_INTEGER_VIRTUAL_SIZE 256 REG_TABLE_VECTOR_VIRTUAL_SIZE 256 REG_RENAMING_MOVE_ELIMINATE FALSE NODE_ISSUE_QUEUE_DISPATCH_SCHEME 0 NODE_ISSUE_QUEUE_SCHEDULE_SCHEME 0 ISSUE_QUEUE_PARALLEL_PICK FALSE RS_SIZES "256" 97 70 19 RS_CONNECTIONS "xF" b0100110011 b1000001100 b0011000000 FU_TYPES "0, 0, 0, 0" b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001 LSQ_ENABLE TRUE LOAD_QUEUE_ENTRY_NUM 128 STORE_QUEUE_ENTRY_NUM 72 DECODE_CYCLES 1 5 MAP_CYCLES 1 5 ICACHE_LATENCY 3 EXTRA_REDIRECT_CYCLES 0 EXTRA_RECOVERY_CYCLES 0 EXTRA_CALLSYS_CYCLES 20 const DIE_ON_CALLSYS FALSE DIE_ON_RET_STALL_THRESH 0 DIE_ON_RET_STALL_CORE 0 DIE_ON_MEM_BLOCK_THRESH 0 DIE_ON_MEM_BLOCK_CORE 0 ICACHE_FETCH_ACROSS_FETCH_TARGET TRUE UOP_CACHE_FETCH_ACROSS_FETCH_TARGET TRUE FETCH_OFF_PATH_OPS TRUE 1 WP_COLLECT_STATS TRUE OP_INV_DELAY 1 OP_NOP_DELAY 1 OP_CF_DELAY 1 OP_MOV_DELAY 1 OP_CMOV_DELAY 1 OP_LDA_DELAY 1 OP_ILD_DELAY 1 OP_IST_DELAY 1 OP_IADD_DELAY 1 OP_IMUL_DELAY 3 OP_IDIV_DELAY -20 OP_ICMP_DELAY 1 OP_LOGIC_DELAY 1 OP_SHIFT_DELAY 1 OP_FLD_DELAY 1 OP_FST_DELAY 1 OP_FCVT_DELAY 3 OP_FADD_DELAY 3 OP_FMUL_DELAY 5 OP_FMA_DELAY 5 OP_FDIV_DELAY -20 OP_FCMP_DELAY 3 OP_FCMOV_DELAY 1 OP_GATHER_DELAY 12 OP_SCATTER_DELAY 18 OP_PIPELINED_FAST_DELAY 2 OP_PIPELINED_MEDIUM_DELAY 5 OP_PIPELINED_SLOW_DELAY 10 OP_NOTPIPELINED_MEDIUM_DELAY -5 OP_NOTPIPELINED_SLOW_DELAY -20 OP_NOTPIPELINED_VERY_SLOW_DELAY -100 UNIFORM_OP_DELAY 0 STALL_ON_WAIT_MEM TRUE STORES_DO_NOT_BLOCK_WINDOW FALSE 1 PREFS_DO_NOT_BLOCK_WINDOW FALSE 1 OBEY_REG_DEP TRUE TRACK_L1_MISS_DEPS FALSE CBP_TRACE_R0 NULL /dev/shm/baseline/traces/.staging/pagerank-web-Google-173917/raw_trace/drmemtrace.pagerank.173929.4303.dir/trace/drmemtrace.pagerank.173929.7791.trace.zip CBP_TRACE_R1 NULL CBP_TRACE_R2 NULL CBP_TRACE_R3 NULL CBP_TRACE_R4 NULL CBP_TRACE_R5 NULL CBP_TRACE_R6 NULL CBP_TRACE_R7 NULL CBP_TRACE_R8 NULL CBP_TRACE_R9 NULL CBP_TRACE_R10 NULL CBP_TRACE_R11 NULL CBP_TRACE_R12 NULL CBP_TRACE_R13 NULL CBP_TRACE_R14 NULL CBP_TRACE_R15 NULL CBP_TRACE_R16 NULL CBP_TRACE_R17 NULL CBP_TRACE_R18 NULL CBP_TRACE_R19 NULL CBP_TRACE_R20 NULL CBP_TRACE_R21 NULL CBP_TRACE_R22 NULL CBP_TRACE_R23 NULL CBP_TRACE_R24 NULL CBP_TRACE_R25 NULL CBP_TRACE_R26 NULL CBP_TRACE_R27 NULL CBP_TRACE_R28 NULL CBP_TRACE_R29 NULL CBP_TRACE_R30 NULL CBP_TRACE_R31 NULL CBP_TRACE_R32 NULL CBP_TRACE_R33 NULL CBP_TRACE_R34 NULL CBP_TRACE_R35 NULL CBP_TRACE_R36 NULL CBP_TRACE_R37 NULL CBP_TRACE_R38 NULL CBP_TRACE_R39 NULL CBP_TRACE_R40 NULL CBP_TRACE_R41 NULL CBP_TRACE_R42 NULL CBP_TRACE_R43 NULL CBP_TRACE_R44 NULL CBP_TRACE_R45 NULL CBP_TRACE_R46 NULL CBP_TRACE_R47 NULL CBP_TRACE_R48 NULL CBP_TRACE_R49 NULL CBP_TRACE_R50 NULL CBP_TRACE_R51 NULL CBP_TRACE_R52 NULL CBP_TRACE_R53 NULL CBP_TRACE_R54 NULL CBP_TRACE_R55 NULL CBP_TRACE_R56 NULL CBP_TRACE_R57 NULL CBP_TRACE_R58 NULL CBP_TRACE_R59 NULL CBP_TRACE_R60 NULL CBP_TRACE_R61 NULL CBP_TRACE_R62 NULL CBP_TRACE_R63 NULL FE_FTQ_BLOCK_NUM 32 FE_FTQ_TAKEN_CFS_PER_CYCLE 2 FE_FTQ_FT_PER_CYCLE 1 DUMB_CORE_ON FALSE DUMB_CORE 1 DCACHE_MISS_RATE 10 L1_MISS_RATE 10 TRACE_BUF_SIZE 0 PERFECT_CONFIDENCE FALSE CONFIDENCE_ENABLE FALSE CONFIDENCE_MECH 0 CONF_OFF_PATH_THRESHOLD 15 CONF_OFF_PATH_INC 5 CONF_BTB_MISS_BP_TAKEN FALSE CONF_IPC_RATE_CONF FALSE CONF_BTB_MISS_BP_TAKEN_THRESHOLD 0 CONF_BTB_MISS_RATE_CYCLES_THRESHOLD 1.0 CONF_IBTB_MISS_RATE_CYCLES_THRESHOLD 1.0 CONF_MISFETCH_RATE_CYCLES_THRESHOLD 1.0 CONF_MISPRED_RATE_CYCLES_THRESHOLD 1.0 CONF_BTB_MISS_SAMPLE_RATE 100000 CONF_IBTB_MISS_SAMPLE_RATE 100000 CONF_MISFETCH_SAMPLE_RATE 100000 CONF_MISPRED_SAMPLE_RATE 100000 CONF_IPC_SAMPLE_RATE 100000 CONF_BTB_MISS_RATE_WEIGHT 200 CONF_BTB_MISS_BP_TAKEN_CONF TRUE CONF_IBTB_MISS_BP_TAKEN_CONF TRUE CONF_BTB_MISS_RATE_CONF TRUE CONF_IBTB_MISS_RATE_CONF TRUE CONF_MISFETCH_RATE_CONF TRUE CONF_MISPRED_RATE_CONF TRUE CONF_INV_BP_CONF TRUE CONF_PERFECT_BTB_MISS_CONF FALSE CONF_PERFECT_IBTB_MISS_CONF FALSE CONF_PERFECT_MISFETCH_CONF FALSE CONF_PERFECT_MISPRED_CONF FALSE CONF_LOG_DFE_TO_REC FALSE CONF_LOG_PHASE_CYCLES FALSE NUM_BPS 1 DFE0_TRIGGER_POLICY 0 DFE1_TRIGGER_POLICY 1 DFE2_TRIGGER_POLICY 1 DFE3_TRIGGER_POLICY 1 DFE4_TRIGGER_POLICY 1 DFE0_STOP_POLICY 0 DFE1_STOP_POLICY 1 DFE2_STOP_POLICY 1 DFE3_STOP_POLICY 1 DFE4_STOP_POLICY 1 LOOKAHEAD_BUF_SIZE 0 DEBUG_CYCLE_START 0 0 DEBUG_CYCLE_STOP 0 -1 DEBUG_TIME_START 0 DEBUG_TIME_STOP 0 DEBUG_INST_START 0 0 DEBUG_INST_STOP 0 -1 DEBUG_OP_START 0 DEBUG_OP_STOP 0 DEBUG_CACHE_LIB FALSE DEBUG_HASH_LIB FALSE DEBUG_LIST_LIB FALSE DEBUG_PORT_LIB FALSE DEBUG_BUS_LIB FALSE DEBUG_OP_POOL FALSE DEBUG_ORACLE FALSE DEBUG_FRONTEND FALSE DEBUG_ADDR_TRANS FALSE DEBUG_BP FALSE DEBUG_BP_DIR FALSE DEBUG_BTB FALSE DEBUG_CRS FALSE DEBUG_MAP FALSE DEBUG_MEMORY FALSE DEBUG_REPLAY FALSE DEBUG_FREQ FALSE DEBUG_MODEL FALSE DEBUG_THREAD FALSE DEBUG_DECOUPLED_FE FALSE DEBUG_CONF FALSE DEBUG_ICACHE_STAGE FALSE DEBUG_DECODE_STAGE FALSE DEBUG_CPP_CACHE FALSE DEBUG_UOP_CACHE FALSE DEBUG_UOP_QUEUE_STAGE FALSE DEBUG_IDQ_STAGE FALSE DEBUG_MAP_STAGE FALSE DEBUG_NODE_STAGE FALSE DEBUG_EXEC_STAGE FALSE DEBUG_DCACHE_STAGE FALSE DEBUG_RETIRED_UOPS FALSE DEBUG_EXC_INSERTS FALSE DEBUG_BP_CONF FALSE DEBUG_ONPATH_CONF FALSE DEBUG_STREAM FALSE DEBUG_STREAM_MEM FALSE DEBUG_WAY FALSE DEBUG_L2MARKV FALSE DEBUG_L2L1PREF FALSE DEBUG_PERF_PRED FALSE DEBUG_POWER_UTILS FALSE DEBUG_DVFS FALSE DEBUG_TRACE_READ FALSE DEBUG_INST_FIELDS FALSE DEBUG_OP_FIELDS FALSE DEBUG_PIN_EXEC_DRIVEN FALSE DEBUG_CACHE_PART FALSE DEBUG_OPTIMIZER2 FALSE DEBUG_PREF FALSE DEBUG_FDIP FALSE DEBUG_EIP FALSE DEBUG_DJOLT FALSE DEBUG_FNLMMA FALSE PERFECT_BP FALSE PERFECT_BTB FALSE PERFECT_IBP FALSE PERFECT_CRS FALSE PERFECT_CBR_BTB FALSE PERFECT_NT_BTB FALSE 0 # deprecated, effectively always true. CFS_PER_CYCLE 3 6 # Number of branches that can be predicted in a single cycle UPDATE_BP_OFF_PATH FALSE 1 # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage). BP_UPDATE_AT_RETIRE FALSE 0 # Update the BP at retire. If false, update at the end of exec. BP_MECH TAGE64K_BP tage64k BP_MECH_L0 BIMODAL_BP BP_L0_LATENCY 1 BP_MAIN_LATENCY 3 BIMODAL_ENTRIES (4 * 1024) HIST_LENGTH 16 PHT_CTR_BITS 2 const BHT_ENTRIES (4 * 1024) BHT_ASSOC 4 HYBRIDS_INDEX_LENGTH 16 HYBRIDG_HIST_LENGTH 16 HYBRIDP_HIST_LENGTH 16 FILTER_INDEX_LENGTH 16 USE_FILTER FALSE INF_HYBRIDGP FALSE BP_HASH_TOS FALSE IBTB_HASH_TOS FALSE BTB_MECH GENERIC_BTB generic BTB_ENTRIES 12288 12288 BTB_ASSOC 4 4 BTB_NUM_BRSLOT 1 BTB_BLOCK_SIZE 64 BTB_OFF_PATH_WRITES TRUE 1 BTB_MAIN_LATENCY 3 3 BTB_L0_PRESENT FALSE 1 BTB_L0_ENTRIES 128 128 BTB_L0_ASSOC 4 4 BTB_L0_LATENCY 1 1 BTB_L1_PRESENT FALSE 1 BTB_L1_ENTRIES 6144 6144 BTB_L1_ASSOC 4 4 BTB_L1_LATENCY 2 2 ENABLE_CRS TRUE 1 CRS_ENTRIES 32 128 CRS_REALISTIC 0 1 ENABLE_IBP TRUE 1 # Enable the indirect branch predictor USE_PAT_HIST TRUE IBTB_MECH 1 tc_tagged IBTB_HIST_LENGTH 16 IBTB_OFF_PATH_WRITES TRUE 1 # Allow off path ops to update the ibtb. TARGETS_IN_HIST 4 TC_ENTRIES (4 * 1024) 4096 TC_ASSOC 4 4 NUM_CORR_BRANCHES 3 SEL_HIST_BP_ENTRIES 8192 SEL_HIST_LENGTH 16 SEL_HIST_DYN_CNT_TH 16 SEL_HIST_MISPRED_TH 4 ENABLE_BP_CONF FALSE CONF_MECH 0 PERF_BP_CONF_PRED FALSE BPC_BITS 16 BPC_MECH 1 BPC_CTR_RESET TRUE BPC_CIT_BITS 8 BPC_CIT_TH 50 BPC_CTR_BITS 3 OPC_COUNT_ZEROS FALSE OPC_COUNT_THRESH 10 INF_LOOP FALSE INF_LOOP_BUCKETS 811 LOOP_ENTRIES (4 * 1024) LOOP_ASSOC 4 LOOP_COUNT_MAX 127 LOOP_REPEAT_MAX 15 KNOB_PRINT_BRINFO FALSE BR_MISPRED_FILE NULL SPEC_LEVEL 3 RANDOM_DETERMINISTIC TRUE TAGESCL64KB_SC TRUE TAGESCL64KB_LOOP TRUE TAGESCL64KB_ALT TRUE CONF_PERCEPTRON_TH 0 CONF_PERCEPTRON_CTR_BITS 8 CONF_PERCEPTRON_ENTRIES 127 CONF_PERCEPTRON_THRESH_OVRD 0 CONF_HIST_LENGTH 32 PERCEPTRON_CONF_USE_CONF FALSE PERCEPTRON_CONF_TRAIN_HIS FALSE PERCEPTRON_CONF_TRAIN_CONF FALSE PERCEPTRON_CONF_TRAIN_OFFSET_CONF FALSE PERCEPTRON_TRAIN_MISP_FACTOR 1 PERCEPTRON_TRAIN_CORR_FACTOR 1 PERCEPTRON_CONF_HIS_BOTH FALSE PERCEPTRON_CONF_HIS_BOTH_LENGTH 4 MTAGE_REALISTIC_SC_40K FALSE MTAGE_REALISTIC_SC_100K FALSE H2P_TABLE_BUCKETS 16384 H2P_MIN_EXEC 5000 H2P_MIN_MISPRED 333 H2P_MISPRED_RATIO_PERMIL 10 H2P_TRACK_CBR TRUE H2P_TRACK_REP TRUE H2P_TRACK_CALL FALSE H2P_TRACK_IBR FALSE H2P_TRACK_ICALL FALSE H2P_TRACK_RET FALSE POWER_INTF_ON FALSE POWER_INTF_ENABLE_SCALING FALSE POWER_INTF_EXEC "power/power_intf.py" POWER_INTF_REF_CHIP_TECH_NM 22 POWER_INTF_REF_CHIP_FREQ (3.2e9) POWER_INTF_REF_MEMORY_FREQ (0.8e9) POWER_OTHER (0.0) PREF_STREAM_ON FALSE 1 PREF_STREAM_PER_CORE_ENABLE FALSE STREAM_BUFFER_N 16 STREAM_PREFETCH_N 2 4 STREAM_START_DIS 5 1 STREAM_LENGTH 16 64 STREAM_FULL_N 1 STREAM_TRAIN_LENGTH 16 STREAM_TRAIN_NUM 1 4 PREF_ACC_USE_CACHE FALSE STREAM_STALL_ON_QUEUE_FULL FALSE PREF_SCHEDULE_NUM 4 TRAIN_FILTER_SIZE 32 PREF_REQ_Q_SIZE 64 STREAM_CREATE_ON_DC_MISS FALSE 0 STREAM_CREATE_ON_L1_MISS TRUE 1 STREAM_TRAIN_ON_WRONGPATH TRUE STREAM_CREATE_ON_WRONGPATH TRUE STREAM_PREF_INTO_DCACHE FALSE REMOVE_REDUNDANT_STREAM FALSE L2HIT_STREAM_SCHEDULE_NUM 4 PREF_REQ_QUEUE_FILTER_ON FALSE HW_PREF_HIT_TRAIN_STREAM FALSE L2HIT_STREAM_BUFFER_N 32 L2HIT_STREAM_PREFETCH_N 2 L2HIT_STREAM_START_DIS 2 L2HIT_STREAM_LENGTH 8 L2HIT_PREF_REQ_Q_SIZE 128 L2HIT_L2ACCESS_REQ_Q_SIZE 64 PREF_STREAM_ACCPERSTREAM FALSE PREF_ACC_DISTANCE_10 128 PREF_FRAMEWORK_ON FALSE 1 PREF_TRACE_ON FALSE PREF_UMLC_ON FALSE PREF_UL1_ON TRUE PREF_DL0REQ_QUEUE_SIZE 32 PREF_UMLC_REQ_QUEUE_SIZE 64 PREF_UL1REQ_QUEUE_SIZE 128 PREF_SHARED_QUEUES TRUE PREF_DL0_MISS_ON TRUE PREF_DL0_HIT_ON TRUE PREF_DL0REQ_QUEUE_FILTER_ON TRUE PREF_UMLC_REQ_QUEUE_FILTER_ON TRUE PREF_UL1REQ_QUEUE_FILTER_ON TRUE PREF_DL0REQ_ADD_FILTER_ON TRUE PREF_UMLC_REQ_ADD_FILTER_ON TRUE PREF_UL1REQ_ADD_FILTER_ON TRUE PREF_DL0REQ_QUEUE_OVERWRITE_ON_FULL FALSE PREF_UMLC_REQ_QUEUE_OVERWRITE_ON_FULL FALSE PREF_UL1REQ_QUEUE_OVERWRITE_ON_FULL FALSE 1 PREF_DL0SCHEDULE_NUM 4 PREF_UMLC_SCHEDULE_NUM 4 PREF_UL1SCHEDULE_NUM 4 PREF_L1Q_DEMAND_RESERVE 0 PREF_REPORT_PREF_MATCH_AS_MISS FALSE PREF_REPORT_PREF_MATCH_AS_HIT TRUE PREF_UPDATE_ON_WRONGPATH TRUE PREF_TRAIN_ON_PREF_MISSES FALSE 0 PREF_ORACLE_TRAIN_ON FALSE 0 PREF_REQ_DROP FALSE PREF_THROTTLE_ON FALSE PREF_THROTTLEFB_ON FALSE 1 PREF_ACC_THRESH_1 0.90 0.75 PREF_ACC_THRESH_2 0.70 0.4 PREF_ACC_THRESH_3 0.60 0.4 PREF_ACC_THRESH_4 0.40 PREF_UPDATE_INTERVAL 0 8192 PREF_ANALYZE_LOAD FALSE PREF_POL_THRESH_1 0.25 PREF_POL_THRESH_2 0.10 PREF_POLBV_ON FALSE PREF_POLBV_SIZE 1024 PREF_TIMELY_THRESH 0.05 0.01 PREF_POLPF_THRESH 0.01 0.005 PREF_DEGFB_USEONLYACC FALSE PREF_DEGFB_USEONLYPOL FALSE PREF_DEGFB_USEONLYLATE FALSE PREF_TIMELY_THRESH_2 0.005 PREF_DEGFB_STATPHASEFILE FALSE PREF_MAX_DEGFB 4 PREF_DHAL FALSE PREF_DHAL_SENTTHRESH 16 PREF_DHAL_USETHRESH_MAX 12 PREF_DHAL_USETHRESH_MIN2 8 PREF_DHAL_USETHRESH_MIN1 4 PREF_DHAL_MAXDEG 64 PREF_HFILTER_ON FALSE PREF_HFILTER_INDEX_BITS 12 PREF_HFILTER_USE_PC FALSE PREF_HFILTER_PRED_USELESS_THRES 2 PREF_HFILTER_RESET_ENABLE FALSE PREF_HFILTER_RESET_INTERVAL 100000 EIP_ENABLE 0 L1I_ENTANGLED_TABLE_INDEX_BITS 9 L1I_ENTANGLED_TABLE_WAYS 16 DJOLT_ENABLE 0 FNLMMA_ENABLE 0 FDIP_ENABLE 1 FDIP_ALWAYS_PREFETCH FALSE PERFECT_FDIP FALSE IPRF_MAX_FTQ_ENTRY_CYC 2 FDIP_BLOOM_FILTER FALSE FDIP_BLOOM_ENTRIES 4000 FDIP_BLOOM2_ENTRIES 1000 FDIP_BLOOM4_ENTRIES 1000 FDIP_BLOOM_SIZE 16384 FDIP_BLOOM_HASHES 6 FDIP_BLOOM_CLEAR_UNUSEFUL_RATIO 0.95 FDIP_BLOOM_CLEAR_CYC_PERIOD 10000 FDIP_UTILITY_HASH_ENABLE 0 FDIP_UTILITY_PREF_POLICY 0 FDIP_ADJUSTABLE_FTQ 0 FDIP_ADJUSTABLE_FTQ_CYC 100000 UTILITY_RATIO_THRESHOLD 0.58 TIMELINESS_RATIO_THRESHOLD 0.82 FDIP_PREF_NO_LATENCY FALSE UDP_USEFUL_THRESHOLD 0 UDP_WEIGHT_USEFUL 4 UDP_WEIGHT_UNUSEFUL 1 UDP_WEIGHT_POSITIVE_SATURATION 2147483647 FDIP_GHIST_HASHING FALSE FDIP_UTILITY_ONLY_TRAIN_OFF_PATH FALSE FDIP_GHIST_BITS 8 UFTQ_MIN_FTQ_BLOCK_NUM 4 UFTQ_MAX_FTQ_BLOCK_NUM 64 FDIP_SENIORITY_FTQ_HOLD_CYC 30000 FDIP_PERFECT_PREFETCH FALSE FDIP_FREEZE_AT_MEM_BUF_LIMIT TRUE FDIP_DUAL_PATH_PREF_IC_ENABLE FALSE FDIP_DUAL_PATH_PREF_UOC_ENABLE FALSE TOP_MISPRED_BR_FILEPATH "br_resteer_coverage.csv" TOP_MISPRED_BR_RESTEER_COVERAGE 0 FDIP_DUAL_PATH_PREF_UOC_ONLINE_ENABLE FALSE FDIP_DUAL_PATH_PREF_UOC_ONLINE_MISPRED_THRESHOLD 1 FDIP_PRINT_CL_INFO FALSE BRANCH_MISPREDICTION_TABLE_SIZE 0 UOC_PREF FALSE UOC_ORACLE_PREF FALSE UOC_ZERO_LATENCY_PREF FALSE L2L1PREF_ON FALSE L2WAY_PREF FALSE L2MARKV_PREF_ON FALSE L2NEXT_PREF_ON FALSE L2HIT_STREAM_PREF_ON FALSE L2L1_DC_HIT_TRAIN FALSE L1_HIT_DUMP_FILE_ON FALSE L1_HIT_DUMP_WO_TXT FALSE L1_HIT_DUMPFILE "l1hit_dump.out" IDEAL_L2_L1_PREFETCHER FALSE IDEAL_L2_ICACHE_PREFETCHER FALSE L1WAY_PREF_SEND_QUEUE 4 L1PREF_REQ_QUEUE_SIZE 1024 L1PREF_IMMEDIATE FALSE L1WAY_PREF_TIMER_DIS 1000 L1MARKV_PREF_SEND_QUEUE 4 L1PREF_MARKV_REQ_QUEUE_SIZE 1024 MARKV_L2ACCESS_REQ_Q_SIZE 64 L1MARKV_PREF_IMMEDIATE FALSE L1MARKV_PREF_TIMER_DIS 1 L2L1_HIT_TRAIN TRUE L1MARKV_REQ_TH 1 L2L1_IMMEDIATE_PREF_CACHE FALSE L2L1_FILL_PREF_CACHE FALSE L2L1_L2_HIT_STAT FALSE PREF_GHB_ON FALSE DEBUG_PREF_GHB FALSE PREF_GHB_BUFFER_N 1024 PREF_GHB_INDEX_N 128 PREF_GHB_CZONE_BITS 12 PREF_GHB_DEGREE 16 PREF_GHB_MAX_DEGREE 32 PREF_STRIDE_ON FALSE DEBUG_PREF_STRIDE FALSE PREF_STRIDE_TABLE_N 1024 PREF_STRIDE_REGION_BITS 16 PREF_STRIDE_DEGREE 4 PREF_STRIDE_DISTANCE 16 PREF_STRIDE_STARTDISTANCE 1 PREF_STRIDE_SINGLE_THRESH 6 PREF_STRIDE_MULTI_THRESH 6 PREF_STRIDE_SINGLE_STRIDE_MODE FALSE PREF_STRIDEPC_ON FALSE DEBUG_PREF_STRIDEPC FALSE PREF_STRIDEPC_TABLE_N 1024 PREF_STRIDEPC_DEGREE 4 PREF_STRIDEPC_DISTANCE 16 PREF_STRIDEPC_USELOADADDR FALSE PREF_STRIDEPC_TRAINNUM 2 PREF_STRIDEPC_STARTDIS 4 PREF_PHASE_ON FALSE PREF_PHASE_STUDY FALSE DEBUG_PREF_PHASE FALSE PREF_PHASE_PRIME_HASH 16381 PREF_PHASE_INFOSIZE 16384 PREF_PHASE_LOG2REGIONSIZE 12 PREF_PHASE_REGIONENTRIES 64 PREF_PHASE_TRACKEDREGIONS 32 PREF_PHASE_INTERVAL 100000 PREF_PHASE_TABLE_SIZE 64 PREF_PHASE_MAXDIFF_THRESH 64 PREF_PHASE_MIN_MISSES 64 PREF_PHASE_MISSPER 0.4 PREF_2DC_ON FALSE DEBUG_PREF_2DC FALSE PREF_2DC_CACHE_SIZE (1 * 1024) PREF_2DC_CACHE_ASSOC 4 PREF_2DC_CACHE_LINE_SIZE 1 PREF_2DC_DEGREE 16 PREF_2DC_ZONE_SHIFT 10 PREF_2DC_TAG_SIZE 16 PREF_2DC_NUM_REGIONS 64 PREF_2DC_REGION_HASH 61 PREF_MARKOV_ON FALSE DEBUG_PREF_MARKOV FALSE PREF_MARKOV_NUM_ENTRIES 65536 PREF_MARKOV_NUM_NEXT_STATES 8 PREF_MARKOV_SEND_ON_PREF_HIT TRUE PREF_MARKOV_UPDATE_ON_PREF_HIT TRUE PREF_MARKOV_TABLE_UPDATE_POLICY 0 PREF_MARKOV_SEND_THRESHOLD 0