# File         : PARAMS.golden_cove
# Date         : 02/27/25
# Description  : Golden Cove Configuration
# Author       : Surim Oh <soh31@ucsc.edu>
#
# Based on documentation found here:
# https://en.wikipedia.org/wiki/Golden_Cove
# https://en.wikichip.org/wiki/intel/microarchitectures/golden_cove
# https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/3

## Simulation Parameters
--mode                          full
--model                         cmp
--sim_limit                     none

## Core Parameters

# Femptoseconds, 3.2GHz, used for energy estimates.
--chip_cycle_time               312500


### Fetch Stage
--fetch_off_path_ops            1

#### ICache
--icache_size                   32768
--icache_assoc                  8
--icache_line_size              64

### Uop Cache
# inclusive w/ L1i
--uop_cache_enable              1
--uop_cache_width               8
--uop_cache_lines               512      # 8 x 512 = 4096 uops in total (~4K)
--uop_cache_assoc               8
--iprf_on_uop_cache_hit         1

### Branch Predictor
--cfs_per_cycle                 6                         # Number of branches that can be predicted in a single cycle
--bp_update_at_retire           0                         # Update the BP at retire. If false, update at the end of exec.
--update_bp_off_path            1                         # Allow off path ops to update branch predictor state (e.g., ops when they complete exec stage).
--bp_mech                       tage64k


#### BTB

# TODO
# multi-level BTB
# 128 entry L0 BTB
# 6144 entry L1 BTB
# 12888 entry L2 BTB
# ~2 entry Return Stack
# roughly 2x8192 for now
# BTB model to use.
--btb_mech                      generic
--btb_entries                   12288
--btb_assoc                     4
--btb_main_latency              3
--btb_l0_present                1
--btb_l0_entries                128
--btb_l0_assoc                  4
--btb_l0_latency                1
--btb_l1_present                1
--btb_l1_entries                6144
--btb_l1_assoc                  4
--btb_l1_latency                2

# Allow the BTB to be updated by off path ops.
--btb_off_path_writes           1

# NT branches are not inserted in BTB, but do not trigger resteer
# since we continue without a control flow change
--perfect_nt_btb                0  # deprecated, effectively always true.

#### CRS

# Enable return stack
--enable_crs                    1
--crs_entries                   128
--crs_realistic                 1

### iBP
--enable_ibp                    1                         # Enable the indirect branch predictor
--ibtb_mech                     tc_tagged
                                                          # iBTB Model. tc_tagless, tc_tagged, tc_hybrid.
--ibtb_off_path_writes          1                         # Allow off path ops to update the ibtb.
--tc_entries                    4096
--tc_assoc                      4

### Decode Stage
--decode_width                  6
--decode_cycles                 5

### Instruction Decode Queue
--idq_size                      144

### Map Stage
--map_cycles                    5

# register renaming table
--reg_renaming_scheme               1
--reg_table_integer_physical_size   280
--reg_table_vector_physical_size    332

### Issue Stage

# Max number of instructions to be renamed, and issued per cycle.
--issue_width                   6

--rs_fill_width                 0
# rs_sizes ~205 in total, and they are split into three different reservation stations (RS1, RS2, RS3) where each has 97, 70, 38 entries respectively
# original architecture
# RS1 connected to port 0,1,5,6,10
# RS2 connected to port 2,3,11
# RS3 connected to port 7,8,4,9
# scarab does not split ST AGU port and ST port, merge them
# adjusted architecture to scarab ST AGU (port 4 and 9 removed. rs_size reduced to 186 from 205)
# RS1 connected to port 0,1,4,5,8
# RS2 connected to port 2,3,9
# RS3 connected to port 6,7 (port 4,9 removed, entries reduced to 19 from 38)
--rs_sizes                      97 70 19
--rs_connections                b0100110011 b1000001100 b0011000000
--fu_types                      b00100100111111100111001001111110010010011111110011100100111111 b10010000110111100011111001110111001000011011110001111100111011 b00000001000000001000000010000010000000100000000100000001000001 b00000001000000001000000010000010000000100000000100000001000001 b00000000110111100011011001110110000000011011110001101100111011 b01001000000000000111001001111110100100000000000011100100111111 b00000010000000010000000100000010000001000000001000000010000001 b00000010000000010000000100000010000001000000001000000010000001 b00000000000000000011001001110110000000000000000001100100111011 b00000001000000001000000010000010000000100000000100000001000001

### Exec Stage

### DCache
--dcache_size 	 	        49152
--dcache_read_ports             1
--dcache_write_ports            1
--dcache_banks                  8
--dcache_assoc		            12
--dcache_line_size              64
--dcache_cycles                 5

### Reorder/Retire Stage

# Max number of instructions to be retired per cycle.
--node_ret_width                8
--node_table_size               512

# Do not keep stores in RSVs on cache misses; TODO: confirm what this knob does
--stores_do_not_block_window    1

# TODO: confirm what this knob does
--prefs_do_not_block_window     1


## Uncore

### Mid-level cache

# Enable use of a midlevel cache between i/d and L1
# client 1.25 MiB (1310720 bytes) per core, 8-way, 15 cycles
# server 2 MiB (2097000 bytes) per core, 8-way, 16 cycles
--mlc_present                   1
--mlc_size                      2097000
--mlc_assoc                     8
--mlc_cycles                    16


### LLC
# 3 MiB per core, 16-way
--l1_size                       3145728
--l1_banks                      8
--l1_cycles		                36          // just a guess
--l1_assoc                      16
--l1_line_size                  64
--l1_interleave_factor          64


### prefetcher
# Kept same as Kaby Lake
--pref_framework_on             1
--pref_stream_on                1
--pref_train_on_pref_misses     0
--pref_oracle_train             0
--pref_ul1req_queue_overwrite_on_full 1

--stream_length                 64
--stream_prefetch_n             4
--stream_start_dis              1
--stream_train_num              4
--stream_create_on_dc_miss      0
--stream_create_on_l1_miss      1

--pref_throttlefb_on=1
--pref_acc_thresh_1=0.75
--pref_acc_thresh_2=0.4
--pref_acc_thresh_3=0.4
--pref_timely_thresh=0.01
--pref_polpf_thresh=0.005
--pref_update_interval=8192

--mem_req_buffer_pref_watermark 4
--promote_to_higher_priority_mem_req_type 1

### Memory
# Kept same as Kaby Lake
--addr_translation		random

--mem_priority_ifetch        0
--mem_priority_dfetch        1
--mem_priority_dstore        2
--mem_priority_iprf          3
--mem_priority_dprf          4
--mem_priority_wb            5
--mem_priority_wb_nodirty    5

--mem_req_buffer_entries        32
--bus_width_in_bytes            8

--ramulator_standard		DDR4
--ramulator_speed		DDR4_2400R
--ramulator_org 		DDR4_8Gb_x8
--ramulator_channels		1
--ramulator_ranks		1
--ramulator_bankgroups		4
--ramulator_banks		4
--ramulator_chip_width		8
--ramulator_rows		65536
--ramulator_cols		1024
--ramulator_scheduling_policy	FRFCFS_Cap
--ramulator_readq_entries	32
--ramulator_writeq_entries	32
--ramulator_record_cmd_trace	FALSE
--ramulator_print_cmd_trace	FALSE
--ramulator_tCK			833333
--ramulator_tCL			16
--ramulator_tCCD		6
--ramulator_tCCDS		4
--ramulator_tCCDL		6
--ramulator_tCWL		12
--ramulator_tBL			4
--ramulator_tWTR		9
--ramulator_tWTRS		3
--ramulator_tWTRL		9
--ramulator_tRP			16
--ramulator_tRPpb		16
--ramulator_tRPab		16
--ramulator_tRCD		16
--ramulator_tRCDR		16
--ramulator_tRCDW		16
--ramulator_tRAS		39
--dram_tech_in_nm		32

## Other


### Debug
--debug_inst_start              0
--debug_inst_stop              -1
--debug_cycle_start             0
--debug_cycle_stop             -1


## Stats and Params
--dump_params                   1
--dump_stats                    1
--dump_trace                    0

####################################
--set_off_path_confirmed        1

--order_beyond_bus              1

--mem_ooo_stores                1
--mem_obey_store_dep            1