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# A Literature Review On Variability In Semiconductor Manufacturing: The Next Forward Leap To Industry 4.0.
Kean Dequeant1,2
Philippe Vialletelle1
Pierre Lemaire2
Marie-Laure Espinouse2
1STMicroelectronics, F-38926, Crolles Cedex, FRANCE
2Univ. Grenoble Alpes, CNRS, G-SCOP, 38 000 Grenoble, FRANCE
## Abstract
Se... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
## 1 **Introduction**
Industry 4.0 is said to be the next industrial revolution. The proper use of real-time information in complex manufacturing systems is expected to allow more customization of products in highly flexible production factories. Semiconductor High Mix Low Volume (HMLV) manufacturing facilities (calle... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
As these types of projections are made considering finite horizons (e.g., see Mhiri et al. 2014), the dynamic cycle time models to develop are closer to clearing functions (see Kacar et al. 2012) than queuing theory. Using historical data to derive these models is not appropriate, since the behavior of the toolsets cha... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
The literature of variability in semiconductor manufacturing focuses on efficiency: In this context, we interpret variability as everything responsible for efficiency losses by means of non-productive waiting times. What we therefore call the intrinsic variability of a manufacturing system (which we will simply refer t... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
## 2 The Complexity **Of Semiconductor Manufacturing** 2.1 Overview Of **Semiconductor Manufacturing**
Traditional production or assembly lines are usually organized to build products starting from raw materials or components, progressively transforming or assembling them in order to deliver "end products" or "finishe... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
The second characteristic of semiconductor manufacturing is that it involves different types of physical processes that require different types of machines (see Mönch et al. 2011). Batching machines, such as deposition or diffusion furnaces for example, will process products in batches of different minimum and maximum ... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
A third characteristic of semiconductor fabs is the business model they use. While High Volume Low Mix units usually produce in the range of 3 to 4 different products at the same time over one or two
different technology generations, High Mix fabs propose a wide variety of products to their customers over several tec... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
## 2.2 **Impact Of Variability**
As utilization, as well as variability, also creates higher cycle times, one way to visualize the intrinsic variability of a manufacturing system is through "operational curves" or "cycle time throughput curves". These curves are found in 20 of the papers that we reviewed, and used in ... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
Figure 1: Operating curves showing different levels of variability (1.A) and the link to capacity loss (1.B).
Moreover, for a given maximum allowed Xfactor value, the maximum allowed capacity utilization decreases as the variability increases, which directly translates into capacity lo... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
| Table 1: Sources of variability identified by authors related to the variability of semiconductor | | | | | |
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| structural | tonstraints betwee | | | | |
| | ence spe... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
| | owntime | roduct mi | riorities | | |
| References | atchin ... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
| Wu (2005) | | | | | |
| Delp et al. (2006) | ... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
| Zisgen et al. (2008) | | | | | |
| Wu and Hui (2008) | ... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
| Leachman (2012) | | | | | |
| Tirkel (2013) | ... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
The sources of variability of a manufacturing system can be defined as the primary factors that create, amplify, and propagate the local uncontrolled over-saturations of the system. We emphasize the fact that, given this definition, sources of variability do not *need* to be variable themselves. As there may be an unli... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
## 3 Literature Review On The Sources **Of Variability** 3.1 **Equipment-Specific Factors**
Natural process time, also referred to as raw processing time or theoretical processing time is, in a simplified manner, the time spent processing each lot on the machine. In the semiconductor environment, the definition become... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
Batching is another equipment-specific characteristic. Most authors recognize the cycle time increase due to batching, and specific queuing equations for batch processes are actually proposed by Huang et al. (2001), Hanschke (2006), Brown et al. (2010), and Leachman (2012). Batches add variability to their toolset, but... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
Tool redundancy is the simplest of examples, as it is found in many manufacturing systems and is measurable: the number of parallel tools that process a given process step. Increasing the redundancy smoothens the capacity of the toolset as tools are generally independent and the breakdowns happen more evenly. The redun... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
Figure 2: Product mix processed by different tools of a toolset over time.
Reentrancy is another, more global, structural factor. As resources interact locally through their redundancy, dedication and heterogeneity, they interact globally in the flow of products. As a part of the manuf... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
## 3.3 Product Induced **Factors**
The impact of product mix can be understood straightforwardly now that we have discussed batches,
 setups and reentrancy. More products mean more recipes on identical tools. Just as reentrancy adds more product *levels* to toolsets, higher product mix... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
Product mix and priorities therefore both have a great impact on the cycle times observed at the different toolsets. As High Mix fabs operate in a *make-to-order* policy, the product mix is thus a very important source of variability as it is continually changing to follow the fluctuations of the demand.
## 3.4 **Ope... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
WIP control strategies are especially important. As some authors have reported, tool downtimes and product arrivals may not be independent because of specific WIP control strategies where production teams push back non-critical maintenance operations in case of high arrival rates.
## 2604 4 The Challenges **Of Integr... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
Figure 4 shows that this second assumption is not always true. Figure 4.A shows the number of arrivals per week at a toolset from STMicroelectronics Crolles300 fab, and Figure 4.B shows arrivals per week generated using the same inter-arrival rate as in Figure 4.A, but assuming independence of arrivals. Figure 4 shows ... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
# 
the processing times resulting follow a time-dependent (autocorrelated) sequence: Ten lots in a row might be processed with a degraded processing time. This temporarily reduces the toolset capacity, creating more over-saturations. This extra variability created by the dependency of th... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
Following the work of Hopp et al. (2007), we intend to develop a Diagnostic Tree of the sources of variability. On top of referencing, for each toolset, the identified sources of variability, one objective of this Diagnostic Tree is to keep track of the root causes of each source as well as the statistics chosen to mod... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
Even though the component market is dominated by a few major players, thousands of production facilities exist through the world. And these factories will continue to produce components in the future due to the pervasion of electronics in every aspect of our lives, the "digitization" of everything. Besides traditional ... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
Piscataway, New Jersey: Institute of Electrical and Electronics Engineers, Inc.
Delp, D., J. Si, and J. W. Fowler. 2006. "The Development of the Complete X-Factor Contribution Measurement for Improving Cycle Time and Cycle Time Variability." IEEE Transactions on Semiconductor Manufacturing 19:352-362.
Etman, L. F., C... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
Ignizio, J. P. 2009a. "Cycle Time Reduction Via Machine-To-Operation Qualification." *International* Journal of Production Research 47:6899-6906.
Ignizio, J. P. 2009b. *Optimizing factory performance*. New York: McGraw-Hill. Ignizio, J. P. 2011. "Estimating the Sustainable Capacity of Semiconductor Fab Workstations.... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
Mhiri, E., M. Jacomino, F. Mangione, P. Vialletelle, and G. Lepelletier. 2014. "A Step Toward Capacity Planning at Finite Capacity in Semiconductor Manufacturing." In Proceedings of *the 2014 Winter* Simulation Conference, edited by A. Tolk, S. Y. Diallo, I. O. Ryzhov, L. Yilmaz, S. Buckley, and J.
A. Miller, 2239-22... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
Rowshannahad, M., S. Dauzère-Pérès, and B. Cassini. 2014. "Qualification Management to Reduce Workload Variability in Semiconductor Manufacturing." In *Proceedings of the 2014 Winter* Simulation Conference, edited by A. Tolk, S. Y. Diallo, I. O. Ryzhov, L. Yilmaz, S. Buckley, and J. A. Miller, 2434-2443. Piscataway, Ne... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
Whitt, W. 1993. "Approximations for the GI/G/M Queue." *Production and Operations Management* 2:114-161.
Wu, K. 2005. "An Examination of Variability and Its Basic Properties for a Factory." IEEE Transactions on Semiconductor Manufacturing 18:214-221.
Wu, K., and K. Hui. 2008. "The Determination and Indetermination of... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
MARIE-LAURE ESPINOUSE is a full professor in the Department of electrical engineering and industrial computing at the Institute of Technology of the Grenoble-Alpes university, France. She received a Ph.D. degree and an habilitation in computer science from the university Joseph Fourier, Grenoble, France. She has a stro... | text_only | 0_A_literature_review_on_variability_in_semiconductor_manufacturing_The_next_forward_leap_to_Industry_ | ||
# New Passivating Chemistries For The Deep Etching Of Through Silicon Vias
William L. Nicoll, Eric Eisenbraun, and Rahul Gupta Abstract-This paper investigated a number of environmentally friendly fluorocarbon and hydrofluorocarbon (HFC) gas chemistries for sidewall passivation during time-multiplexed plasma etch proc... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
Finally, as the number of TSVs on a chip increases, it is essential that the mask pattern of these TSVs is etched anisotropically, without a large horizontal etch rate into neighboring structures. These three requirements demand an etch process that delivers competitive etch rates, good photoresist selectivity, smooth ... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
This study investigates passivation gas alternatives to C4F8 in the time-multiplexed or Bosch silicon etch process. The performance of four fluorocarbon and/or hydrofluorocarbon
(collectively referred to as "HFC") gases is characterized, and their environmental merits will be briefly discussed.
## Ii. Experimental Set... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
Growth rate of thick HFC films deposited on pre-etched structures Fig. 3.
by C4F8 and the HFC test gases. Film thickness was measured along the top, bottom, and sidewall of the trench. All four test gases demonstrated higher deposition rates vs. C4F8, although HFC 1 deposited more poly... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
## A. Deposition And Etch On Planar And Structured Samples
Before etching trenches, a growth and etch rate study was carried out on films deposited on planar silicon surfaces as well as pre-etched TSV structures. The film's growth and etch rates on different parts of the trench as well as the film's chemical structure... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
Before depositing the HFC films, some predictions can be made regarding their performance. All four test gases had lower F/C ratios than C4F8, so our gases would be expected to show high polymerization rates [5], which we see from the planar deposition rates in Fig. 3 (note that HFC 1's deposition took place mostly on ... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
Etch rate of thick HFC films exposed to a SF6/Ar plasma. High Fig. 5.
trench bottom etch rates are desired for depassivation. Experimental conditions: 850W power, 30W bias, 100 sccm SF6, 40 scem Ar, 23 mT pressure, 2.5 minutes etch time.
TABLE I
OPTIMIZED TSV ETCH RECIPES
| Bosch Cyc... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
When these same films are exposed to a typical Bosch etch chemistry such as an Ar/SF6 plasma, physical and chemical etching alter the structure of the film, which could impact its ability to serve as a passivation barrier on the sidewalls.
As seen in Fig. 4, HFCs 1, 2, and 4 all show indications of reductions in cross... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
Example 2 um trench structures produced using C4F8 (bottom) and Fig. 6.
our test gases at 25 seem HFC / 9 sec deposition pulse time. The high trench bottom/sidewall deposition rate of HFC 3 caused the walls to narrow in width as etching progressed. Scale bar is 10 um.
Fig. 7.
Silicon... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
Silicon:Resist selectivity vs. passivating gas flowrate for C4F8 and Fig. 8.
other HFC gases. These gases tended to demonstrate higher selectivity due to the higher planar HFC film deposition rates protecting the mask from erosion.
Shown are data from ... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
The optimum passivating gas flowrate for our test recipes was below that typically used in our ICP chamber with C4F8, but the gases showed overlapping ideal process windows at 25 sccm HFC gas flowrate. Some of the gas mixtures had difficulty with ignition at 10 sccm HFC gas flowrate, and some
Results from AFM roughness scans of... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
The biggest hurdle anticipated in deploying such high deposition rate gases in the manufacturing environment is their tendency to quickly coat the chamber walls with polymer residue, which can lead to defect-inducing flakes, longer clean times, and process variations. One group attempted to use oxygen in high-growth HF... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
It has also been shown by previous work that alternative HFC passivating gases have a much lower GWP versus C4F8.
Although chamber wall polymerization remains a concern, recipes with low passivating gas fraction and deposition step times have demonstrated it can be minimized.
## References
[1] P. Forster, V. Ramaswa... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
[7]
C. B. Labelle, V. M. Donnelly, G. R. Bogart, R. L. Opila, and A.
Kornblit, "Investigation of fluorocarbon plasma deposition from C4F8 for use as passivation during deep silicon etching," J. Vac. Sci. Technol.
A, vol. 22, no. 6, pp. 2500-2507, 2004.
[8] M. A. Blauw, T. Zijlstra, and E. van der Drift, "Balancing t... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
Mr. Nicoll was an Invited Speaker at the Advanced Semiconductor Manufacturing Conference in 2012. He was the recipient of the AIChE Pittsburgh Section Scholarship Award in 2006 and received the Charlemagne Stipendium in 2005 to fund studies at RWTH Aachen, Aachen, Germany.
Eric Eisenbr... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
Dr. Eisenbraun received his Ph.D. in Physics from the University at Albany, and his B.S. in Physics from Rensselaer Polytechnic Institute. Prior to UAlbany, Professor Eisenbraun was Chief Scientist at Tokyo Electron (TEL) Massachusetts, and a Process Engineer at Lam Research. He has over twenty years experience in nano... | text_only | 10_New_Passivating_Chemistries_for_the_Deep_Etching_of_Through_Silicon_Vias | ||
RESEARCH ARTICLE | MAY 01 2001 Profile evolution during polysilicon gate etching with lowpressure high-density plasma chemistries Cl2 /HBr/O2 Mutumi Tuda; Kenji Shintani; Hiroki Ootera J. Vac. Sci. Technol. A 19, 711–717 (2001)
https://doi.org/10.1116/1... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
Profile evolution during polysilicon gate etching has been investigated with low-pressure high-density Cl2 /HBr/O2 plasma chemistries. Etching was performed in electron cyclotron resonance Cl2 /HBr/O2 plasmas as a function of HBr percentage in a Cl2 /HBr mixture, using oxide-masked poly-Si gate structures. The linewidt... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
## I. Introduction
As the device feature size continues to be scaled down, increasingly severe requirements are being imposed on plasma etching technology, including etch anisotropy, profile control, feature size or critical dimension ~CD! control relative to the mask width, and etch selectivity to the mask materials ... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
This article presents some aspects of plasma–surface interactions in microstructures during etching of poly-Si gates with low-pressure high-density Cl2 /HBr/O2 plasma chemistries. Etching was performed in electron cyclotron resonance
~ECR! Cl2 /HBr/O2 plasmas as a function of percentage of HBr added, using oxide-masked... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
## Ii. Etch Experiments A. Plasma Reactor And Samples For Etching
Etch experiments were performed using an ECR plasma reactor, described in detail elsewhere.13,16,19 Briefly, a resonance magnetic field of 875 G was located '5 cm downstream of a quartz microwave window, and a wafer stage was placed '20 cm from the wind... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
The etch rates of poly-Si and SiO2 were determined from their thicknesses in an open field, measured at 13 points per wafer using an optical film thickness measurement instrument. In measurements of the SiO2 etch rate, blanket SiO2 films, deposited over a Si wafer by chemical vapor deposition, were used. The linewidth ... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
## B. Etching Characteristics
Figure 1 shows the macroscopic etch rates of poly-Si and SiO2 in Cl2 /HBr/O2 plasmas as a function of HBr percentage in a Cl2 /HBr mixture. Also shown in this figure is the etch
FIG. 1. Macroscopic etch rates of poly-Si and SiO2 in Cl2 /HBr/O2 plasmas
as... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
The etching of SiO2 in Cl2 /HBr/O2 plasmas stops almost completely at an HBr percentage above ;80%. As a result, the etch selectivity of poly-Si over SiO2 increases significantly with increasing HBr percentage. It is further noted that under these conditions, the uniformity of the poly-Si etch rate was less than '3% ov... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
The spatial distributions of DL for isolated lines over a wafer are plotted in Fig. 3, for different HBr percentages in Cl2 /HBr. For Cl2 /O2 plasmas without HBr addition, DL is almost independent of the radial position. However, for HBr/O2 plasmas, DL exhibits a maximum at around the center of the wafer.
Figure 4 sho... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
FIG. 3. Spatial distributions of the linewidth shift DL for isolated poly-Si
lines etched in Cl2 /HBr/O2 plasmas for different HBr percentages in Cl2 /HBr:Cl2 /O2, Cl2/70%-HBr/O2, and HBr/O2 plasmas. Note that DL indicates the degree of sidewall tapering of poly-Si lines.
FIG. 4. Line... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
As mentioned above, the linewidth shifts DLs obtained in Cl2 /O2 and HBr/O2 plasmas are large because of strongly tapered sidewalls. However, we can see an apparent difference in these sidewall features: for Cl2 /O2 plasmas, the sidewalls exhibit curved tapering near the bottom; on the other hand, for HBr/O2 plasmas, t... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
However, the simultaneous redeposition of etch products directly arriving from the surface being etched is considered to remain almost unchanged. The results are shown in Figs. 7 and 8.
Figure 7 shows the normalized etch rates of poly-Si in Cl2 /HBr/O2 plasmas as a function of macroscopic open space of the oxide-maske... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
## Iii. Discussion
For a better understanding of the etched profiles in Cl2 /HBr/O2 plasmas, we carried out numerical profile simu-
FIG. 6. Cross-sectional SEM micrographs of poly-Si line-and-space features
etched in an HBr/O2 plasma ~a! before and ~b! after the removal of deposited ... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
FIG. 8. Linewidth shifts DLs for isolated lines of poly-Si as a function of macroscopic open space of the oxide-masked sample, etched in Cl2 /HBr/O2 plasmas for different HBr percentages in Cl2 /HBr:Cl2 /O2, Cl2/70%-HBr/O2, and HBr/O2 plasmas. Note that DL indicates the degree of sidewall tapering of poly-Si lines. | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
count the fact that the particle flux into a microstructure is generally reduced by geometrical shadowing effects of the mask. The ion flux Gi was obtained by integrating the incident angular distribution of ions, which was derived from the time-independent collisionless sheath theory,20 the angular distribution was de... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
a sticking probability Splasma . Thus, the incident flux Gp of etch products was obtained by adding the flux Gsurface coming from the other nodal points on the surface and the flux Gplasma coming from the plasma.13,21 Figures 9~a! and 9~b! show simulated etched profiles with effects of redeposition of etch products des... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
FIG. 9. Simulated etched profiles ~a! with effects of redeposition of etch
products desorbed from the surface, and ~b! with effects of deposition of etch products or inhibitors coming from the plasma. The sticking probabilities of etch products are Ssurface50.15 in ~a!, and Ssurface50 ... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
In etching of poly-Si with HBr/O2 plasmas, as already shown in Fig. 4, the linewidth shift DL increased considerably with an increase of microscopic line spacing: preferential sidewall tapering occurred for wider pattern features.
Furthermore, DL or the degree of sidewall tapering increased with an increase of macrosc... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
Regarding the etched profiles obtained in Cl2 /O2 plasmas, the sidewall features exhibited curved tapering, and the degree of tapering was almost independent of the microscopic and macroscopic poly-Si open spaces, as shown in Figs. 4 and 8. Thus, the curved sidewalls formed in Cl2 /O2 plasmas are considered to be intri... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
These angular dependencies YSi(u) of the etch yield are shown in Fig. 11, where the incidence angle u of ions is
FIG. 11. Angular dependencies YSi(u) of the Si etch yield used in Fig. 10,
where the incidence angle u of ions is respect to the normal of the surface being etched.
respect... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
## Iv. Conclusions
Profile evolution during poly-Si gate etching has been investigated with low-pressure high-density Cl2 /HBr/O2 plasma chemistries. Etching was performed in ECR
Cl2 /HBr/O2 plasmas as a function of percentage of HBr added, using oxide-masked poly-Si gate structures with a variety of microscopic and m... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
## Acknowledgments
The authors are deeply grateful to H. Kimura and H.
Miyatake for providing the samples and for many fruitful discussions. They also thank T. Nishiura, R. Yoshifuku, R. Obara, and H. Sawai for helpful discussions.
1*ULSI Technology*, edited by C. Y. Chang and S. M. Sze ~McGraw-Hill, New York, 1996!... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
Nguyen, Y. Melaku, D. Gates, and M. Ben-Dor, J. Vac. Sci. Technol. A
11, 1301 ~1993!. 15K. Harafuji, M. Ohkuni, M. Kubota, H. Nakagawa, and A. Misaka, Technical Digest 1995 International Electron Devices Meeting, Washington, 1995 ~IEEE, New York, 1995!, p. 105. 16M. Tuda, K. Shintani, H. Kimura, S. Tomohisa, and H. Oot... | text_only | 11_Profile evolution during polysilicon gate etching with low-pressure high-density cl2 hbr o2 plasma | ||
# Sidewall Dominated Characteristics On Fin-Gate Algan/Gan Mos-Channel-Hemts
Shinya Takashima, *Member, IEEE*, Zhongda Li, *Student Member, IEEE*, and T. Paul Chow, *Fellow, IEEE*
Abstract— The fin-gate structure was fabricated onto AlGaN/GaN MOS channel-high electron mobility transistors
(MOSC-HEMTs), and the fin sid... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
Index Terms— Fin-FET, Gallium nitride (GaN), high electron mobility transistor (HEMT), MOS, short channel.
## I. Introduction
GALLIUM nitride (GaN) is a promising material for high-power and low-loss electronics because of its wide bandgap energy and large critical electric field [1], and AlGaN/GaN high electron mobi... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
Z. Li and T. P. Chow are with Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY 12180 USA (e-mail: [email protected]; [email protected]).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2013.... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
In this paper, we researched the sidewall contribution to the MOS channel characteristics in fin-gate MOSC-HEMTs (FinMOSC-HEMTs). Fin-MOSC-HEMTs with 120-nm fin width show significant suppression of short channel effects, but the Vth becomes lower than that of conventional MOSC-HEMTs because of the depletion mode natur... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
MOSC-HEMT devices both with and without fin structure were fabricated on same GaN-on-Si wafer. Fig. 1(a) shows schematic device cross-section, where only channel length Lch was changed in the sets of different Lch devices. The highvoltage epi is used for the purpose of the future application to power devices, the struc... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
The device fabrication started with initial solvent degrease clean, followed by deep mesa isolation to define device area. Before fin structure, gate recess was patterned by e-beam lithography with plasma enhanced chemical vapor deposited SiO2 mask; then etching with chlorine-based inductively coupled plasma reactive i... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
isolate gate and source/drain, then densified at 900 °C for 30 min in N2. Ohmic contacts were formed by evaporation of Ti/Al/Ni/Au and patterned by liftoff technique, followed by a rapid thermal annealing under 800 °C for 1 min in N2.
Finally, Ti/Al was evaporated and patterned as inte... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
For conventional MOSC-HEMTs, Id curve starts increasing from more negative voltage when the channel length becomes shorter.
The threshold voltage is defined as the gate bias intercept of the linear extrapolation of drain current. The fitting is done at the point where Id shows the highest slope. Extracted Vth is shown... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
Fig. 2.
Channel length variation of La-Vg transfer characteristics for (a) MOSC-HEMTs without fin structure and (b) Fin-MOSC-HEMTs with 120-mwidth fin structure. Both measurements were performed under Vg = 0.1 V at room temperature. (c) Channel length dependence of extracted Vig on our... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
Fig. 5.
Breakdown characteristics for Lch = 0.3-um MOSC-HEMT and Fin-MOSC-HEMT with 120-nm fin. Gate bias of Vg = - 2 V was used.
finite output conductance because of DIBL effect. Pulsed gate bias testing was also performed and higher output currents than those of dc gate bias condition were observed as shown in Fig. ... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
Fig. 6. Fin width dependence of (a) Id –Vg transfer characteristics under Vd = 0.1 V at room temperature and (b) extracted Vth.
mode, narrow fin structure helps depleting the channel inside of the fin, giving an increase of threshold voltage. However, when the sidewall shows depletion m... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
The fin top surface is Ga-faced, polar (0001) c-plane, which has negative polarization charges [19]. On the other hand, the polarization charges are thought to be lost on the sidewalls created by mesa trench because of almost vertical orientation
Fig. 7. Channel length dependence of device RON. RON was extracted from
... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
## C. Mos Channel Sheet Resistance
MOS channel sheet resistance can be extracted from RON
dependence on recessed channel lengths. RON is calculated from the slope of the output Id –Vd characteristics between Vd = 0 and 1 V under Vg − Vth = 6.8 V to take account of Vth change. The slope gives MOS channel sheet resistan... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
The intercepts in Fig. 7 show series resistance consisted of contact resistance and 2-DEG resistance between source-togate and gate-to-drain regions. As shown in Fig. 1, the mesa trenches over the gate recess line have an overlap of 0.5 μm on both source and drain sides in our devices. Because of the fin structure crea... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
In addition, it is effective to decrease fin pitch for achieving low RON in terms of increasing effective channel width in MOS gate region and effective 2-DEG width in overlapped fin structure on 2-DEG region. The device performance of FinMOSC-HEMTs can be further improved through optimizing these parameters.
## D. Tr... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
## E. Temperature Effect
Finally, we also investigated the temperature effect on Vth for MOSC-HEMT and Fin-MOSC-HEMT. Fig. 9(a) and
(b) shows Id –Vg transfer characteristics on Lch = 1.1-μm devices with temperature. Both the MOSC-HEMT and Fin-MOSC-HEMT show a drain current decrease with elevating temperature, because ... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
There is a clear difference in their threshold voltage behavior between the MOSC-HEMT and the Fin-MOSCHEMT as shown in Fig. 9(c). The conventional MOSC-HEMT
shows complex temperature dependence as initial increase, then decrease, and secondary increase, which is consistent with [25]. By contrast, Vth on Fin-MOSC-HEMT i... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
## Iv. Conclusion
The sidewall contribution to the MOS channel characteristics in Fin-MOSC-HEMTs was investigated. Whereas the Fin-MOSC-HEMTs with 120-nm fin width showed significant suppression of short channel effects, the Vth became lower than that of conventional MOSC-HEMTs because of the depletion mode nature of ... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
[3] H. Kambayashi, Y. Satoh, S. Ootomo, T. Kokawa, T. Nomura, S. Kato, and T. P. Chow, "Over 100 A operation normally-off AlGaN/GaN hybrid MOS-HFET on Si substrate with high-breakdown voltage," Solid-State Electron., vol. 54, pp. 660–664, Jun. 2010.
[4] B. Lu, O. I. Saadat, and T. Palacios, "High-performance integrate... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
[10] T. Zimmermann, Y. Cao, J. Guo, X. Luo, D. Jena, and H. G. Xing, "Topdown AlN/GaN enhancement- & depletion-mode nanoribbon HEMTs,"
in *Proc. Device Res. Conf.*, 2009, pp. 129–130.
[11] K.-S. Im, R.-H. Kim, K.-W. Kim, D.-S. Kim, C. S. Lee, S. Cristoloveanu, and J.-H. Lee, "Normally off single-nanoribbon Al2O3/GaN M... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
2003.
[17] Z.-Q. Fang, D. C. Look, X.-L. Wnag, J. Han, F. A. Khan, and I. Adesida, "Plasma-etching-enhanced deep centers in n-GaN grown by metalorganic chemical-vapor deposition," *Appl. Phys. Lett.*, vol. 82, pp. 1562–1564, Mar. 2003.
[18] K. Tang, W. Huang, and T. P. Chow, "GaN MOS capacitors and FETs on plasma-etc... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
[24] K. Matocha, T. P. Chow, and R. J. Gutmann, "High-voltage normally off GaN MOSFETs on sapphire substrates," *IEEE Trans. Electron Devices*,
vol. 52, no. 1, pp. 6–10, Jan. 2005.
[25] J. Zhang, C. Hitchcock, Z. Li, and T. P. Chow, "Investigation of pyroelectric polarization effect on GaN MOS capacitors and field-eff... | text_only | 12_Sidewall_Dominated_Characteristics_on_Fin-Gate_AlGaN_GaN_MOS-Channel-HEMTs | ||
RESEARCH ARTICLE | APRIL 09 2015 Silicon etching in a pulsed HBr/O2 **plasma. II. Pattern transfer**
Moritz Haass; Maxime Darnon; Gilles Cunge; Olivier Joubert J. Vac. Sci. Technol. B 33, 032203 (2015)
https://doi.org/10.1116/1.4917231
Articles You May Be Interested In Atomic-scale si... | text_only | 13_Silicon etching in a pulsed HBr_O2 plasma. II. Pattern transfer. | ||
## I. Introduction
Plasmas composed of HBr/O2 are often used for silicon etch processes such as gate etch processes or shallow trench isolation etching and, because silicon etching in such chemistries is rather well understood, it is a perfect candidate to study the impact of plasma pulsing upon the gas phase and the ... | text_only | 13_Silicon etching in a pulsed HBr_O2 plasma. II. Pattern transfer. | ||
Many authors have investigated the etch mechanisms in HBr/O2 plasmas for silicon and SiO2.
5–13 The fundamental mechanisms for Si and SiO2 etching are summarized in the following, wherein a very small percentage of oxygen in the feed gas stock is considered. Bromine-, hydrogen-, and, to a minor extent, also oxygen-con... | text_only | 13_Silicon etching in a pulsed HBr_O2 plasma. II. Pattern transfer. | ||
In contrast to silicon etching, SiO2 is etched very slowly.
Because the formation of Si–O bonds is thermodynamically favored compared to Si–Br bonds, chemically enhanced etching of SiO2 is minimized. Oxygen atoms are preferentially sputtered from the surface,11,14 leaving free spaces for Br to form Si–Br bonds and, su... | text_only | 13_Silicon etching in a pulsed HBr_O2 plasma. II. Pattern transfer. | ||
In comparison, the silicon etching yield is strongly enhanced by a large surface coverage of Br radicals and the activation energy is rather low, while the SiO2 etching needs quite a lot of activation energy even if the surface is fully covered with Br radicals.15 Therefore, it is likely that, in most process condition... | text_only | 13_Silicon etching in a pulsed HBr_O2 plasma. II. Pattern transfer. |
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